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https://github.com/YosysHQ/yosys
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WIP
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parent
afdae7b87e
commit
c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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@ -37,7 +37,7 @@ struct ExclusiveDatabase
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SigBit y_port;
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pool<Cell*> reduce_or;
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for (auto cell : module->cells()) {
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if (cell->type == ID($eq)) {
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if (cell->type == TW($eq)) {
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SigSpec y_sig = sigmap(cell->getPort(TW::Y));
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if (GetSize(y_sig) == 0)
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continue;
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@ -50,7 +50,7 @@ struct ExclusiveDatabase
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}
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y_port = y_sig[0];
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}
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else if (cell->type == ID($logic_not)) {
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else if (cell->type == TW($logic_not)) {
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SigSpec y_sig = sigmap(cell->getPort(TW::Y));
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if (GetSize(y_sig) == 0)
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continue;
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@ -58,7 +58,7 @@ struct ExclusiveDatabase
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const_sig = Const(State::S0, GetSize(nonconst_sig));
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y_port = y_sig[0];
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}
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else if (cell->type == ID($reduce_or)) {
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else if (cell->type == TW($reduce_or)) {
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reduce_or.insert(cell);
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continue;
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}
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@ -152,11 +152,11 @@ struct MuxpackWorker
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for (auto cell : module->cells())
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{
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if (cell->type.in(ID($mux), ID($pmux)) && !cell->get_bool_attribute(ID::keep))
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if (cell->type.in(TW($mux), TW($pmux)) && !cell->get_bool_attribute(ID::keep))
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{
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SigSpec a_sig = sigmap(cell->getPort(TW::A));
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SigSpec b_sig;
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if (cell->type == ID($mux))
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if (cell->type == TW($mux))
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b_sig = sigmap(cell->getPort(TW::B));
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SigSpec y_sig = sigmap(cell->getPort(TW::Y));
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@ -193,10 +193,10 @@ struct MuxpackWorker
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{
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for (auto cell : candidate_cells)
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{
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log_debug("Considering %s (%s)\n", cell, cell->type.unescape());
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log_debug("Considering %s (%s)\n", cell, cell->type.unescaped());
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SigSpec a_sig = sigmap(cell->getPort(TW::A));
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if (cell->type == ID($mux)) {
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if (cell->type == TW($mux)) {
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SigSpec b_sig = sigmap(cell->getPort(TW::B));
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if (sig_chain_prev.count(a_sig) + sig_chain_prev.count(b_sig) != 1)
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goto start_cell;
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@ -204,7 +204,7 @@ struct MuxpackWorker
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if (!sig_chain_prev.count(a_sig))
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a_sig = b_sig;
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}
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else if (cell->type == ID($pmux)) {
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else if (cell->type == TW($pmux)) {
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if (!sig_chain_prev.count(a_sig))
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goto start_cell;
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}
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@ -289,7 +289,7 @@ struct MuxpackWorker
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s_sig.append(cursor_cell->getPort(TW::S));
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}
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else {
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log_assert(cursor_cell->type == ID($mux));
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log_assert(cursor_cell->type == TW($mux));
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b_sig.append(cursor_cell->getPort(TW::A));
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s_sig.append(module->LogicNot(NEW_TWINE, cursor_cell->getPort(TW::S)));
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}
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