mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-19 05:35:47 +00:00
Code Activity

WIP

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
Download patch file Download diff file Expand all files Collapse all files

8
passes/memory/memory_share.cc
View file

@ -80,7 +80,7 @@ struct MemoryShareWorker
if (GetSize(mem.rd_ports) <= 1)
return false;
log("Consolidating read ports of memory %s.%s by address:\n", module, mem.memid.unescape());
log("Consolidating read ports of memory %s.%s by address:\n", module, design->twines.unescaped_str(mem.memid));
bool changed = false;
int abits = 0;
@ -197,7 +197,7 @@ struct MemoryShareWorker
if (GetSize(mem.wr_ports) <= 1)
return false;
log("Consolidating write ports of memory %s.%s by address:\n", module, mem.memid.unescape());
log("Consolidating write ports of memory %s.%s by address:\n", module, design->twines.unescaped_str(mem.memid));
bool changed = false;
int abits = 0;
@ -316,7 +316,7 @@ struct MemoryShareWorker
if (eligible_ports.size() <= 1)
return;
log("Consolidating write ports of memory %s.%s using sat-based resource sharing:\n", module, mem.memid.unescape());
log("Consolidating write ports of memory %s.%s using sat-based resource sharing:\n", module, design->twines.unescaped_str(mem.memid));
// Group eligible ports by clock domain and width.
@ -482,7 +482,7 @@ struct MemoryShareWorker
sigmap_xmux = sigmap;
for (auto cell : module->cells())
{
if (cell->type == ID($mux))
if (cell->type == TW($mux))
{
RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(TW::A));
RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(TW::B));