mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-20 22:25:49 +00:00
WIP
This commit is contained in:
parent
afdae7b87e
commit
c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
|
|
@ -60,7 +60,7 @@ struct MemoryMemxPass : public Pass {
|
|||
{
|
||||
if (port.clk_enable)
|
||||
log_error("Memory %s.%s has a synchronous read port. Synchronous read ports are not supported by memory_memx!\n",
|
||||
module, mem.memid.unescape());
|
||||
module, design->twines.unescaped_str(mem.memid));
|
||||
|
||||
SigSpec addr_ok = make_addr_check(mem, port.addr);
|
||||
Wire *raw_rdata = module->addWire(NEW_TWINE, GetSize(port.data));
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue