mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-21 22:55:51 +00:00
Code Activity

WIP

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
Download patch file Download diff file Expand all files Collapse all files

18
passes/fsm/fsm_detect.cc
View file

@ -55,7 +55,7 @@ ret_false:
sig2driver.find(sig, cellport_list);
for (auto &cellport : cellport_list)
{
if ((cellport.first->type != ID($mux) && cellport.first->type != ID($pmux)) || cellport.second != TW::Y) {
if ((cellport.first->type != TW($mux) && cellport.first->type != TW($pmux)) || cellport.second != TW::Y) {
goto ret_false;
}
@ -99,9 +99,9 @@ static bool check_state_users(RTLIL::SigSpec sig)
RTLIL::Cell *cell = cellport.first;
if (muxtree_cells.count(cell) > 0)
continue;
if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
if (cell->type.in(TW($input_port), TW($output_port), TW($public)))
continue;
if (cell->type == ID($logic_not) && assign_map(cell->getPort(TW::A)) == sig)
if (cell->type == TW($logic_not) && assign_map(cell->getPort(TW::A)) == sig)
continue;
if (cellport.second != TW::A && cellport.second != TW::B)
return false;
@ -145,7 +145,7 @@ static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false)
for (auto &cellport : cellport_list)
{
if ((cellport.first->type != ID($dff) && cellport.first->type != ID($adff)) || cellport.second != TW::Q)
if ((cellport.first->type != TW($dff) && cellport.first->type != TW($adff)) || cellport.second != TW::Q)
continue;
muxtree_cells.clear();
@ -175,10 +175,10 @@ static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false)
RTLIL::Cell *cell = cellport.first;
bool set_output = false, clr_output = false;
if (cell->type.in(ID($ne), ID($reduce_or), ID($reduce_bool)))
if (cell->type.in(TW($ne), TW($reduce_or), TW($reduce_bool)))
set_output = true;
if (cell->type.in(ID($eq), ID($logic_not), ID($reduce_and)))
if (cell->type.in(TW($eq), TW($logic_not), TW($reduce_and)))
clr_output = true;
if (set_output || clr_output) {
@ -202,7 +202,7 @@ static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false)
SigSpec sig_y = sig_d, sig_undef;
if (!ignore_self_reset) {
if (cellport.first->type == ID($adff)) {
if (cellport.first->type == TW($adff)) {
SigSpec sig_arst = assign_map(cellport.first->getPort(TW::ARST));
if (ce.eval(sig_arst, sig_undef))
is_self_resetting = true;
@ -328,12 +328,12 @@ struct FsmDetectPass : public Pass {
sig_at_port.clear();
for (auto cell : module->cells())
for (auto &conn_it : cell->connections()) {
if (ct.cell_output(cell->type, conn_it.first) || !ct.cell_known(cell->type)) {
if (ct.cell_output(cell->type_impl, conn_it.first) || !ct.cell_known(cell->type_impl)) {
RTLIL::SigSpec sig = conn_it.second;
assign_map.apply(sig);
sig2driver.insert(sig, sig2driver_entry_t(cell, conn_it.first));
}
if (!ct.cell_known(cell->type) || ct.cell_input(cell->type, conn_it.first)) {
if (!ct.cell_known(cell->type_impl) || ct.cell_input(cell->type_impl, conn_it.first)) {
RTLIL::SigSpec sig = conn_it.second;
assign_map.apply(sig);
sig2user.insert(sig, sig2driver_entry_t(cell, conn_it.first));

14
passes/fsm/fsm_expand.cc
View file

@ -47,10 +47,10 @@ struct FsmExpand
bool is_cell_merge_candidate(RTLIL::Cell *cell)
{
if (full_mode || cell->type == ID($_MUX_))
if (full_mode || cell->type == TW($_MUX_))
return true;
if (cell->type.in(ID($mux), ID($pmux)))
if (cell->type.in(TW($mux), TW($pmux)))
if (cell->getPort(TW::A).size() < 2)
return true;
@ -147,7 +147,7 @@ struct FsmExpand
RTLIL::SigSpec input_sig, output_sig;
for (auto &p : cell->connections())
if (ct.cell_output(cell->type, p.first))
if (ct.cell_output(cell->type_impl, p.first))
output_sig.append(assign_map(p.second));
else
input_sig.append(assign_map(p.second));
@ -189,7 +189,7 @@ struct FsmExpand
if (GetSize(input_sig) > 10)
log_warning("Cell %s.%s (%s) has %d input bits, merging into FSM %s.%s might be problematic.\n",
cell->module, cell, cell->type.unescape(),
cell->module, cell, cell->type.unescaped(),
GetSize(input_sig), fsm_cell->module, fsm_cell);
if (GetSize(fsm_data.transition_table) > 10000)
@ -230,9 +230,9 @@ struct FsmExpand
for (auto &cell_it : module->cells_) {
RTLIL::Cell *c = cell_it.second;
if (ct.cell_known(c->type) && design->selected(mod, c))
if (ct.cell_known(c->type_impl) && design->selected(mod, c))
for (auto &p : c->connections()) {
if (ct.cell_output(c->type, p.first))
if (ct.cell_output(c->type_impl, p.first))
sig2driver.insert(assign_map(p.second), c);
else
sig2user.insert(assign_map(p.second), c);
@ -298,7 +298,7 @@ struct FsmExpandPass : public Pass {
for (auto mod : design->selected_modules()) {
std::vector<RTLIL::Cell*> fsm_cells;
for (auto cell : mod->selected_cells())
if (cell->type == ID($fsm))
if (cell->type == TW($fsm))
fsm_cells.push_back(cell);
for (auto c : fsm_cells) {
FsmExpand fsm_expand(c, design, mod, full_mode);

2
passes/fsm/fsm_export.cc
View file

@ -175,7 +175,7 @@ struct FsmExportPass : public Pass {
for (auto mod : design->selected_modules())
for (auto cell : mod->selected_cells())
if (cell->type == ID($fsm)) {
if (cell->type == TW($fsm)) {
attr_it = cell->attributes.find(ID::fsm_export);
if (!flag_noauto || (attr_it != cell->attributes.end())) {
write_kiss2(mod, cell, filename, flag_origenc);

14
passes/fsm/fsm_extract.cc
View file

@ -70,7 +70,7 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
for (auto &cellport : cellport_list)
{
RTLIL::Cell *cell = module->cell(cellport.first);
if ((cell->type != ID($mux) && cell->type != ID($pmux)) || cellport.second != TW::Y) {
if ((cell->type != TW($mux) && cell->type != TW($pmux)) || cellport.second != TW::Y) {
log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type, log_id(cell));
return false;
}
@ -272,14 +272,14 @@ static void extract_fsm(RTLIL::Wire *wire)
sig2driver.find(dff_out, cellport_list);
for (auto &cellport : cellport_list) {
RTLIL::Cell *cell = module->cell(cellport.first);
if ((cell->type != ID($dff) && cell->type != ID($adff)) || cellport.second != TW::Q)
if ((cell->type != TW($dff) && cell->type != TW($adff)) || cellport.second != TW::Q)
continue;
log(" found %s cell for state register: %s\n", cell->type, log_id(cell));
RTLIL::SigSpec sig_q = assign_map(cell->getPort(TW::Q));
RTLIL::SigSpec sig_d = assign_map(cell->getPort(TW::D));
clk = cell->getPort(TW::CLK);
clk_polarity = cell->parameters[ID::CLK_POLARITY].as_bool();
if (cell->type == ID($adff)) {
if (cell->type == TW($adff)) {
arst = cell->getPort(TW::ARST);
arst_polarity = cell->parameters[ID::ARST_POLARITY].as_bool();
reset_state = cell->parameters[ID::ARST_VALUE];
@ -368,7 +368,7 @@ static void extract_fsm(RTLIL::Wire *wire)
// create fsm cell
RTLIL::Cell *fsm_cell = module->addCell(Twine{stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++)}, ID($fsm));
RTLIL::Cell *fsm_cell = module->addCell(Twine{stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++)}, TW($fsm));
fsm_cell->setPort(TW::CLK, clk);
fsm_cell->setPort(TW::ARST, arst);
fsm_cell->parameters[ID::CLK_POLARITY] = clk_polarity ? State::S1 : State::S0;
@ -446,19 +446,19 @@ struct FsmExtractPass : public Pass {
exclusive_ctrls.clear();
for (auto cell : module->cells()) {
for (auto &conn_it : cell->connections()) {
if (ct.cell_output(cell->type, conn_it.first) || !ct.cell_known(cell->type)) {
if (ct.cell_output(cell->type_impl, conn_it.first) || !ct.cell_known(cell->type_impl)) {
RTLIL::SigSpec sig = conn_it.second;
assign_map.apply(sig);
sig2driver.insert(sig, sig2driver_entry_t(cell->meta_->name, conn_it.first));
}
if (ct.cell_input(cell->type, conn_it.first) && cell->hasPort(TW::Y) &&
if (ct.cell_input(cell->type_impl, conn_it.first) && cell->hasPort(TW::Y) &&
cell->getPort(TW::Y).size() == 1 && (conn_it.first == TW::A || conn_it.first == TW::B)) {
RTLIL::SigSpec sig = conn_it.second;
assign_map.apply(sig);
sig2trigger.insert(sig, sig2driver_entry_t(cell->meta_->name, conn_it.first));
}
}
if (cell->type == ID($pmux)) {
if (cell->type == TW($pmux)) {
RTLIL::SigSpec sel_sig = assign_map(cell->getPort(TW::S));
for (auto &bit1 : sel_sig)
for (auto &bit2 : sel_sig)

2
passes/fsm/fsm_info.cc
View file

@ -48,7 +48,7 @@ struct FsmInfoPass : public Pass {
for (auto mod : design->selected_modules())
for (auto cell : mod->selected_cells())
if (cell->type == ID($fsm)) {
if (cell->type == TW($fsm)) {
log("\n");
log("FSM `%s' from module `%s':\n", cell, mod);
FsmData fsm_data;

14
passes/fsm/fsm_map.cc
View file

@ -74,7 +74,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
RTLIL::Wire *eq_wire = module->addWire(NEW_TWINE);
and_sig.append(RTLIL::SigSpec(eq_wire));
RTLIL::Cell *eq_cell = module->addCell(NEW_TWINE, ID($eq));
RTLIL::Cell *eq_cell = module->addCell(NEW_TWINE, TW($eq));
eq_cell->setPort(TW::A, eq_sig_a);
eq_cell->setPort(TW::B, eq_sig_b);
eq_cell->setPort(TW::Y, RTLIL::SigSpec(eq_wire));
@ -102,7 +102,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
RTLIL::Wire *or_wire = module->addWire(NEW_TWINE);
and_sig.append(RTLIL::SigSpec(or_wire));
RTLIL::Cell *or_cell = module->addCell(NEW_TWINE, ID($reduce_or));
RTLIL::Cell *or_cell = module->addCell(NEW_TWINE, TW($reduce_or));
or_cell->setPort(TW::A, or_sig);
or_cell->setPort(TW::Y, RTLIL::SigSpec(or_wire));
or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
@ -118,7 +118,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
RTLIL::Wire *and_wire = module->addWire(NEW_TWINE);
cases_vector.append(RTLIL::SigSpec(and_wire));
RTLIL::Cell *and_cell = module->addCell(NEW_TWINE, ID($and));
RTLIL::Cell *and_cell = module->addCell(NEW_TWINE, TW($and));
and_cell->setPort(TW::A, and_sig.extract(0, 1));
and_cell->setPort(TW::B, and_sig.extract(1, 1));
and_cell->setPort(TW::Y, RTLIL::SigSpec(and_wire));
@ -141,7 +141,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
}
if (cases_vector.size() > 1) {
RTLIL::Cell *or_cell = module->addCell(NEW_TWINE, ID($reduce_or));
RTLIL::Cell *or_cell = module->addCell(NEW_TWINE, TW($reduce_or));
or_cell->setPort(TW::A, cases_vector);
or_cell->setPort(TW::Y, output);
or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
@ -212,7 +212,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
{
encoding_is_onehot = false;
RTLIL::Cell *eq_cell = module->addCell(NEW_TWINE, ID($eq));
RTLIL::Cell *eq_cell = module->addCell(NEW_TWINE, TW($eq));
eq_cell->setPort(TW::A, sig_a);
eq_cell->setPort(TW::B, sig_b);
eq_cell->setPort(TW::Y, RTLIL::SigSpec(state_onehot, i));
@ -285,7 +285,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
}
}
RTLIL::Cell *mux_cell = module->addCell(NEW_TWINE, ID($pmux));
RTLIL::Cell *mux_cell = module->addCell(NEW_TWINE, TW($pmux));
mux_cell->setPort(TW::A, sig_a);
mux_cell->setPort(TW::B, sig_b);
mux_cell->setPort(TW::S, sig_s);
@ -339,7 +339,7 @@ struct FsmMapPass : public Pass {
for (auto mod : design->selected_modules()) {
std::vector<RTLIL::Cell*> fsm_cells;
for (auto cell : mod->selected_cells())
if (cell->type == ID($fsm))
if (cell->type == TW($fsm))
fsm_cells.push_back(cell);
for (auto cell : fsm_cells)
map_fsm(cell, mod);

2
passes/fsm/fsm_opt.cc
View file

@ -348,7 +348,7 @@ struct FsmOptPass : public Pass {
for (auto mod : design->selected_modules())
for (auto cell : mod->selected_cells())
if (cell->type == ID($fsm))
if (cell->type == TW($fsm))
FsmData::optimize_fsm(cell, mod);
}
} FsmOptPass;

2
passes/fsm/fsm_recode.cc
View file

@ -184,7 +184,7 @@ struct FsmRecodePass : public Pass {
for (auto mod : design->selected_modules())
for (auto cell : mod->selected_cells())
if (cell->type == ID($fsm))
if (cell->type == TW($fsm))
fsm_recode(cell, mod, fm_set_fsm_file, encfile, default_encoding);
if (fm_set_fsm_file != NULL)