mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-23 23:52:32 +00:00
Code Activity

WIP

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
Download patch file Download diff file Expand all files Collapse all files

8
passes/equiv/equiv_struct.cc
View file

@ -124,7 +124,7 @@ struct EquivStructWorker
pool<TwineRef> cells;
for (auto cell : module->selected_cells())
if (cell->type == ID($equiv)) {
if (cell->type == TW($equiv)) {
SigBit sig_a = sigmap(cell->getPort(TW::A).as_bit());
SigBit sig_b = sigmap(cell->getPort(TW::B).as_bit());
equiv_bits.add(sig_b, sig_a);
@ -137,7 +137,7 @@ struct EquivStructWorker
}
for (auto cell : module->selected_cells())
if (cell->type == ID($equiv)) {
if (cell->type == TW($equiv)) {
SigBit sig_a = sigmap(cell->getPort(TW::A).as_bit());
SigBit sig_b = sigmap(cell->getPort(TW::B).as_bit());
SigBit sig_y = sigmap(cell->getPort(TW::Y).as_bit());
@ -264,7 +264,7 @@ struct EquivStructWorker
run_strategy:
int total_group_size = GetSize(gold_cells) + GetSize(gate_cells) + GetSize(other_cells);
log(" %s merging %d %s cells (from group of %d) using strategy %s:\n", phase ? "Bwd" : "Fwd",
2*GetSize(cell_pairs), cells_type.unescape(), total_group_size, strategy);
2*GetSize(cell_pairs), design->twines.unescaped_str(cells_type), total_group_size, strategy);
for (auto it : cell_pairs) {
log(" Merging cells %s and %s.\n", it.first, it.second);
merge_cell_pair(it.first, it.second);
@ -314,7 +314,7 @@ struct EquivStructPass : public Pass {
}
void execute(std::vector<std::string> args, Design *design) override
{
pool<IdString> fwonly_cells({ ID($equiv) });
pool<IdString> fwonly_cells({ TW($equiv) });
bool mode_icells = false;
bool mode_fwd = false;
int max_iter = -1;