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This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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12
passes/equiv/equiv_induct.cc
View file

@ -47,7 +47,7 @@ struct EquivInductWorker : public EquivWorker<>
if (!satgen.importCell(cell, step)) {
report_missing_model(cfg.ignore_unknown_cells, cell);
}
if (cell->type == ID($equiv)) {
if (cell->type == TW($equiv)) {
SigBit bit_a = sigmap(cell->getPort(TW::A)).as_bit();
SigBit bit_b = sigmap(cell->getPort(TW::B)).as_bit();
if (bit_a != bit_b) {
@ -88,14 +88,14 @@ struct EquivInductWorker : public EquivWorker<>
if (satgen.model_undef) {
for (auto cell : cells)
if (yosys_celltypes.cell_known(cell->type))
if (yosys_celltypes.cell_known(cell->type_impl))
for (auto &conn : cell->connections())
if (yosys_celltypes.cell_input(cell->type, conn.first))
if (yosys_celltypes.cell_input(cell->type_impl, conn.first))
undriven_signals.add(sigmap(conn.second));
for (auto cell : cells)
if (yosys_celltypes.cell_known(cell->type))
if (yosys_celltypes.cell_known(cell->type_impl))
for (auto &conn : cell->connections())
if (yosys_celltypes.cell_output(cell->type, conn.first))
if (yosys_celltypes.cell_output(cell->type_impl, conn.first))
undriven_signals.del(sigmap(conn.second));
}
@ -211,7 +211,7 @@ struct EquivInductPass : public Pass {
vector<Cell*> assume_cells;
for (auto cell : module->selected_cells())
if (cell->type == ID($equiv)) {
if (cell->type == TW($equiv)) {
if (cell->getPort(TW::A) != cell->getPort(TW::B))
unproven_equiv_cells.insert(cell);
}

20
passes/equiv/equiv_make.cc
View file

@ -115,7 +115,7 @@ struct EquivMakeWorker
if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
cell_names.insert(it->name);
gold_clone->rename(it, gold_clone->design->twines.add(Twine{it->name.str() + "_gold"}));
if (it->type.in(ID($input_port), ID($output_port), ID($public)))
if (it->type.in(TW($input_port), TW($output_port), TW($public)))
gold_clone->remove(it);
}
@ -129,7 +129,7 @@ struct EquivMakeWorker
if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
cell_names.insert(it->name);
gate_clone->rename(it, gate_clone->design->twines.add(Twine{it->name.str() + "_gate"}));
if (it->type.in(ID($input_port), ID($output_port), ID($public)))
if (it->type.in(TW($input_port), TW($output_port), TW($public)))
gate_clone->remove(it);
}
@ -164,7 +164,7 @@ struct EquivMakeWorker
if (encdata.count(id))
{
log("Creating encoder/decoder for signal %s.\n", id.unescape());
log("Creating encoder/decoder for signal %s.\n", design->twines.unescaped_str(id));
Wire *dec_wire = equiv_mod->addWire(Twine{id.str() + "_decoded"}, gold_wire->width);
Wire *enc_wire = equiv_mod->addWire(Twine{id.str() + "_encoded"}, gate_wire->width);
@ -239,7 +239,7 @@ struct EquivMakeWorker
log("Presumably equivalent wires: %s (%s), %s (%s) -> %s\n",
gold_wire, log_signal(assign_map(gold_wire)),
gate_wire, log_signal(assign_map(gate_wire)), id.unescape());
gate_wire, log_signal(assign_map(gate_wire)), design->twines.unescaped_str(id));
if (gold_wire->port_output || gate_wire->port_output)
{
@ -310,7 +310,7 @@ struct EquivMakeWorker
for (auto c : cells_list)
for (auto &conn : c->connections())
if (!ct.cell_output(c->type, conn.first)) {
if (!ct.cell_output(c->type_impl, conn.first)) {
SigSpec old_sig = assign_map(conn.second);
SigSpec new_sig = rd_signal_map(old_sig);
for (int i = 0; i < GetSize(old_sig); i++)
@ -318,7 +318,7 @@ struct EquivMakeWorker
new_sig[i] = old_sig[i];
if (old_sig != new_sig) {
log("Changing input %s of cell %s (%s): %s -> %s\n",
equiv_mod->design->twines.str(conn.first).c_str(), c, c->type.unescape(),
equiv_mod->design->twines.str(conn.first).c_str(), c, design->twines.unescaped_str(c->type),
log_signal(old_sig), log_signal(new_sig));
c->setPort(conn.first, new_sig);
}
@ -339,7 +339,7 @@ struct EquivMakeWorker
Cell *gold_cell = equiv_mod->cell(gold_id);
Cell *gate_cell = equiv_mod->cell(gate_id);
if (gold_cell == nullptr || gate_cell == nullptr || gold_cell->type != gate_cell->type || !ct.cell_known(gold_cell->type) ||
if (gold_cell == nullptr || gate_cell == nullptr || gold_cell->type != gate_cell->type || !ct.cell_known(gold_cell->type_impl) ||
gold_cell->parameters != gate_cell->parameters || GetSize(gold_cell->connections()) != GetSize(gate_cell->connections()))
try_next_cell_name:
continue;
@ -349,14 +349,14 @@ struct EquivMakeWorker
goto try_next_cell_name;
log("Presumably equivalent cells: %s %s (%s) -> %s\n",
gold_cell, gate_cell, gold_cell->type.unescape(), id.unescape());
gold_cell, gate_cell, design->twines.unescaped_str(gold_cell->type), design->twines.unescaped_str(id));
for (auto gold_conn : gold_cell->connections())
{
SigSpec gold_sig = assign_map(gold_conn.second);
SigSpec gate_sig = assign_map(gate_cell->getPort(gold_conn.first));
if (ct.cell_output(gold_cell->type, gold_conn.first)) {
if (ct.cell_output(gold_cell->type_impl, gold_conn.first)) {
equiv_mod->connect(gate_sig, gold_sig);
continue;
}
@ -403,7 +403,7 @@ struct EquivMakeWorker
for (auto cell : equiv_mod->cells()) {
for (auto &conn : cell->connections())
if (!ct.cell_known(cell->type) || ct.cell_output(cell->type, conn.first))
if (!ct.cell_known(cell->type_impl) || ct.cell_output(cell->type_impl, conn.first))
for (auto bit : assign_map(conn.second))
undriven_bits.erase(bit);
}

4
passes/equiv/equiv_mark.cc
View file

@ -48,7 +48,7 @@ struct EquivMarkWorker
{
for (auto cell : module->cells())
{
if (cell->type == ID($equiv))
if (cell->type == TW($equiv))
equiv_cells.insert(cell->meta_->name);
for (auto &port : cell->connections())
@ -139,7 +139,7 @@ struct EquivMarkWorker
for (auto cell : module->cells())
{
if (cell_regions.count(cell->meta_->name) || cell->type != ID($equiv))
if (cell_regions.count(cell->meta_->name) || cell->type != TW($equiv))
continue;
SigSpec sig_a = sigmap(cell->getPort(TW::A));

20
passes/equiv/equiv_miter.cc
View file

@ -47,7 +47,7 @@ struct EquivMiterWorker
if (cone.count(c))
return;
if (c->type == ID($equiv) && !seed_cells.count(c)) {
if (c->type == TW($equiv) && !seed_cells.count(c)) {
leaves.insert(c);
return;
}
@ -55,9 +55,9 @@ struct EquivMiterWorker
cone.insert(c);
for (auto &conn : c->connections()) {
if (!ct.cell_input(c->type, conn.first))
if (!ct.cell_input(c->type_impl, conn.first))
continue;
if (c->type == ID($equiv) && (conn.first == TW::A) != gold_mode)
if (c->type == TW($equiv) && (conn.first == TW::A) != gold_mode)
continue;
for (auto bit : sigmap(conn.second))
if (bit_to_driver.count(bit))
@ -73,7 +73,7 @@ struct EquivMiterWorker
for (auto c : source_module->cells())
for (auto &conn : c->connections())
if (ct.cell_output(c->type, conn.first))
if (ct.cell_output(c->type_impl, conn.first))
for (auto bit : sigmap(conn.second))
if (bit.wire)
bit_to_driver[bit] = c;
@ -81,7 +81,7 @@ struct EquivMiterWorker
// find seed cells
for (auto c : source_module->selected_cells())
if (c->type == ID($equiv)) {
if (c->type == TW($equiv)) {
log("Seed $equiv cell: %s\n", c);
seed_cells.insert(c);
}
@ -143,7 +143,7 @@ struct EquivMiterWorker
for (auto w : miter_wires)
miter_module->addWire(Twine{w->name.str()}, w->width);
for (auto c : miter_cells) {
if (c->type.in(ID($input_port), ID($output_port), ID($public)))
if (c->type.in(TW($input_port), TW($output_port), TW($public)))
continue;
auto mc = miter_module->addCell(Twine{c->name.str()}, c);
for (auto &conn : mc->connections())
@ -175,11 +175,11 @@ struct EquivMiterWorker
for (auto c : miter_module->cells())
for (auto &conn : c->connections()) {
if (ct.cell_input(c->type, conn.first))
if (ct.cell_input(c->type_impl, conn.first))
for (auto bit : conn.second)
if (bit.wire)
used_bits.insert(bit);
if (ct.cell_output(c->type, conn.first))
if (ct.cell_output(c->type_impl, conn.first))
for (auto bit : conn.second)
if (bit.wire)
driven_bits.insert(bit);
@ -214,7 +214,7 @@ struct EquivMiterWorker
vector<Cell*> equiv_cells;
for (auto c : miter_module->cells())
if (c->type == ID($equiv) && c->getPort(TW::A) != c->getPort(TW::B))
if (c->type == TW($equiv) && c->getPort(TW::A) != c->getPort(TW::B))
equiv_cells.push_back(c);
for (auto c : equiv_cells)
@ -324,7 +324,7 @@ struct EquivMiterPass : public Pass {
design->sigNormalize(false);
if (design->module(design->twines.lookup(worker.miter_name.str())))
log_cmd_error("Miter module %s already exists.\n", worker.miter_name.unescape());
log_cmd_error("Miter module %s already exists.\n", design->twines.unescaped_str(worker.miter_name));
worker.source_module = nullptr;
for (auto m : design->selected_modules()) {

8
passes/equiv/equiv_purge.cc
View file

@ -37,7 +37,7 @@ struct EquivPurgeWorker
Wire *wire = sig.as_wire();
if (wire->name.isPublic()) {
if (!wire->port_output) {
log(" Module output: %s (%s)\n", log_signal(wire), cellname.unescape());
log(" Module output: %s (%s)\n", log_signal(wire), design->twines.unescaped_str(cellname));
wire->port_output = true;
}
return wire;
@ -53,7 +53,7 @@ struct EquivPurgeWorker
Wire *wire = module->addWire(Twine{name}, GetSize(sig));
wire->port_output = true;
module->connect(wire, sig);
log(" Module output: %s (%s)\n", log_signal(wire), cellname.unescape());
log(" Module output: %s (%s)\n", log_signal(wire), design->twines.unescaped_str(cellname));
return wire;
}
}
@ -102,7 +102,7 @@ struct EquivPurgeWorker
for (auto cell : module->cells())
{
if (cell->type != ID($equiv)) {
if (cell->type != TW($equiv)) {
for (auto &port : cell->connections()) {
if (cell->input(port.first))
for (auto bit : sigmap(port.second))
@ -167,7 +167,7 @@ struct EquivPurgeWorker
rewrite_sigmap.add(chunk, make_input(chunk));
for (auto cell : module->cells())
if (cell->type == ID($equiv))
if (cell->type == TW($equiv))
cell->setPort(TW::Y, rewrite_sigmap(sigmap(cell->getPort(TW::Y))));
module->fixup_ports();

2
passes/equiv/equiv_remove.cc
View file

@ -68,7 +68,7 @@ struct EquivRemovePass : public Pass {
for (auto module : design->selected_modules())
{
for (auto cell : module->selected_cells())
if (cell->type == ID($equiv) && (mode_gold || mode_gate || cell->getPort(TW::A) == cell->getPort(TW::B))) {
if (cell->type == TW($equiv) && (mode_gold || mode_gate || cell->getPort(TW::A) == cell->getPort(TW::B))) {
log("Removing $equiv cell %s.%s (%s).\n", module, cell, log_signal(cell->getPort(TW::Y)));
module->connect(cell->getPort(TW::Y), mode_gate ? cell->getPort(TW::B) : cell->getPort(TW::A));
module->remove(cell);

10
passes/equiv/equiv_simple.cc
View file

@ -111,7 +111,7 @@ struct EquivSimpleWorker : public EquivWorker<EquivSimpleConfig>
return true;
for (auto &conn : cell->connections())
if (yosys_celltypes.cell_input(cell->type, conn.first))
if (yosys_celltypes.cell_input(cell->type_impl, conn.first))
for (auto bit : model.sigmap(conn.second)) {
if (cell->is_builtin_ff()) {
if (conn.first != TW::CLK && conn.first != TW::C)
@ -461,14 +461,14 @@ struct EquivSimplePass : public Pass {
int unproven_cells_counter = 0;
for (auto cell : module->selected_cells()) {
if (cell->type == ID($equiv) && cell->getPort(TW::A) != cell->getPort(TW::B)) {
if (cell->type == TW($equiv) && cell->getPort(TW::A) != cell->getPort(TW::B)) {
auto bit = sigmap(cell->getPort(TW::Y).as_bit());
auto bit_group = bit;
if (cfg.group && bit_group.wire)
bit_group.offset = 0;
unproven_equiv_cells[bit_group][bit] = cell;
unproven_cells_counter++;
} else if (cell->type == ID($assume)) {
} else if (cell->type == TW($assume)) {
assumes.push_back(cell);
}
}
@ -480,10 +480,10 @@ struct EquivSimplePass : public Pass {
unproven_cells_counter, GetSize(unproven_equiv_cells), module);
for (auto cell : module->cells()) {
if (!ct.cell_known(cell->type))
if (!ct.cell_known(cell->type_impl))
continue;
for (auto &conn : cell->connections())
if (yosys_celltypes.cell_output(cell->type, conn.first))
if (yosys_celltypes.cell_output(cell->type_impl, conn.first))
for (auto bit : sigmap(conn.second))
bit2driver[bit] = cell;
}

2
passes/equiv/equiv_status.cc
View file

@ -59,7 +59,7 @@ struct EquivStatusPass : public Pass {
int proven_equiv_cells = 0;
for (auto cell : module->selected_cells())
if (cell->type == ID($equiv)) {
if (cell->type == TW($equiv)) {
if (cell->getPort(TW::A) != cell->getPort(TW::B))
unproven_equiv_cells.push_back(cell);
else

8
passes/equiv/equiv_struct.cc
View file

@ -124,7 +124,7 @@ struct EquivStructWorker
pool<TwineRef> cells;
for (auto cell : module->selected_cells())
if (cell->type == ID($equiv)) {
if (cell->type == TW($equiv)) {
SigBit sig_a = sigmap(cell->getPort(TW::A).as_bit());
SigBit sig_b = sigmap(cell->getPort(TW::B).as_bit());
equiv_bits.add(sig_b, sig_a);
@ -137,7 +137,7 @@ struct EquivStructWorker
}
for (auto cell : module->selected_cells())
if (cell->type == ID($equiv)) {
if (cell->type == TW($equiv)) {
SigBit sig_a = sigmap(cell->getPort(TW::A).as_bit());
SigBit sig_b = sigmap(cell->getPort(TW::B).as_bit());
SigBit sig_y = sigmap(cell->getPort(TW::Y).as_bit());
@ -264,7 +264,7 @@ struct EquivStructWorker
run_strategy:
int total_group_size = GetSize(gold_cells) + GetSize(gate_cells) + GetSize(other_cells);
log(" %s merging %d %s cells (from group of %d) using strategy %s:\n", phase ? "Bwd" : "Fwd",
2*GetSize(cell_pairs), cells_type.unescape(), total_group_size, strategy);
2*GetSize(cell_pairs), design->twines.unescaped_str(cells_type), total_group_size, strategy);
for (auto it : cell_pairs) {
log(" Merging cells %s and %s.\n", it.first, it.second);
merge_cell_pair(it.first, it.second);
@ -314,7 +314,7 @@ struct EquivStructPass : public Pass {
}
void execute(std::vector<std::string> args, Design *design) override
{
pool<IdString> fwonly_cells({ ID($equiv) });
pool<IdString> fwonly_cells({ TW($equiv) });
bool mode_icells = false;
bool mode_fwd = false;
int max_iter = -1;