mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-25 08:32:34 +00:00
WIP
This commit is contained in:
Emil J. Tywoniak
parent
afdae7b87e
commit
c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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@ -294,18 +294,18 @@ struct XpropWorker
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}
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void mark_maybe_x(Cell *cell) {
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if (cell->type.in(ID($bweqx), ID($eqx), ID($nex), ID($initstate), ID($assert), ID($assume), ID($cover), ID($anyseq), ID($anyconst)))
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if (cell->type.in(TW($bweqx), TW($eqx), TW($nex), TW($initstate), TW($assert), TW($assume), TW($cover), TW($anyseq), TW($anyconst)))
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return;
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if (cell->type.in(ID($pmux))) {
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if (cell->type.in(TW($pmux))) {
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mark_outputs_maybe_x(cell);
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return;
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}
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if (cell->is_builtin_ff() || cell->type == ID($anyinit)) {
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if (cell->is_builtin_ff() || cell->type == TW($anyinit)) {
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FfData ff(&initvals, cell);
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if (cell->type != ID($anyinit))
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if (cell->type != TW($anyinit))
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for (int i = 0; i < ff.width; i++)
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if (ff.val_init[i] == State::Sx)
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mark_maybe_x(ff.sig_q[i]);
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@ -318,7 +318,7 @@ struct XpropWorker
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return;
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}
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if (cell->type == ID($not)) {
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if (cell->type == TW($not)) {
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auto &sig_y = cell->getPort(TW::Y);
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auto sig_a = cell->getPort(TW::A); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
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for (int i = 0; i < GetSize(sig_y); i++)
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@ -327,7 +327,7 @@ struct XpropWorker
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return;
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}
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if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
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if (cell->type.in(TW($and), TW($or), TW($xor), TW($xnor))) {
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auto &sig_y = cell->getPort(TW::Y);
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auto sig_a = cell->getPort(TW::A); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
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auto sig_b = cell->getPort(TW::B); sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
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@ -337,7 +337,7 @@ struct XpropWorker
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return;
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}
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if (cell->type.in(ID($bwmux))) {
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if (cell->type.in(TW($bwmux))) {
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auto &sig_y = cell->getPort(TW::Y);
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auto &sig_a = cell->getPort(TW::A);
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auto &sig_b = cell->getPort(TW::B);
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@ -348,7 +348,7 @@ struct XpropWorker
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return;
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}
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if (cell->type.in(ID($_MUX_), ID($mux), ID($bmux))) {
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if (cell->type.in(TW($_MUX_), TW($mux), TW($bmux))) {
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auto &sig_y = cell->getPort(TW::Y);
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auto &sig_a = cell->getPort(TW::A);
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auto &sig_b = cell->getPort(TW::B);
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@ -372,7 +372,7 @@ struct XpropWorker
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return;
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}
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if (cell->type.in(ID($demux))) {
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if (cell->type.in(TW($demux))) {
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auto &sig_y = cell->getPort(TW::Y);
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auto &sig_a = cell->getPort(TW::A);
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auto &sig_s = cell->getPort(TW::S);
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@ -387,7 +387,7 @@ struct XpropWorker
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return;
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}
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if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift))) {
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if (cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift))) {
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auto &sig_b = cell->getPort(TW::B);
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auto &sig_y = cell->getPort(TW::Y);
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@ -407,7 +407,7 @@ struct XpropWorker
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return;
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}
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if (cell->type.in(ID($shiftx))) {
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if (cell->type.in(TW($shiftx))) {
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auto &sig_b = cell->getPort(TW::B);
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auto &sig_y = cell->getPort(TW::Y);
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@ -438,24 +438,24 @@ struct XpropWorker
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return;
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}
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if (cell->type.in(ID($add), ID($sub), ID($mul), ID($neg))) {
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if (cell->type.in(TW($add), TW($sub), TW($mul), TW($neg))) {
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if (inputs_maybe_x(cell))
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mark_outputs_maybe_x(cell);
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return;
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}
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if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
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if (cell->type.in(TW($div), TW($mod), TW($divfloor), TW($modfloor))) {
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mark_outputs_maybe_x(cell);
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return;
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}
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if (cell->type.in(
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ID($le), ID($lt), ID($ge), ID($gt),
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ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor),
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ID($reduce_bool), ID($logic_not), ID($logic_or), ID($logic_and),
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ID($eq), ID($ne),
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TW($le), TW($lt), TW($ge), TW($gt),
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TW($reduce_and), TW($reduce_or), TW($reduce_xor), TW($reduce_xnor),
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TW($reduce_bool), TW($logic_not), TW($logic_or), TW($logic_and),
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TW($eq), TW($ne),
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ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_ANDNOT_), ID($_OR_), ID($_NOR_), ID($_ORNOT_), ID($_XOR_), ID($_XNOR_)
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TW($_NOT_), TW($_AND_), TW($_NAND_), TW($_ANDNOT_), TW($_OR_), TW($_NOR_), TW($_ORNOT_), TW($_XOR_), TW($_XNOR_)
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)) {
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auto &sig_y = cell->getPort(TW::Y);
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if (inputs_maybe_x(cell))
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@ -463,11 +463,11 @@ struct XpropWorker
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return;
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}
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if (cell->type.in(ID($scopeinfo))) {
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if (cell->type.in(TW($scopeinfo))) {
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return;
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}
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log_warning("Unhandled cell %s (%s) during maybe-x marking\n", cell, cell->type.unescape());
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log_warning("Unhandled cell %s (%s) during maybe-x marking\n", cell, cell->type.unescaped());
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mark_outputs_maybe_x(cell);
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}
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@ -481,7 +481,7 @@ struct XpropWorker
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{
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if (!ports_maybe_x(cell)) {
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if (cell->type == ID($bweq)) {
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if (cell->type == TW($bweq)) {
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auto sig_y = cell->getPort(TW::Y);
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auto sig_a = cell->getPort(TW::A);
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auto sig_b = cell->getPort(TW::B);
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@ -492,7 +492,7 @@ struct XpropWorker
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return;
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}
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if (cell->type.in(ID($nex), ID($eqx))) {
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if (cell->type.in(TW($nex), TW($eqx))) {
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auto sig_y = cell->getPort(TW::Y);
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auto sig_a = cell->getPort(TW::A);
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auto sig_b = cell->getPort(TW::B);
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@ -500,7 +500,7 @@ struct XpropWorker
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RTLIL::IdString name(cell->name);
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auto type = cell->type;
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module->remove(cell);
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if (type == ID($eqx))
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if (type == TW($eqx))
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module->addEq(name, sig_a, sig_b, sig_y);
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else
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module->addNe(name, sig_a, sig_b, sig_y);
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@ -510,10 +510,10 @@ struct XpropWorker
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return;
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}
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if (cell->type.in(ID($not), ID($_NOT_))) {
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if (cell->type.in(TW($not), TW($_NOT_))) {
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auto &sig_y = cell->getPort(TW::Y);
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auto sig_a = cell->getPort(TW::A);
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if (cell->type == ID($not))
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if (cell->type == TW($not))
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sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
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auto enc_a = encoded(sig_a);
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@ -527,11 +527,11 @@ struct XpropWorker
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return;
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}
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if (cell->type.in(ID($and), ID($or), ID($_AND_), ID($_OR_), ID($_NAND_), ID($_NOR_), ID($_ANDNOT_), ID($_ORNOT_))) {
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if (cell->type.in(TW($and), TW($or), TW($_AND_), TW($_OR_), TW($_NAND_), TW($_NOR_), TW($_ANDNOT_), TW($_ORNOT_))) {
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auto &sig_y = cell->getPort(TW::Y);
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auto sig_a = cell->getPort(TW::A);
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auto sig_b = cell->getPort(TW::B);
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if (cell->type.in(ID($and), ID($or))) {
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if (cell->type.in(TW($and), TW($or))) {
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sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
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sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
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}
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@ -540,11 +540,11 @@ struct XpropWorker
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auto enc_b = encoded(sig_b);
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auto enc_y = encoded(sig_y, true);
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if (cell->type.in(ID($or), ID($_OR_), ID($_NOR_), ID($_ORNOT_)))
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if (cell->type.in(TW($or), TW($_OR_), TW($_NOR_), TW($_ORNOT_)))
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enc_a.invert(), enc_b.invert(), enc_y.invert();
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if (cell->type.in(ID($_NAND_), ID($_NOR_)))
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if (cell->type.in(TW($_NAND_), TW($_NOR_)))
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enc_y.invert();
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if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
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if (cell->type.in(TW($_ANDNOT_), TW($_ORNOT_)))
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enc_b.invert();
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enc_y.connect_0(module->Or(NEW_TWINE, enc_a.is_0, enc_b.is_0));
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@ -554,7 +554,7 @@ struct XpropWorker
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return;
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}
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if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($logic_not))) {
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if (cell->type.in(TW($reduce_and), TW($reduce_or), TW($reduce_bool), TW($logic_not))) {
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auto &sig_y = cell->getPort(TW::Y);
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auto &sig_a = cell->getPort(TW::A);
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@ -563,9 +563,9 @@ struct XpropWorker
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enc_y.connect_as_bool();
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if (cell->type.in(ID($reduce_or), ID($reduce_bool)))
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if (cell->type.in(TW($reduce_or), TW($reduce_bool)))
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enc_a.invert(), enc_y.invert();
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if (cell->type == ID($logic_not))
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if (cell->type == TW($logic_not))
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enc_a.invert();
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enc_y.connect_0(module->ReduceOr(NEW_TWINE, enc_a.is_0));
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@ -576,7 +576,7 @@ struct XpropWorker
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return;
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}
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if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
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if (cell->type.in(TW($reduce_xor), TW($reduce_xnor))) {
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auto &sig_y = cell->getPort(TW::Y);
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auto &sig_a = cell->getPort(TW::A);
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@ -584,7 +584,7 @@ struct XpropWorker
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auto enc_y = encoded(sig_y, true);
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enc_y.connect_as_bool();
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if (cell->type == ID($reduce_xnor))
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if (cell->type == TW($reduce_xnor))
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enc_y.invert();
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@ -596,7 +596,7 @@ struct XpropWorker
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return;
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}
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if (cell->type.in(ID($logic_and), ID($logic_or))) {
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if (cell->type.in(TW($logic_and), TW($logic_or))) {
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auto &sig_y = cell->getPort(TW::Y);
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auto &sig_a = cell->getPort(TW::A);
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auto &sig_b = cell->getPort(TW::B);
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@ -612,7 +612,7 @@ struct XpropWorker
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auto b_is_1 = module->ReduceOr(NEW_TWINE, enc_b.is_1);
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auto b_is_0 = module->ReduceAnd(NEW_TWINE, enc_b.is_0);
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if (cell->type == ID($logic_or))
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if (cell->type == TW($logic_or))
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enc_y.invert(), std::swap(a_is_0, a_is_1), std::swap(b_is_0, b_is_1);
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enc_y.connect_0(module->Or(NEW_TWINE, a_is_0, b_is_0));
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@ -622,11 +622,11 @@ struct XpropWorker
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return;
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}
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if (cell->type.in(ID($xor), ID($xnor), ID($_XOR_), ID($_XNOR_))) {
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if (cell->type.in(TW($xor), TW($xnor), TW($_XOR_), TW($_XNOR_))) {
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auto &sig_y = cell->getPort(TW::Y);
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auto sig_a = cell->getPort(TW::A);
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auto sig_b = cell->getPort(TW::B);
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if (cell->type.in(ID($xor), ID($xnor))) {
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if (cell->type.in(TW($xor), TW($xnor))) {
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sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
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sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
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}
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@ -635,7 +635,7 @@ struct XpropWorker
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auto enc_b = encoded(sig_b);
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auto enc_y = encoded(sig_y, true);
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if (cell->type.in(ID($xnor), ID($_XNOR_)))
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if (cell->type.in(TW($xnor), TW($_XNOR_)))
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enc_y.invert();
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enc_y.connect_x(module->Or(NEW_TWINE, enc_a.is_x, enc_b.is_x));
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@ -645,7 +645,7 @@ struct XpropWorker
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return;
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}
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if (cell->type.in(ID($eq), ID($ne))) {
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if (cell->type.in(TW($eq), TW($ne))) {
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auto &sig_y = cell->getPort(TW::Y);
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auto sig_a = cell->getPort(TW::A);
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auto sig_b = cell->getPort(TW::B);
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@ -658,7 +658,7 @@ struct XpropWorker
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auto enc_y = encoded(sig_y, true);
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enc_y.connect_as_bool();
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if (cell->type == ID($ne))
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if (cell->type == TW($ne))
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enc_y.invert();
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auto delta = module->Xor(NEW_TWINE, enc_a.is_1, enc_b.is_1);
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@ -671,7 +671,7 @@ struct XpropWorker
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return;
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}
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if (cell->type.in(ID($eqx), ID($nex))) {
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if (cell->type.in(TW($eqx), TW($nex))) {
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auto &sig_y = cell->getPort(TW::Y);
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auto sig_a = cell->getPort(TW::A);
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auto sig_b = cell->getPort(TW::B);
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@ -687,7 +687,7 @@ struct XpropWorker
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auto eq = module->ReduceAnd(NEW_TWINE, {delta_0, delta_1});
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auto res = cell->type == ID($nex) ? module->Not(NEW_TWINE, eq) : eq;
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auto res = cell->type == TW($nex) ? module->Not(NEW_TWINE, eq) : eq;
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module->connect(sig_y[0], res);
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if (GetSize(sig_y) > 1)
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@ -696,7 +696,7 @@ struct XpropWorker
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return;
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}
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if (cell->type.in(ID($bweqx))) {
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if (cell->type.in(TW($bweqx))) {
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auto &sig_y = cell->getPort(TW::Y);
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auto &sig_a = cell->getPort(TW::A);
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auto &sig_b = cell->getPort(TW::B);
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@ -711,13 +711,13 @@ struct XpropWorker
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return;
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}
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if (cell->type.in(ID($_MUX_), ID($mux), ID($bwmux))) {
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if (cell->type.in(TW($_MUX_), TW($mux), TW($bwmux))) {
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auto &sig_y = cell->getPort(TW::Y);
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auto &sig_a = cell->getPort(TW::A);
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auto &sig_b = cell->getPort(TW::B);
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auto sig_s = cell->getPort(TW::S);
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if (cell->type == ID($mux))
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if (cell->type == TW($mux))
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sig_s = SigSpec(sig_s[0], GetSize(sig_y));
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auto enc_a = encoded(sig_a);
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@ -736,7 +736,7 @@ struct XpropWorker
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return;
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}
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if (cell->type.in(ID($pmux))) {
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if (cell->type.in(TW($pmux))) {
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auto &sig_y = cell->getPort(TW::Y);
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auto &sig_a = cell->getPort(TW::A);
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auto &sig_b = cell->getPort(TW::B);
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@ -771,7 +771,7 @@ struct XpropWorker
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return;
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}
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if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) {
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if (cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx))) {
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auto &sig_y = cell->getPort(TW::Y);
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auto &sig_a = cell->getPort(TW::A);
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auto &sig_b = cell->getPort(TW::B);
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@ -787,9 +787,9 @@ struct XpropWorker
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SigSpec y_1 = module->addWire(NEW_TWINE, GetSize(sig_y));
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SigSpec y_x = module->addWire(NEW_TWINE, GetSize(sig_y));
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auto encoded_type = cell->type == ID($shiftx) ? ID($shift) : cell->type;
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auto encoded_type = cell->type == TW($shiftx) ? TW($shift) : cell->type;
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if (cell->type == ID($shiftx)) {
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if (cell->type == TW($shiftx)) {
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std::swap(enc_a.is_0, enc_a.is_x);
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}
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@ -813,7 +813,7 @@ struct XpropWorker
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|
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SigSpec y_0 = module->Not(NEW_TWINE, y_not_0);
|
||||
|
||||
if (cell->type == ID($shiftx))
|
||||
if (cell->type == TW($shiftx))
|
||||
std::swap(y_0, y_x);
|
||||
|
||||
enc_y.connect_0(module->And(NEW_TWINE, y_0, SigSpec(not_all_x, GetSize(sig_y))));
|
||||
|
|
@ -824,7 +824,7 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($ff))) {
|
||||
if (cell->type.in(TW($ff))) {
|
||||
auto &sig_d = cell->getPort(TW::D);
|
||||
auto &sig_q = cell->getPort(TW::Q);
|
||||
|
||||
|
|
@ -857,12 +857,12 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->is_builtin_ff() || cell->type == ID($anyinit)) {
|
||||
if (cell->is_builtin_ff() || cell->type == TW($anyinit)) {
|
||||
FfData ff(&initvals, cell);
|
||||
|
||||
if ((ff.has_clk || ff.has_gclk) && !ff.has_ce && !ff.has_aload && !ff.has_srst && !ff.has_arst && !ff.has_sr) {
|
||||
if (ff.has_clk && maybe_x(ff.sig_clk)) {
|
||||
log_warning("Only non-x CLK inputs are currently supported for %s (%s)\n", cell, cell->type.unescape());
|
||||
log_warning("Only non-x CLK inputs are currently supported for %s (%s)\n", cell, cell->type.unescaped());
|
||||
} else {
|
||||
auto init_q = ff.val_init;
|
||||
auto init_q_is_1 = init_q;
|
||||
|
|
@ -907,15 +907,15 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
} else {
|
||||
log_warning("Unhandled FF-cell %s (%s), consider running clk2fflogic, async2sync and/or dffunmap\n", cell, cell->type.unescape());
|
||||
log_warning("Unhandled FF-cell %s (%s), consider running clk2fflogic, async2sync and/or dffunmap\n", cell, cell->type.unescaped());
|
||||
}
|
||||
}
|
||||
|
||||
// Celltypes where any input x bit makes the whole output x
|
||||
if (cell->type.in(
|
||||
ID($neg),
|
||||
ID($le), ID($lt), ID($ge), ID($gt),
|
||||
ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor)
|
||||
TW($neg),
|
||||
TW($le), TW($lt), TW($ge), TW($gt),
|
||||
TW($add), TW($sub), TW($mul), TW($div), TW($mod), TW($divfloor), TW($modfloor)
|
||||
)) {
|
||||
|
||||
SigSpec inbits_x;
|
||||
|
|
@ -927,7 +927,7 @@ struct XpropWorker
|
|||
}
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
|
||||
if (cell->type.in(TW($div), TW($mod), TW($divfloor), TW($modfloor))) {
|
||||
auto sig_b = cell->getPort(TW::B);
|
||||
auto invalid = module->LogicNot(NEW_TWINE, sig_b);
|
||||
inbits_x.append(invalid);
|
||||
|
|
@ -937,7 +937,7 @@ struct XpropWorker
|
|||
|
||||
SigBit outbits_x = (GetSize(inbits_x) == 1 ? inbits_x : module->ReduceOr(NEW_TWINE, inbits_x));
|
||||
|
||||
bool bool_out = cell->type.in(ID($le), ID($lt), ID($ge), ID($gt));
|
||||
bool bool_out = cell->type.in(TW($le), TW($lt), TW($ge), TW($gt));
|
||||
|
||||
for (auto &conn : cell->connections()) {
|
||||
if (cell->output(conn.first)) {
|
||||
|
|
@ -958,15 +958,15 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type == ID($bmux)) // TODO might want to support bmux natively anyway
|
||||
if (cell->type == TW($bmux)) // TODO might want to support bmux natively anyway
|
||||
log("Running 'bmuxmap' preserves x-propagation and can be run before 'xprop'.\n");
|
||||
if (cell->type == ID($demux)) // TODO might want to support demux natively anyway
|
||||
if (cell->type == TW($demux)) // TODO might want to support demux natively anyway
|
||||
log("Running 'demuxmap' preserves x-propagation and can be run before 'xprop'.\n");
|
||||
|
||||
if (options.required)
|
||||
log_error("Unhandled cell %s (%s)\n", cell, cell->type.unescape());
|
||||
log_error("Unhandled cell %s (%s)\n", cell, cell->type.unescaped());
|
||||
else
|
||||
log_warning("Unhandled cell %s (%s)\n", cell, cell->type.unescape());
|
||||
log_warning("Unhandled cell %s (%s)\n", cell, cell->type.unescaped());
|
||||
}
|
||||
|
||||
void split_ports()
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue