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This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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4
passes/cmds/test_patch.cc
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@ -17,12 +17,12 @@ struct TestPatchPass : public Pass {
for (auto module : design->selected_modules()) {
SigMap sigmap(module);
for (auto cell : module->selected_cells()) {
if (cell->type == ID($add)) {
if (cell->type == TW($add)) {
Cell* add = cell;
log_assert(add->getPort(TW::B).is_wire());
log_assert(add->getPort(TW::B).known_driver());
auto neg = add->getPort(TW::B)[0].wire->driverCell();
log_assert(neg->type == ID($not));
log_assert(neg->type == TW($not));
RTLIL::Patch patcher(module, nullptr);
int width = cell->getPort(TW::A).size();
auto sub = patcher.addSub(NEW_TWINE,