mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-21 14:45:50 +00:00
WIP
This commit is contained in:
Emil J. Tywoniak
parent
afdae7b87e
commit
c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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@ -59,18 +59,18 @@ struct statdata_t {
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double local_sequential_area = 0;
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double submodule_area = 0;
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int num_submodules = 0;
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std::map<RTLIL::IdString, unsigned int, RTLIL::sort_by_id_str> num_submodules_by_type;
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std::map<RTLIL::IdString, double, RTLIL::sort_by_id_str> submodules_area_by_type;
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std::map<TwineRef, unsigned int, RTLIL::sort_by_id_str> num_submodules_by_type;
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std::map<TwineRef, double, RTLIL::sort_by_id_str> submodules_area_by_type;
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std::map<RTLIL::IdString, unsigned int, RTLIL::sort_by_id_str> local_num_cells_by_type;
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std::map<RTLIL::IdString, double, RTLIL::sort_by_id_str> local_area_cells_by_type;
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std::map<RTLIL::IdString, double, RTLIL::sort_by_id_str> local_seq_area_cells_by_type;
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std::map<TwineRef, unsigned int, RTLIL::sort_by_id_str> local_num_cells_by_type;
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std::map<TwineRef, double, RTLIL::sort_by_id_str> local_area_cells_by_type;
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std::map<TwineRef, double, RTLIL::sort_by_id_str> local_seq_area_cells_by_type;
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string tech;
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std::map<RTLIL::IdString, unsigned int, RTLIL::sort_by_id_str> num_cells_by_type;
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std::map<RTLIL::IdString, double, RTLIL::sort_by_id_str> area_cells_by_type;
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std::map<RTLIL::IdString, double, RTLIL::sort_by_id_str> seq_area_cells_by_type;
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std::set<RTLIL::IdString> unknown_cell_area;
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std::map<TwineRef, unsigned int, RTLIL::sort_by_id_str> num_cells_by_type;
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std::map<TwineRef, double, RTLIL::sort_by_id_str> area_cells_by_type;
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std::map<TwineRef, double, RTLIL::sort_by_id_str> seq_area_cells_by_type;
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std::set<TwineRef> unknown_cell_area;
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statdata_t operator+(const statdata_t &other) const
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{
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@ -141,7 +141,7 @@ struct statdata_t {
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}
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}
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statdata_t(RTLIL::Design *design, const RTLIL::Module *mod, bool width_mode, dict<IdString, cell_area_t> &cell_area, string techname)
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statdata_t(RTLIL::Design *design, const RTLIL::Module *mod, bool width_mode, dict<TwineRef, cell_area_t> &cell_area, string techname)
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{
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tech = techname;
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@ -183,35 +183,35 @@ struct statdata_t {
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local_num_memory_bits += it.second->width * it.second->size;
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}
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for (auto cell : mod->selected_cells()) {
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RTLIL::IdString cell_type = cell->type;
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TwineRef cell_type = cell->type_impl;
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if (width_mode) {
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if (cell_type.in(ID($not), ID($pos), ID($neg), ID($logic_not), ID($logic_and), ID($logic_or), ID($reduce_and),
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ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($lut), ID($and), ID($or),
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ID($xor), ID($xnor), ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx), ID($lt),
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ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt), ID($add), ID($sub), ID($mul),
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ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow), ID($alu))) {
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if (cell_type.in(TW($not), TW($pos), TW($neg), TW($logic_not), TW($logic_and), TW($logic_or), TW($reduce_and),
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TW($reduce_or), TW($reduce_xor), TW($reduce_xnor), TW($reduce_bool), TW($lut), TW($and), TW($or),
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TW($xor), TW($xnor), TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx), TW($lt),
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TW($le), TW($eq), TW($ne), TW($eqx), TW($nex), TW($ge), TW($gt), TW($add), TW($sub), TW($mul),
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TW($div), TW($mod), TW($divfloor), TW($modfloor), TW($pow), TW($alu))) {
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int width_a = cell->hasPort(TW::A) ? GetSize(cell->getPort(TW::A)) : 0;
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int width_b = cell->hasPort(TW::B) ? GetSize(cell->getPort(TW::B)) : 0;
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int width_y = cell->hasPort(TW::Y) ? GetSize(cell->getPort(TW::Y)) : 0;
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cell_type = stringf("%s_%d", cell_type, max<int>({width_a, width_b, width_y}));
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} else if (cell_type.in(ID($mux)))
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cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(TW::Y)));
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else if (cell_type.in(ID($bmux), ID($pmux)))
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cell_type = design->twines.add(Twine{stringf("%s_%d", cell_type, max<int>({width_a, width_b, width_y}))});
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} else if (cell_type.in(TW($mux)))
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cell_type = design->twines.add(Twine{stringf("%s_%d", cell_type, GetSize(cell->getPort(TW::Y)))});
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else if (cell_type.in(TW($bmux), TW($pmux)))
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cell_type =
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stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(TW::Y)), GetSize(cell->getPort(TW::S)));
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else if (cell_type == ID($demux))
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design->twines.add(Twine{stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(TW::Y)), GetSize(cell->getPort(TW::S)))});
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else if (cell_type == TW($demux))
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cell_type =
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stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::S)));
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else if (cell_type.in(ID($sr), ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe),
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ID($sdff), ID($sdffe), ID($sdffce), ID($aldff), ID($aldffe), ID($dlatch), ID($adlatch),
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ID($dlatchsr)))
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cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(TW::Q)));
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design->twines.add(Twine{stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::S)))});
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else if (cell_type.in(TW($sr), TW($ff), TW($dff), TW($dffe), TW($dffsr), TW($dffsre), TW($adff), TW($adffe),
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TW($sdff), TW($sdffe), TW($sdffce), TW($aldff), TW($aldffe), TW($dlatch), TW($adlatch),
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TW($dlatchsr)))
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cell_type = design->twines.add(Twine{stringf("%s_%d", cell_type, GetSize(cell->getPort(TW::Q)))});
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}
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if (!cell_area.empty()) {
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// check if cell_area provides a area calculator
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if (cell_area.count(cell->type)) {
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cell_area_t cell_data = cell_area.at(cell->type);
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if (cell_area.count(cell->type_impl)) {
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cell_area_t cell_data = cell_area.at(cell->type_impl);
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if (cell_data.single_parameter_area.size() > 0) {
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// assume that we just take the max of the A,B,Y ports
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@ -337,18 +337,16 @@ struct statdata_t {
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num_processes++;
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local_num_processes++;
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}
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RTLIL::IdString cell_name = mod->name;
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auto s = cell_name.str();
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}
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unsigned int estimate_xilinx_lc()
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{
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unsigned int lut6_cnt = num_cells_by_type[ID(LUT6)];
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unsigned int lut5_cnt = num_cells_by_type[ID(LUT5)];
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unsigned int lut4_cnt = num_cells_by_type[ID(LUT4)];
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unsigned int lut3_cnt = num_cells_by_type[ID(LUT3)];
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unsigned int lut2_cnt = num_cells_by_type[ID(LUT2)];
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unsigned int lut1_cnt = num_cells_by_type[ID(LUT1)];
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unsigned int lut6_cnt = num_cells_by_type[TW::LUT6];
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unsigned int lut5_cnt = num_cells_by_type[TW::LUT5];
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unsigned int lut4_cnt = num_cells_by_type[TW::LUT4];
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unsigned int lut3_cnt = num_cells_by_type[TW::LUT3];
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unsigned int lut2_cnt = num_cells_by_type[TW::LUT2];
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unsigned int lut1_cnt = num_cells_by_type[TW::LUT1];
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unsigned int lc_cnt = 0;
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lc_cnt += lut6_cnt;
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@ -505,7 +503,7 @@ struct statdata_t {
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}
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}
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void log_data(RTLIL::IdString mod_name, bool top_mod, bool print_area = true, bool print_hierarchical = true, bool print_global_only = false)
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void log_data(const TwinePool& twines, TwineRef mod_name, bool top_mod, bool print_area = true, bool print_hierarchical = true, bool print_global_only = false)
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{
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print_log_header(print_area, print_hierarchical, print_global_only);
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@ -523,7 +521,7 @@ struct statdata_t {
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print_log_line("cells", local_num_cells, local_area, num_cells, area, 0, print_area, print_hierarchical, print_global_only);
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for (auto &it : num_cells_by_type)
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if (it.second) {
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auto name = string(it.first.unescape());
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auto name = twines.unescaped_str(it.first);
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print_log_line(name, local_num_cells_by_type.count(it.first) ? local_num_cells_by_type.at(it.first) : 0,
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local_area_cells_by_type.count(it.first) ? local_area_cells_by_type.at(it.first) : 0, it.second,
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area_cells_by_type.at(it.first), 1, print_area, print_hierarchical, print_global_only);
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@ -533,7 +531,7 @@ struct statdata_t {
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print_global_only);
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for (auto &it : num_submodules_by_type)
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if (it.second)
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print_log_line(string(it.first.unescape()), it.second, 0, it.second,
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print_log_line(twines.unescaped_str(it.first), it.second, 0, it.second,
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submodules_area_by_type.count(it.first) ? submodules_area_by_type.at(it.first) : 0, 1,
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print_area, print_hierarchical, print_global_only);
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}
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@ -582,7 +580,7 @@ struct statdata_t {
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count_local, area_local);
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}
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void log_data_json(const char *mod_name, bool first_module, bool hierarchical = false, bool global_only = false)
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void log_data_json(const TwinePool& twines, const char *mod_name, bool first_module, bool hierarchical = false, bool global_only = false)
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{
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if (!first_module)
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log(",\n");
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@ -607,7 +605,7 @@ struct statdata_t {
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if (it.second) {
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if (!first_line)
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log(",\n");
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log(" %s: %s", json11::Json(it.first.unescape()).dump(),
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log(" %s: %s", json11::Json(twines.unescaped_str(it.first)).dump(),
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json_line(local_num_cells_by_type.count(it.first) ? local_num_cells_by_type.at(it.first) : 0,
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local_area_cells_by_type.count(it.first) ? local_area_cells_by_type.at(it.first) : 0, it.second,
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area_cells_by_type.at(it.first))
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@ -621,7 +619,7 @@ struct statdata_t {
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if (it.second) {
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if (!first_line)
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log(",\n");
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log(" %s: %s", json11::Json(it.first.unescape()).dump(),
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log(" %s: %s", json11::Json(twines.unescaped_str(it.first)).dump(),
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json_line(0, 0, it.second,
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submodules_area_by_type.count(it.first) ? submodules_area_by_type.at(it.first) : 0)
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.c_str());
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@ -662,14 +660,14 @@ struct statdata_t {
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if (it.second) {
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if (!first_line)
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log(",\n");
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log(" %s: %u", json11::Json(it.first.unescape()).dump(), it.second);
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log(" %s: %u", json11::Json(twines.unescaped_str(it.first)).dump(), it.second);
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first_line = false;
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}
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for (auto &it : num_submodules_by_type)
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if (it.second) {
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if (!first_line)
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log(",\n");
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log(" %s: %u", json11::Json(it.first.unescape()).dump(), it.second);
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log(" %s: %u", json11::Json(twines.unescaped_str(it.first)).dump(), it.second);
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first_line = false;
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}
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log("\n");
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@ -697,14 +695,14 @@ struct statdata_t {
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if (it.second) {
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if (!first_line)
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log(",\n");
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log(" %s: %u", json11::Json(it.first.unescape()).dump(), it.second);
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log(" %s: %u", json11::Json(twines.unescaped_str(it.first)).dump(), it.second);
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first_line = false;
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}
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for (auto &it : num_submodules_by_type)
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if (it.second) {
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if (!first_line)
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log(",\n");
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log(" %s: %u", json11::Json(it.first.unescape()).dump(), it.second);
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log(" %s: %u", json11::Json(twines.unescaped_str(it.first)).dump(), it.second);
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first_line = false;
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}
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log("\n");
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@ -726,7 +724,7 @@ struct statdata_t {
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}
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};
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statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTLIL::IdString mod, int level, bool quiet = false, bool has_area = true,
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statdata_t hierarchy_worker(const TwinePool& twines, std::map<TwineRef, statdata_t> &mod_stat, TwineRef mod, int level, bool quiet = false, bool has_area = true,
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bool hierarchy_mode = true)
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{
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statdata_t mod_data = mod_stat.at(mod);
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@ -734,60 +732,60 @@ statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTL
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for (auto &it : mod_data.num_submodules_by_type) {
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if (mod_stat.count(it.first) > 0) {
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if (!quiet)
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mod_data.print_log_line(string(it.first.unescape()), mod_stat.at(it.first).local_num_cells,
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mod_data.print_log_line(twines.unescaped_str(it.first), mod_stat.at(it.first).local_num_cells,
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mod_stat.at(it.first).local_area, mod_stat.at(it.first).num_cells, mod_stat.at(it.first).area,
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level, has_area, hierarchy_mode);
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hierarchy_worker(mod_stat, it.first, level + 1, quiet, has_area, hierarchy_mode) * it.second;
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hierarchy_worker(twines, mod_stat, it.first, level + 1, quiet, has_area, hierarchy_mode) * it.second;
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}
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}
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return mod_data;
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}
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statdata_t hierarchy_builder(RTLIL::Design *design, const RTLIL::Module *top_mod, std::map<RTLIL::IdString, statdata_t> &mod_stat,
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bool width_mode, dict<IdString, cell_area_t> &cell_area, string techname)
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statdata_t hierarchy_builder(RTLIL::Design *design, const RTLIL::Module *top_mod, std::map<TwineRef, statdata_t> &mod_stat,
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bool width_mode, dict<TwineRef, cell_area_t> &cell_area, string techname)
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{
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if (top_mod == nullptr)
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top_mod = design->top_module();
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statdata_t mod_data(design, top_mod, width_mode, cell_area, techname);
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for (auto cell : top_mod->selected_cells()) {
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if (cell_area.count(cell->type) == 0) {
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if (design->has(cell->type)) {
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if (cell_area.count(cell->type_impl) == 0) {
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if (design->has(cell->type_impl)) {
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if (!(design->module(cell->type)->attributes.count(ID::blackbox))) {
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// deal with modules
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mod_data.add(
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hierarchy_builder(design, design->module(cell->type), mod_stat, width_mode, cell_area, techname));
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mod_data.num_submodules_by_type[cell->type]++;
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mod_data.submodules_area_by_type[cell->type] += mod_stat.at(cell->type).area;
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mod_data.submodule_area += mod_stat.at(cell->type).area;
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mod_data.num_submodules_by_type[cell->type_impl]++;
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mod_data.submodules_area_by_type[cell->type_impl] += mod_stat.at(cell->type_impl).area;
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mod_data.submodule_area += mod_stat.at(cell->type_impl).area;
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mod_data.num_submodules++;
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mod_data.unknown_cell_area.erase(cell->type);
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mod_data.unknown_cell_area.erase(cell->type_impl);
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mod_data.num_cells -=
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(mod_data.num_cells_by_type.count(cell->type) != 0) ? mod_data.num_cells_by_type.at(cell->type) : 0;
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mod_data.num_cells_by_type.erase(cell->type);
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mod_data.local_num_cells -= (mod_data.local_num_cells_by_type.count(cell->type) != 0)
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? mod_data.local_num_cells_by_type.at(cell->type)
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(mod_data.num_cells_by_type.count(cell->type_impl) != 0) ? mod_data.num_cells_by_type.at(cell->type_impl) : 0;
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mod_data.num_cells_by_type.erase(cell->type_impl);
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mod_data.local_num_cells -= (mod_data.local_num_cells_by_type.count(cell->type_impl) != 0)
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? mod_data.local_num_cells_by_type.at(cell->type_impl)
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: 0;
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mod_data.local_num_cells_by_type.erase(cell->type);
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mod_data.local_area_cells_by_type.erase(cell->type);
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mod_data.local_num_cells_by_type.erase(cell->type_impl);
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mod_data.local_area_cells_by_type.erase(cell->type_impl);
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} else {
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// deal with blackbox cells
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if (design->module(cell->type)->attributes.count(ID::area) &&
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design->module(cell->type)->attributes.at(ID::area).size() == 0) {
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mod_data.num_submodules_by_type[cell->type]++;
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mod_data.num_submodules_by_type[cell->type_impl]++;
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mod_data.num_submodules++;
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mod_data.submodules_area_by_type[cell->type] +=
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double(design->module(cell->type)->attributes.at(ID::area).as_int());
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mod_data.area += double(design->module(cell->type)->attributes.at(ID::area).as_int());
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mod_data.unknown_cell_area.erase(cell->type);
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mod_data.submodules_area_by_type[cell->type_impl] +=
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double(design->module(cell->type_impl)->attributes.at(ID::area).as_int());
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mod_data.area += double(design->module(cell->type_impl)->attributes.at(ID::area).as_int());
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mod_data.unknown_cell_area.erase(cell->type_impl);
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mod_data.num_cells -=
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(mod_data.num_cells_by_type.count(cell->type) != 0) ? mod_data.num_cells_by_type.at(cell->type) : 0;
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mod_data.num_cells_by_type.erase(cell->type);
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mod_data.local_num_cells -= (mod_data.local_num_cells_by_type.count(cell->type) != 0)
|
||||
? mod_data.local_num_cells_by_type.at(cell->type)
|
||||
(mod_data.num_cells_by_type.count(cell->type_impl) != 0) ? mod_data.num_cells_by_type.at(cell->type_impl) : 0;
|
||||
mod_data.num_cells_by_type.erase(cell->type_impl);
|
||||
mod_data.local_num_cells -= (mod_data.local_num_cells_by_type.count(cell->type_impl) != 0)
|
||||
? mod_data.local_num_cells_by_type.at(cell->type_impl)
|
||||
: 0;
|
||||
mod_data.local_num_cells_by_type.erase(cell->type);
|
||||
mod_data.local_area_cells_by_type.erase(cell->type);
|
||||
mod_data.local_num_cells_by_type.erase(cell->type_impl);
|
||||
mod_data.local_area_cells_by_type.erase(cell->type_impl);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -797,7 +795,7 @@ statdata_t hierarchy_builder(RTLIL::Design *design, const RTLIL::Module *top_mod
|
|||
return mod_data;
|
||||
}
|
||||
|
||||
void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_area, string liberty_file)
|
||||
void read_liberty_cellarea(TwinePool& twines, dict<TwineRef, cell_area_t> &cell_area, string liberty_file)
|
||||
{
|
||||
std::istream *f = uncompressed(liberty_file.c_str());
|
||||
yosys_input_files.insert(liberty_file);
|
||||
|
|
@ -874,7 +872,8 @@ void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_area, string libert
|
|||
|
||||
if (ar != nullptr && !ar->value.empty()) {
|
||||
string prefix = cell->args[0].substr(0, 1) == "$" ? "" : "\\";
|
||||
cell_area[prefix + cell->args[0]] = {atof(ar->value.c_str()), is_flip_flop, single_parameter_area, double_parameter_area,
|
||||
TwineRef t = twines.add(Twine{prefix + cell->args[0]});
|
||||
cell_area[t] = {atof(ar->value.c_str()), is_flip_flop, single_parameter_area, double_parameter_area,
|
||||
port_names};
|
||||
}
|
||||
}
|
||||
|
|
@ -927,8 +926,8 @@ struct StatPass : public Pass {
|
|||
{
|
||||
bool width_mode = false, json_mode = false, hierarchy_mode = false;
|
||||
RTLIL::Module *top_mod = nullptr;
|
||||
std::map<RTLIL::IdString, statdata_t> mod_stat;
|
||||
dict<IdString, cell_area_t> cell_area;
|
||||
std::map<TwineRef, statdata_t> mod_stat;
|
||||
dict<TwineRef, cell_area_t> cell_area;
|
||||
string techname;
|
||||
|
||||
size_t argidx;
|
||||
|
|
@ -940,7 +939,7 @@ struct StatPass : public Pass {
|
|||
if (args[argidx] == "-liberty" && argidx + 1 < args.size()) {
|
||||
string liberty_file = args[++argidx];
|
||||
rewrite_filename(liberty_file);
|
||||
read_liberty_cellarea(cell_area, liberty_file);
|
||||
read_liberty_cellarea(design->twines, cell_area, liberty_file);
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-tech" && argidx + 1 < args.size()) {
|
||||
|
|
@ -1005,13 +1004,13 @@ struct StatPass : public Pass {
|
|||
top_mod = mod;
|
||||
statdata_t data = mod_stat.at(mod->name);
|
||||
if (json_mode) {
|
||||
data.log_data_json(mod->name.c_str(), first_module, hierarchy_mode);
|
||||
data.log_data_json(design->twines, mod->name.c_str(), first_module, hierarchy_mode);
|
||||
first_module = false;
|
||||
} else {
|
||||
log("\n");
|
||||
log("=== %s%s ===\n", mod->name.unescape(), mod->is_selected_whole() ? "" : " (partially selected)");
|
||||
log("=== %s%s ===\n", design->twines.unescaped_str(mod->name), mod->is_selected_whole() ? "" : " (partially selected)");
|
||||
log("\n");
|
||||
data.log_data(mod->name, false, has_area, hierarchy_mode);
|
||||
data.log_data(design->twines, mod->name, false, has_area, hierarchy_mode);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1031,13 +1030,13 @@ struct StatPass : public Pass {
|
|||
mod_stat[top_mod->name].area, 0, has_area, hierarchy_mode, true);
|
||||
}
|
||||
|
||||
statdata_t data = hierarchy_worker(mod_stat, top_mod->name, 0, /*quiet=*/json_mode, has_area, hierarchy_mode);
|
||||
statdata_t data = hierarchy_worker(design->twines, mod_stat, top_mod->name, 0, /*quiet=*/json_mode, has_area, hierarchy_mode);
|
||||
|
||||
if (json_mode)
|
||||
data.log_data_json("design", true, hierarchy_mode, true);
|
||||
data.log_data_json(design->twines, "design", true, hierarchy_mode, true);
|
||||
else if (GetSize(mod_stat) > 1) {
|
||||
log("\n");
|
||||
data.log_data(top_mod->name, true, has_area, hierarchy_mode, true);
|
||||
data.log_data(design->twines, top_mod->name, true, has_area, hierarchy_mode, true);
|
||||
}
|
||||
|
||||
design->scratchpad_set_int("stat.num_wires", data.num_wires);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue