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This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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26
passes/cmds/glift.cc
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@ -70,7 +70,7 @@ private:
void add_precise_GLIFT_logic(const RTLIL::Cell *cell, RTLIL::SigSpec &port_a, RTLIL::SigSpec &port_a_taint, RTLIL::SigSpec &port_b, RTLIL::SigSpec &port_b_taint, RTLIL::SigSpec &port_y_taint) {
//AKA AN2_SH2 or OR2_SH2
bool is_and = cell->type.in(ID($_AND_), ID($_NAND_));
bool is_and = cell->type.in(TW($_AND_), TW($_NAND_));
RTLIL::SigSpec n_port_a = module->LogicNot(Twine{cell->name.str() + "_t_1_1"}, port_a, false, cell->src_ref());
RTLIL::SigSpec n_port_b = module->LogicNot(Twine{cell->name.str() + "_t_1_2"}, port_b, false, cell->src_ref());
auto subexpr1 = module->And(Twine{cell->name.str() + "_t_1_3"}, is_and? port_a : n_port_a, port_b_taint, false, cell->src_ref());
@ -82,7 +82,7 @@ private:
void add_imprecise_GLIFT_logic_1(const RTLIL::Cell *cell, RTLIL::SigSpec &port_a, RTLIL::SigSpec &port_a_taint, RTLIL::SigSpec &port_b, RTLIL::SigSpec &port_b_taint, RTLIL::SigSpec &port_y_taint) {
//AKA AN2_SH3 or OR2_SH3
bool is_and = cell->type.in(ID($_AND_), ID($_NAND_));
bool is_and = cell->type.in(TW($_AND_), TW($_NAND_));
RTLIL::SigSpec n_port_a = module->LogicNot(Twine{cell->name.str() + "_t_2_1"}, port_a, false, cell->src_ref());
auto subexpr1 = module->And(Twine{cell->name.str() + "_t_2_2"}, is_and? port_b : n_port_a, is_and? port_a_taint : port_b_taint, false, cell->src_ref());
module->addOr(Twine{cell->name.str() + "_t_2_3"}, is_and? port_b_taint : port_a_taint, subexpr1, port_y_taint, false, cell->src_ref());
@ -90,7 +90,7 @@ private:
void add_imprecise_GLIFT_logic_2(const RTLIL::Cell *cell, RTLIL::SigSpec &port_a, RTLIL::SigSpec &port_a_taint, RTLIL::SigSpec &port_b, RTLIL::SigSpec &port_b_taint, RTLIL::SigSpec &port_y_taint) {
//AKA AN2_SH4 or OR2_SH4
bool is_and = cell->type.in(ID($_AND_), ID($_NAND_));
bool is_and = cell->type.in(TW($_AND_), TW($_NAND_));
RTLIL::SigSpec n_port_b = module->LogicNot(Twine{cell->name.str() + "_t_3_1"}, port_b, false, cell->src_ref());
auto subexpr1 = module->And(Twine{cell->name.str() + "_t_3_2"}, is_and? port_a : n_port_b, is_and? port_b_taint : port_a_taint, false, cell->src_ref());
module->addOr(Twine{cell->name.str() + "_t_3_3"}, is_and? port_a_taint : port_b_taint, subexpr1, port_y_taint, false, cell->src_ref());
@ -150,13 +150,13 @@ private:
auto select_width = metamux_select.as_wire()->width;
std::vector<RTLIL::Const> costs;
if (celltype == ID($_AND_) || celltype == ID($_OR_)) {
if (celltype == TW($_AND_) || celltype == TW($_OR_)) {
costs = {5, 2, 2, 1, 0, 0, 0, 0};
log_assert(select_width == 2 || select_width == 3);
log_assert(opt_instrumentmore || select_width == 2);
log_assert(!opt_instrumentmore || select_width == 3);
}
else if (celltype == ID($_XOR_) || celltype == ID($_XNOR_)) {
else if (celltype == TW($_XOR_) || celltype == TW($_XNOR_)) {
costs = {1, 0, 0, 0};
log_assert(select_width == 2);
}
@ -184,10 +184,10 @@ private:
std::vector<RTLIL::SigSig> connections(module->connections());
for(auto &cell : module->cells().to_vector()) {
if (!cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_MUX_), ID($_NMUX_), ID($_NOT_), ID($anyconst), ID($allconst), ID($assume), ID($assert)) && module->design->module(cell->type) == nullptr) {
if (!cell->type.in(TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_), TW($_XOR_), TW($_XNOR_), TW($_MUX_), TW($_NMUX_), TW($_NOT_), TW($anyconst), TW($allconst), TW($assume), TW($assert)) && module->design->module(cell->type) == nullptr) {
log_cmd_error("Unsupported cell type \"%s\" found. Run `techmap` first.\n", cell->type);
}
if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_))) {
if (cell->type.in(TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_))) {
const unsigned int A = 0, B = 1, Y = 2;
const unsigned int NUM_PORTS = 3;
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::B), cell->getPort(TW::Y)};
@ -234,7 +234,7 @@ private:
auto select_width = log2(num_versions);
log_assert(exp2(select_width) == num_versions);
RTLIL::SigSpec meta_mux_select(module->addWire(Twine{cell->name.str() + "_sel"}, select_width));
meta_mux_selects.push_back(make_pair(meta_mux_select, cell->type));
meta_mux_selects.push_back(make_pair(meta_mux_select, RTLIL::IdString(cell->type)));
module->connect(meta_mux_select, module->Anyconst(module->design->twines.add(Twine{cell->name.str() + "_hole"}), select_width, cell->src_ref()));
std::vector<RTLIL::SigSpec> next_meta_mux_y_ports, meta_mux_y_ports(taint_version);
@ -252,7 +252,7 @@ private:
}
else log_cmd_error("This is a bug (1).\n");
}
else if (cell->type.in(ID($_XOR_), ID($_XNOR_))) {
else if (cell->type.in(TW($_XOR_), TW($_XNOR_))) {
const unsigned int A = 0, B = 1, Y = 2;
const unsigned int NUM_PORTS = 3;
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::B), cell->getPort(TW::Y)};
@ -289,7 +289,7 @@ private:
}
RTLIL::SigSpec meta_mux_select(module->addWire(Twine{cell->name.str() + "_sel"}, select_width));
meta_mux_selects.push_back(make_pair(meta_mux_select, cell->type));
meta_mux_selects.push_back(make_pair(meta_mux_select, RTLIL::IdString(cell->type)));
module->connect(meta_mux_select, module->Anyconst(module->design->twines.add(Twine{cell->name.str() + "_hole"}), select_width, cell->src_ref()));
std::vector<RTLIL::SigSpec> next_meta_mux_y_ports, meta_mux_y_ports(taint_version);
@ -308,7 +308,7 @@ private:
else log_cmd_error("This is a bug (2).\n");
}
else if (cell->type.in(ID($_MUX_), ID($_NMUX_))) {
else if (cell->type.in(TW($_MUX_), TW($_NMUX_))) {
const unsigned int A = 0, B = 1, S = 2, Y = 3;
const unsigned int NUM_PORTS = 4;
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::B), cell->getPort(TW::S), cell->getPort(TW::Y)};
@ -321,7 +321,7 @@ private:
add_precise_GLIFT_mux(cell, ports[A], port_taints[A], ports[B], port_taints[B], ports[S], port_taints[S], port_taints[Y]);
}
else if (cell->type.in(ID($_NOT_))) {
else if (cell->type.in(TW($_NOT_))) {
const unsigned int A = 0, Y = 1;
const unsigned int NUM_PORTS = 2;
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::Y)};
@ -332,7 +332,7 @@ private:
for (unsigned int i = 0; i < NUM_PORTS; ++i)
port_taints[i] = get_corresponding_taint_signal(ports[i]);
if (cell->type == ID($_NOT_)) {
if (cell->type == TW($_NOT_)) {
module->connect(port_taints[Y], port_taints[A]);
}
else log_cmd_error("This is a bug (3).\n");