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This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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2
passes/cmds/connect.cc
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@ -36,7 +36,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
for (auto cell : module->cells())
for (auto &port : cell->connections_)
if (ct.cell_output(cell->type, port.first))
if (ct.cell_output(cell->type.ref(), port.first))
sigmap(port.second).replace(sig, dummy_wire, &port.second);
bool need_fixup = false;