mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-23 07:32:32 +00:00
Code Activity

WIP

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
Download patch file Download diff file Expand all files Collapse all files

3
passes/cmds/add.cc
View file

@ -42,7 +42,8 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const
log_error("Could not find wire with name \"%s\".\n", name);
}
else {
RTLIL::Cell *formal_cell = module->addCell(NEW_TWINE, "$" + celltype);
TwineRef _type = module->design->twines.add(Twine{"$" + celltype});
RTLIL::Cell *formal_cell = module->addCell(NEW_TWINE, _type);
formal_cell->setPort(TW::A, wire);
if(enable_name == "") {
formal_cell->setPort(TW::EN, State::S1);