WIP

passes/cmds/Makefile.inc

@@ -50,7 +50,7 @@ OBJS += passes/cmds/xprop.o
 OBJS += passes/cmds/dft_tag.o
 OBJS += passes/cmds/future.o
 OBJS += passes/cmds/box_derive.o
-OBJS += passes/cmds/example_dt.o
+#OBJS += passes/cmds/example_dt.o
 OBJS += passes/cmds/portarcs.o
 OBJS += passes/cmds/wrapcell.o
 OBJS += passes/cmds/setenv.o

passes/cmds/abstract.cc

@@ -174,7 +174,7 @@ unsigned int abstract_state(Module* mod, EnableLogic enable, const std::vector<S
 	std::vector<FfData> ffs;
 	// Abstract flop inputs if they're driving a selected output rep
 	for (auto cell : mod->cells()) {
-		if (!ct.cell_types.count(cell->type))
+		if (!ct.cell_types.count(cell->type_impl))
 			continue;
 		FfData ff(nullptr, cell);
 		if (ff.has_sr)
@@ -265,7 +265,7 @@ unsigned int abstract_value(Module* mod, EnableLogic enable, const std::vector<S
 	unsigned int changed = 0;
 	std::vector<Cell*> cells_snapshot = mod->cells();
 	for (auto cell : cells_snapshot) {
-		if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
+		if (cell->type.in(TW($input_port), TW($output_port), TW($public)))
 			continue;
 		for (auto conn : cell->connections())
 			if (cell->output(conn.first)) {

passes/cmds/add.cc

@@ -42,7 +42,8 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const
 		log_error("Could not find wire with name \"%s\".\n", name);
 	}
 	else {
-		RTLIL::Cell *formal_cell = module->addCell(NEW_TWINE, "$" + celltype);
+		TwineRef _type = module->design->twines.add(Twine{"$" + celltype});
+		RTLIL::Cell *formal_cell = module->addCell(NEW_TWINE, _type);
 		formal_cell->setPort(TW::A, wire);
 		if(enable_name == "") {
 			formal_cell->setPort(TW::EN, State::S1);

passes/cmds/box_derive.cc

@@ -100,7 +100,7 @@ struct BoxDerivePass : Pass {
 					continue;
 
 				if (!done.count(index)) {
-					IdString derived_type = base->derive(d, cell->parameters);
+					TwineRef derived_type = base->derive(d, cell->parameters);
 					Module *derived = d->module(derived_type);
 					log_assert(derived && "Failed to derive module\n");
 					log("derived %s\n", derived_type);

passes/cmds/check.cc

@@ -87,7 +87,7 @@ int check_bufnorm_wire(RTLIL::Module *module, RTLIL::Wire *wire)
 			if (!dsig.is_wire() || dsig.as_wire() != wire)
 				log_warning("bufNorm: wire %s.%s driverCell_ %s port %s does not connect back to this wire\n",
 					log_id(module), log_id(wire), log_id(driver), module->design->twines.str(dport).c_str()), counter++;
-			if (wire->port_input && !wire->port_output && driver->type != ID($input_port))
+			if (wire->port_input && !wire->port_output && driver->type != TW($input_port))
 				log_warning("bufNorm: module input wire %s.%s is driven by non-$input_port cell %s of type %s\n",
 					log_id(module), log_id(wire), log_id(driver), log_id(driver->type)), counter++;
 		}
@@ -295,14 +295,14 @@ struct CheckPass : public Pass {
 					// Only those cell types for which the edge data can expode quadratically
 					// in port widths are those for us to check.
 					if (!cell->type.in(
-							ID($add), ID($sub),
-							ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),
-							ID($pmux), ID($bmux)))
+							TW($add), TW($sub),
+							TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx),
+							TW($pmux), TW($bmux)))
 						return false;
 
 					int in_widths = 0, out_widths = 0;
 
-					if (cell->type.in(ID($pmux), ID($bmux))) {
+					if (cell->type.in(TW($pmux), TW($bmux))) {
 						// We're skipping inputs A and B, since each of their bits contributes only one edge
 						in_widths = GetSize(cell->getPort(TW::S));
 						out_widths = GetSize(cell->getPort(TW::Y));
@@ -358,17 +358,17 @@ struct CheckPass : public Pass {
 			pool<Cell *> coarsened_cells;
 			for (auto cell : module->cells())
 			{
-				if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
+				if (cell->type.in(TW($input_port), TW($output_port), TW($public)))
 					continue;
 
 				if (mapped && cell->type.begins_with("$") && design->module(cell->type) == nullptr) {
-					if (allow_tbuf && cell->type == ID($_TBUF_)) goto cell_allowed;
-					log_warning("Cell %s.%s is an unmapped internal cell of type %s.\n", module, cell, cell->type.unescape());
+					if (allow_tbuf && cell->type == TW($_TBUF_)) goto cell_allowed;
+					log_warning("Cell %s.%s is an unmapped internal cell of type %s.\n", module, cell, cell->type.unescaped());
 					counter++;
 				cell_allowed:;
 				}
 
-				if (cell->type == ID($connect)) {
+				if (cell->type == TW($connect)) {
 					// Inefficient, but rare case in sane design
 					auto sig_a = cell->getPort(TW::A);
 					auto sig_b = cell->getPort(TW::B);
@@ -406,13 +406,13 @@ struct CheckPass : public Pass {
 						wire_drivers_count[bit]++;
 						if (output && (bit.wire || !input))
 							wire_drivers[bit].push_back(stringf("port %s[%d] of cell %s (%s)", cell->module->design->twines.str(conn.first).c_str(), i,
-																cell, cell->type.unescape()));
+																cell, cell->type.unescaped()));
 						if (output)
 							driver_cells[bit] = cell;
 					}
 				}
 
-				if (yosys_celltypes.cell_evaluable(cell->type) || cell->type.in(ID($mem_v2), ID($memrd), ID($memrd_v2)) \
+				if (yosys_celltypes.cell_evaluable(cell->type.ref()) || cell->type.in(TW($mem_v2), TW($memrd), TW($memrd_v2)) \
 						|| cell->is_builtin_ff()) {
 					if (!edges_db.add_edges_from_cell(cell))
 						coarsened_cells.insert(cell);
@@ -529,7 +529,7 @@ struct CheckPass : public Pass {
 						driver_src = stringf(" source: %s", src_attr);
 					}
 
-					message += stringf("    cell %s (%s)%s\n", driver, driver->type.unescape(), driver_src);
+					message += stringf("    cell %s (%s)%s\n", driver, design->twines.unescaped_str(driver->type), driver_src);
 
 					if (!coarsened_cells.count(driver)) {						
 						MatchingEdgePrinter printer(message, sigmap, prev, bit);

passes/cmds/chformal.cc

@@ -24,42 +24,42 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-static RTLIL::IdString formal_flavor(RTLIL::Cell *cell)
+static TwineRef formal_flavor(RTLIL::Cell *cell)
 {
-	if (cell->type != ID($check))
-		return cell->type;
+	if (cell->type != TW($check))
+		return cell->type_impl;
 
 	std::string flavor_param = cell->getParam(ID(FLAVOR)).decode_string();
 	if (flavor_param == "assert")
-		return ID($assert);
+		return TW($assert);
 	else if (flavor_param == "assume")
-		return ID($assume);
+		return TW($assume);
 	else if (flavor_param == "cover")
-		return ID($cover);
+		return TW($cover);
 	else if (flavor_param == "live")
-		return ID($live);
+		return TW($live);
 	else if (flavor_param == "fair")
-		return ID($fair);
+		return TW($fair);
 	else
 		log_abort();
 }
 
-static void set_formal_flavor(RTLIL::Cell *cell, RTLIL::IdString flavor)
+static void set_formal_flavor(RTLIL::Cell *cell, TwineRef flavor)
 {
-	if (cell->type != ID($check)) {
-		cell->type_impl = cell->module->design->twines.add(Twine{flavor.str()});
+	if (cell->type != TW($check)) {
+		cell->type_impl = flavor;
 		return;
 	}
 
-	if (flavor == ID($assert))
+	if (flavor == TW($assert))
 		cell->setParam(ID(FLAVOR), std::string("assert"));
-	else if (flavor == ID($assume))
+	else if (flavor == TW($assume))
 		cell->setParam(ID(FLAVOR), std::string("assume"));
-	else if (flavor == ID($cover))
+	else if (flavor == TW($cover))
 		cell->setParam(ID(FLAVOR), std::string("cover"));
-	else if (flavor == ID($live))
+	else if (flavor == TW($live))
 		cell->setParam(ID(FLAVOR), std::string("live"));
-	else if (flavor == ID($fair))
+	else if (flavor == TW($fair))
 		cell->setParam(ID(FLAVOR), std::string("fair"));
 	else
 		log_abort();
@@ -67,7 +67,7 @@ static void set_formal_flavor(RTLIL::Cell *cell, RTLIL::IdString flavor)
 
 static bool is_triggered_check_cell(RTLIL::Cell * cell)
 {
-	return cell->type == ID($check) && cell->getParam(ID(TRG_ENABLE)).as_bool();
+	return cell->type == TW($check) && cell->getParam(ID(TRG_ENABLE)).as_bool();
 }
 
 struct ChformalPass : public Pass {
@@ -136,7 +136,7 @@ struct ChformalPass : public Pass {
 		bool live2fair = false;
 		bool fair2live = false;
 
-		pool<IdString> constr_types;
+		pool<TwineRef> constr_types;
 		char mode = 0;
 		int mode_arg = 0;
 
@@ -144,23 +144,23 @@ struct ChformalPass : public Pass {
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
 			if (args[argidx] == "-assert") {
-				constr_types.insert(ID($assert));
+				constr_types.insert(TW($assert));
 				continue;
 			}
 			if (args[argidx] == "-assume") {
-				constr_types.insert(ID($assume));
+				constr_types.insert(TW($assume));
 				continue;
 			}
 			if (args[argidx] == "-live") {
-				constr_types.insert(ID($live));
+				constr_types.insert(TW($live));
 				continue;
 			}
 			if (args[argidx] == "-fair") {
-				constr_types.insert(ID($fair));
+				constr_types.insert(TW($fair));
 				continue;
 			}
 			if (args[argidx] == "-cover") {
-				constr_types.insert(ID($cover));
+				constr_types.insert(TW($cover));
 				continue;
 			}
 			if (mode == 0 && args[argidx] == "-remove") {
@@ -222,11 +222,11 @@ struct ChformalPass : public Pass {
 		design->sigNormalize(false);
 
 		if (constr_types.empty()) {
-			constr_types.insert(ID($assert));
-			constr_types.insert(ID($assume));
-			constr_types.insert(ID($live));
-			constr_types.insert(ID($fair));
-			constr_types.insert(ID($cover));
+			constr_types.insert(TW($assert));
+			constr_types.insert(TW($assume));
+			constr_types.insert(TW($live));
+			constr_types.insert(TW($fair));
+			constr_types.insert(TW($cover));
 		}
 
 		if (assert2assume && assert2cover) {
@@ -274,13 +274,13 @@ struct ChformalPass : public Pass {
 
 				for (auto cell : module->selected_cells())
 				{
-					if (cell->type == ID($ff)) {
+					if (cell->type == TW($ff)) {
 						SigSpec D = sigmap(cell->getPort(TW::D));
 						SigSpec Q = sigmap(cell->getPort(TW::Q));
 						for (int i = 0; i < GetSize(D); i++)
 							ffmap[Q[i]] = make_pair(D[i], make_pair(State::Sm, false));
 					}
-					if (cell->type == ID($dff)) {
+					if (cell->type == TW($dff)) {
 						SigSpec D = sigmap(cell->getPort(TW::D));
 						SigSpec Q = sigmap(cell->getPort(TW::Q));
 						SigSpec C = sigmap(cell->getPort(TW::CLK));
@@ -301,7 +301,7 @@ struct ChformalPass : public Pass {
 						cell->setParam(ID::TRG_POLARITY, false);
 					}
 
-					IdString flavor = formal_flavor(cell);
+					TwineRef flavor = formal_flavor(cell);
 
 					while (true)
 					{
@@ -312,8 +312,8 @@ struct ChformalPass : public Pass {
 							break;
 
 						if (!init_zero.count(EN)) {
-							if (flavor == ID($cover)) break;
-							if (flavor.in(ID($assert), ID($assume)) && !init_one.count(A)) break;
+							if (flavor == TW($cover)) break;
+							if (flavor.in(TW($assert), TW($assume)) && !init_one.count(A)) break;
 						}
 
 						const auto &A_map = ffmap.at(A);
@@ -372,8 +372,8 @@ struct ChformalPass : public Pass {
 			{
 				for (auto cell : constr_cells)
 				{
-					if (cell->type == ID($check)) {
-						Cell *cover = module->addCell(NEW_TWINE_SUFFIX("coverenable"), ID($check));
+					if (cell->type == TW($check)) {
+						Cell *cover = module->addCell(NEW_TWINE_SUFFIX("coverenable"), TW::$check);
 						cover->attributes = cell->attributes;
 						if (cell->src_id() != Twine::Null && module->design)
 							cover->set_src_id(cell->src_id());
@@ -395,24 +395,24 @@ struct ChformalPass : public Pass {
 			if (mode == 'c')
 			{
 				for (auto cell : constr_cells) {
-					IdString flavor = formal_flavor(cell);
-					if (assert2assume && flavor == ID($assert))
-						set_formal_flavor(cell, ID($assume));
-					if (assert2cover && flavor == ID($assert))
-						set_formal_flavor(cell, ID($cover));
-					else if (assume2assert && flavor == ID($assume))
-						set_formal_flavor(cell, ID($assert));
-					else if (live2fair && flavor == ID($live))
-						set_formal_flavor(cell, ID($fair));
-					else if (fair2live && flavor == ID($fair))
-						set_formal_flavor(cell, ID($live));
+					TwineRef flavor = formal_flavor(cell);
+					if (assert2assume && flavor == TW($assert))
+						set_formal_flavor(cell, TW($assume));
+					if (assert2cover && flavor == TW($assert))
+						set_formal_flavor(cell, TW($cover));
+					else if (assume2assert && flavor == TW($assume))
+						set_formal_flavor(cell, TW($assert));
+					else if (live2fair && flavor == TW($live))
+						set_formal_flavor(cell, TW($fair));
+					else if (fair2live && flavor == TW($fair))
+						set_formal_flavor(cell, TW($live));
 				}
 			}
 			else
 			if (mode == 'l')
 			{
 				for (auto cell : constr_cells) {
-					if (cell->type != ID($check))
+					if (cell->type != TW($check))
 						continue;
 
 					if (is_triggered_check_cell(cell))
@@ -431,7 +431,7 @@ struct ChformalPass : public Pass {
 					plain_cell->setPort(TW::A, sig_a);
 					plain_cell->setPort(TW::EN, sig_en);
 
-					if (plain_cell->type.in(ID($assert), ID($assume)))
+					if (plain_cell->type.in(TW($assert), TW($assume)))
 						sig_a = module->Not(NEW_TWINE, sig_a);
 
 					SigBit combined_en = module->And(NEW_TWINE, sig_a, sig_en);

passes/cmds/clean_zerowidth.cc

@@ -66,7 +66,7 @@ struct CleanZeroWidthPass : public Pass {
 		{
 			for (auto cell : module->selected_cells())
 			{
-				if (!ct.cell_known(cell->type)) {
+				if (!ct.cell_known(cell->type_impl)) {
 					// User-defined cell: just prune zero-width connections.
 					for (auto it: cell->connections()) {
 						if (GetSize(it.second) == 0) {
@@ -80,7 +80,7 @@ struct CleanZeroWidthPass : public Pass {
 					if (GetSize(cell->getPort(TW::Q)) == 0) {
 						module->remove(cell);
 					}
-				} else if (cell->type.in(ID($pmux), ID($bmux), ID($demux))) {
+				} else if (cell->type.in(TW($pmux), TW($bmux), TW($demux))) {
 					// Remove altogether if WIDTH is 0, replace with
 					// a connection if S_WIDTH is 0.
 					if (cell->getParam(ID::WIDTH).as_int() == 0) {
@@ -90,7 +90,7 @@ struct CleanZeroWidthPass : public Pass {
 						module->connect(cell->getPort(TW::Y), cell->getPort(TW::A));
 						module->remove(cell);
 					}
-				} else if (cell->type == ID($concat)) {
+				} else if (cell->type == TW($concat)) {
 					// If a concat has a zero-width input: replace with direct
 					// connection to the other input.
 					if (cell->getParam(ID::A_WIDTH).as_int() == 0) {
@@ -100,17 +100,17 @@ struct CleanZeroWidthPass : public Pass {
 						module->connect(cell->getPort(TW::Y), cell->getPort(TW::A));
 						module->remove(cell);
 					}
-				} else if (cell->type == ID($fsm)) {
+				} else if (cell->type == TW($fsm)) {
 					// TODO: not supported
 				} else if (cell->is_mem_cell()) {
 					// Skip — will be handled below.
-				} else if (cell->type == ID($lut)) {
+				} else if (cell->type == TW($lut)) {
 					// Zero-width LUT is just a const driver.
 					if (cell->getParam(ID::WIDTH).as_int() == 0) {
 						module->connect(cell->getPort(TW::Y), cell->getParam(ID::LUT)[0]);
 						module->remove(cell);
 					}
-				} else if (cell->type == ID($sop)) {
+				} else if (cell->type == TW($sop)) {
 					// Zero-width SOP is just a const driver.
 					if (cell->getParam(ID::WIDTH).as_int() == 0) {
 						// The value is 1 iff DEPTH is non-0.
@@ -128,7 +128,7 @@ struct CleanZeroWidthPass : public Pass {
 					// A and B to 1-bit if their width is 0.
 					if (cell->getParam(ID::Y_WIDTH).as_int() == 0) {
 						module->remove(cell);
-					} else if (cell->type.in(ID($macc), ID($macc_v2))) {
+					} else if (cell->type.in(TW($macc), TW($macc_v2))) {
 						// TODO: fixing zero-width A and B not supported.
 					} else {
 						if (cell->getParam(ID::A_WIDTH).as_int() == 0) {

passes/cmds/connect.cc

@@ -36,7 +36,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
 
 	for (auto cell : module->cells())
 	for (auto &port : cell->connections_)
-		if (ct.cell_output(cell->type, port.first))
+		if (ct.cell_output(cell->type.ref(), port.first))
 			sigmap(port.second).replace(sig, dummy_wire, &port.second);
 
 	bool need_fixup = false;

passes/cmds/design.cc

@@ -268,7 +268,7 @@ struct DesignPass : public Pass {
 			{
 				log("Importing %s as %s.\n", mod, RTLIL::unescape_id(prefix));
 
-				RTLIL::Module *t = mod->clone(copy_to_design, RTLIL::IdString(prefix));
+				RTLIL::Module *t = mod->clone(copy_to_design, copy_to_design->twines.add(Twine{prefix}));
 				t->attributes.erase(ID::top);
 
 				queue.insert(t);
@@ -297,7 +297,7 @@ struct DesignPass : public Pass {
 						if (copy_to_design->module(trg_name) != nullptr)
 							copy_to_design->remove(copy_to_design->module(trg_name));
 
-						RTLIL::Module *t = fmod->clone(copy_to_design, RTLIL::IdString(trg_name));
+						RTLIL::Module *t = fmod->clone(copy_to_design, copy_to_design->twines.add(Twine{trg_name}));
 						t->attributes.erase(ID::top);
 
 						queue.insert(t);
@@ -321,7 +321,7 @@ struct DesignPass : public Pass {
 				if (copy_to_design->module(trg_name) != nullptr)
 					copy_to_design->remove(copy_to_design->module(trg_name));
 
-				mod->clone(copy_to_design, RTLIL::IdString(trg_name));
+				mod->clone(copy_to_design, copy_to_design->twines.add(Twine{trg_name}));
 			}
 		}
 

passes/cmds/dft_tag.cc

@@ -90,10 +90,10 @@ struct DftTagWorker {
 		bool design_changed = false;
 
 		for (auto cell : module->cells()) {
-			if (cell->type == ID($overwrite_tag))
+			if (cell->type == TW($overwrite_tag))
 				overwrite_cells.push_back(cell);
 
-			if (cell->type == ID($original_tag))
+			if (cell->type == TW($original_tag))
 				original_cells.push_back(cell);
 		}
 
@@ -137,7 +137,7 @@ struct DftTagWorker {
 		if (found == modwalker.signal_consumers.end())
 			return;
 		for (auto &consumer : found->second) {
-			if (consumer.cell->type.in(ID($original_tag)))
+			if (consumer.cell->type.in(TW($original_tag)))
 				continue;
 			if (sigmap(consumer.cell->getPort(consumer.port)[consumer.offset]) != driver_bit)
 				continue;
@@ -249,7 +249,7 @@ struct DftTagWorker {
 	void propagate_tags()
 	{
 		for (auto cell : module->cells()) {
-			if (cell->type == ID($set_tag)) {
+			if (cell->type == TW($set_tag)) {
 				pending_cells.insert(cell);
 				pending_cell_queue.push_back(cell);
 			}
@@ -371,7 +371,7 @@ struct DftTagWorker {
 
 	void propagate_tags(Cell *cell)
 	{
-		if (cell->type == ID($set_tag)) {
+		if (cell->type == TW($set_tag)) {
 			IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string());
 			if (all_tags.insert(tag).second) {
 				auto group_sep = tag.str().find(':');
@@ -388,25 +388,25 @@ struct DftTagWorker {
 			return;
 		}
 
-		if (cell->type == ID($get_tag)) {
+		if (cell->type == TW($get_tag)) {
 			return;
 		}
 
-		if (cell->type.in(ID($not), ID($pos))) {
+		if (cell->type.in(TW($not), TW($pos))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A);
-			if (cell->type.in(ID($not), ID($or))) {
+			if (cell->type.in(TW($not), TW($or))) {
 				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
 			}
 			forward_tags(sig_y, sig_a);
 			return;
 		}
 
-		if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($bweqx))) {
+		if (cell->type.in(TW($and), TW($or), TW($xor), TW($xnor), TW($bweqx))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A);
 			auto sig_b = cell->getPort(TW::B);
-			if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
+			if (cell->type.in(TW($and), TW($or), TW($xor), TW($xnor))) {
 				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
 				sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
 			}
@@ -415,13 +415,13 @@ struct DftTagWorker {
 			return;
 		}
 
-		if (cell->type.in(ID($mux), ID($bwmux))) {
+		if (cell->type.in(TW($mux), TW($bwmux))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto &sig_a = cell->getPort(TW::A);
 			auto &sig_b = cell->getPort(TW::B);
 			auto sig_s = cell->getPort(TW::S);
 
-			if (cell->type == ID($mux))
+			if (cell->type == TW($mux))
 				sig_s = SigSpec(sig_s[0], GetSize(sig_y));
 
 			forward_tags(sig_y, sig_a);
@@ -430,7 +430,7 @@ struct DftTagWorker {
 			return;
 		}
 
-		if (cell->is_builtin_ff() || cell->type == ID($anyinit)) {
+		if (cell->is_builtin_ff() || cell->type == TW($anyinit)) {
 			FfData ff(&initvals, cell);
 
 			if (ff.has_clk || ff.has_gclk)
@@ -440,10 +440,10 @@ struct DftTagWorker {
 
 		// Single output but, sensitive to all inputs
 		if (cell->type.in(
-			ID($le), ID($lt), ID($ge), ID($gt),
-			ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor),
-			ID($reduce_bool), ID($logic_not), ID($logic_or), ID($logic_and),
-			ID($eq), ID($ne)
+			TW($le), TW($lt), TW($ge), TW($gt),
+			TW($reduce_and), TW($reduce_or), TW($reduce_xor), TW($reduce_xnor),
+			TW($reduce_bool), TW($logic_not), TW($logic_or), TW($logic_and),
+			TW($eq), TW($ne)
 		)) {
 			auto &sig_y = cell->getPort(TW::Y);
 
@@ -456,10 +456,10 @@ struct DftTagWorker {
 		add_tags(cell, tags(cell));
 
 		if (cell->type.in(
-			ID($_AND_), ID($_OR_), ID($_NAND_), ID($_NOR_), ID($_ANDNOT_), ID($_ORNOT_),
-			ID($_XOR_), ID($_XNOR_), ID($_NOT_), ID($_BUF_), ID($_MUX_),
+			TW($_AND_), TW($_OR_), TW($_NAND_), TW($_NOR_), TW($_ANDNOT_), TW($_ORNOT_),
+			TW($_XOR_), TW($_XNOR_), TW($_NOT_), TW($_BUF_), TW($_MUX_),
 
-			ID($assert), ID($assume)
+			TW($assert), TW($assume)
 		)) {
 			return;
 		}
@@ -477,7 +477,7 @@ struct DftTagWorker {
 
 	void process_cell(IdString tag, Cell *cell)
 	{
-		if (cell->type == ID($set_tag)) {
+		if (cell->type == TW($set_tag)) {
 			IdString cell_tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string());
 
 			auto tag_sig_a = tag_signal(tag, cell->getPort(TW::A));
@@ -494,14 +494,14 @@ struct DftTagWorker {
 			return;
 		}
 
-		if (cell->type == ID($get_tag)) {
+		if (cell->type == TW($get_tag)) {
 			log_assert(false);
 		}
 
-		if (cell->type.in(ID($not), ID($pos), ID($_NOT_), ID($_BUF_))) {
+		if (cell->type.in(TW($not), TW($pos), TW($_NOT_), TW($_BUF_))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A);
-			if (cell->type.in(ID($not), ID($or))) {
+			if (cell->type.in(TW($not), TW($or))) {
 				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
 			}
 			emit_tag_signal(tag, sig_y, tag_signal(tag, sig_a));
@@ -509,13 +509,13 @@ struct DftTagWorker {
 		}
 
 		if (cell->type.in(
-			ID($and), ID($or),
-			ID($_AND_), ID($_OR_), ID($_NAND_), ID($_NOR_), ID($_ANDNOT_), ID($_ORNOT_)
+			TW($and), TW($or),
+			TW($_AND_), TW($_OR_), TW($_NAND_), TW($_NOR_), TW($_ANDNOT_), TW($_ORNOT_)
 		)) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A);
 			auto sig_b = cell->getPort(TW::B);
-			if (cell->type.in(ID($and), ID($or))) {
+			if (cell->type.in(TW($and), TW($or))) {
 				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
 				sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
 			}
@@ -523,9 +523,9 @@ struct DftTagWorker {
 			bool inv_a = false;
 			bool inv_b = false;
 
-			if (cell->type.in(ID($or), ID($_OR_), ID($_NOR_), ID($_ORNOT_)))
+			if (cell->type.in(TW($or), TW($_OR_), TW($_NOR_), TW($_ORNOT_)))
 				inv_a ^= true, inv_b ^= true;
-			if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
+			if (cell->type.in(TW($_ANDNOT_), TW($_ORNOT_)))
 				inv_b ^= true;
 
 			if (inv_a)
@@ -554,11 +554,11 @@ struct DftTagWorker {
 			return;
 		}
 
-		if (cell->type.in(ID($xor), ID($xnor), ID($bweqx), ID($_XOR_), ID($_XNOR_))) {
+		if (cell->type.in(TW($xor), TW($xnor), TW($bweqx), TW($_XOR_), TW($_XNOR_))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A);
 			auto sig_b = cell->getPort(TW::B);
-			if (cell->type.in(ID($xor), ID($xnor))) {
+			if (cell->type.in(TW($xor), TW($xnor))) {
 				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
 				sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
 			}
@@ -572,13 +572,13 @@ struct DftTagWorker {
 		}
 
 
-		if (cell->type.in(ID($_MUX_), ID($mux), ID($bwmux))) {
+		if (cell->type.in(TW($_MUX_), TW($mux), TW($bwmux))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto &sig_a = cell->getPort(TW::A);
 			auto &sig_b = cell->getPort(TW::B);
 			auto sig_s = cell->getPort(TW::S);
 
-			if (cell->type == ID($mux))
+			if (cell->type == TW($mux))
 				sig_s = SigSpec(sig_s[0], GetSize(sig_y));
 
 			auto group_sig_a = tag_group_signal(tag, sig_a);
@@ -606,7 +606,7 @@ struct DftTagWorker {
 			return;
 		}
 
-		if (cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex))) {
+		if (cell->type.in(TW($eq), TW($ne), TW($eqx), TW($nex))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A);
 			auto sig_b = cell->getPort(TW::B);
@@ -635,7 +635,7 @@ struct DftTagWorker {
 		}
 
 
-		if (cell->type.in(ID($lt), ID($gt), ID($le), ID($ge))) {
+		if (cell->type.in(TW($lt), TW($gt), TW($le), TW($ge))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A);
 			auto sig_b = cell->getPort(TW::B);
@@ -643,7 +643,7 @@ struct DftTagWorker {
 			sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool());
 			sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool());
 
-			if (cell->type.in(ID($gt), ID($le)))
+			if (cell->type.in(TW($gt), TW($le)))
 				std::swap(sig_a, sig_b);
 
 			auto group_sig_a = tag_group_signal(tag, sig_a);
@@ -666,14 +666,14 @@ struct DftTagWorker {
 			return;
 		}
 
-		if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($logic_not))) {
+		if (cell->type.in(TW($reduce_and), TW($reduce_or), TW($reduce_bool), TW($logic_not))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A);
 
 			auto group_sig_a = tag_group_signal(tag, sig_a);
 			auto tag_sig_a = tag_signal(tag, sig_a);
 
-			if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not)))
+			if (cell->type.in(TW($reduce_or), TW($reduce_bool), TW($logic_not)))
 				sig_a = autoNot(NEW_TWINE, sig_a);
 
 			auto filled = autoOr(NEW_TWINE, sig_a, group_sig_a);
@@ -686,12 +686,12 @@ struct DftTagWorker {
 			return;
 		}
 
-		if (cell->is_builtin_ff() || cell->type == ID($anyinit)) {
+		if (cell->is_builtin_ff() || cell->type == TW($anyinit)) {
 			FfData ff(&initvals, cell);
 			// TODO handle some more variants
 			if ((ff.has_clk || ff.has_gclk) && !ff.has_ce && !ff.has_aload && !ff.has_srst && !ff.has_arst && !ff.has_sr) {
 				if (ff.has_clk && !tags(ff.sig_clk).empty())
-					log_warning("Tags on CLK input ignored for %s (%s)\n", cell, cell->type.unescape());
+					log_warning("Tags on CLK input ignored for %s (%s)\n", cell, cell->type);
 
 				int width = ff.width;
 
@@ -709,7 +709,7 @@ struct DftTagWorker {
 				emit_tag_signal(tag, sig_q, ff.sig_q);
 				return;
 			} else {
-				log_warning("Unhandled FF-cell %s (%s), consider running clk2fflogic, async2sync and/or dffunmap\n", cell, cell->type.unescape());
+				log_warning("Unhandled FF-cell %s (%s), consider running clk2fflogic, async2sync and/or dffunmap\n", cell, cell->type);
 
 				// For unhandled FFs, the default propagation would cause combinational loops
 				emit_tag_signal(tag, ff.sig_q, Const(0, ff.width));
@@ -739,7 +739,7 @@ struct DftTagWorker {
 		// which is an over-approximation (unless the cell is a module that
 		// generates tags itself in which case it could be arbitrary).
 		if (warned_cells.insert(cell).second)
-			log_warning("Unhandled cell %s (%s) while emitting tag signals\n", cell, cell->type.unescape());
+			log_warning("Unhandled cell %s (%s) while emitting tag signals\n", cell, cell->type);
 	}
 
 	void emit_tags()
@@ -747,7 +747,7 @@ struct DftTagWorker {
 		warned_cells.clear();
 		std::vector<Cell *> get_tag_cells;
 		for (auto cell : module->selected_cells())
-			if (cell->type == ID($get_tag))
+			if (cell->type == TW($get_tag))
 				get_tag_cells.push_back(cell);
 
 		for (auto cell : get_tag_cells) {
@@ -798,13 +798,13 @@ struct DftTagWorker {
 		std::vector<Cell *> get_tag_cells;
 		std::vector<Cell *> set_tag_cells;
 		for (auto cell : module->cells()) {
-			if (cell->type == ID($get_tag))
+			if (cell->type == TW($get_tag))
 				get_tag_cells.push_back(cell);
 
-			if (cell->type == ID($set_tag))
+			if (cell->type == TW($set_tag))
 				set_tag_cells.push_back(cell);
 
-			log_assert(!cell->type.in(ID($overwrite_tag), ID($original_tag)));
+			log_assert(!cell->type.in(TW($overwrite_tag), TW($original_tag)));
 		}
 
 		for (auto cell : set_tag_cells) {

passes/cmds/edgetypes.cc

@@ -92,12 +92,12 @@ struct EdgetypePass : public Pass {
 				auto sink_bit_index = std::get<2>(sink);
 
 				string source_str = multibit_ports.count(std::pair<IdString, TwineRef>(source_cell_type, source_port_name)) ?
-						stringf("%s.%s[%d]", source_cell_type.unescape(), module->design->twines.str(source_port_name).c_str(), source_bit_index) :
-						stringf("%s.%s", source_cell_type.unescape(), module->design->twines.str(source_port_name).c_str());
+						stringf("%s.%s[%d]", design->twines.unescaped_str(source_cell_type), module->design->twines.str(source_port_name).c_str(), source_bit_index) :
+						stringf("%s.%s", design->twines.unescaped_str(source_cell_type), module->design->twines.str(source_port_name).c_str());
 
 				string sink_str = multibit_ports.count(std::pair<IdString, TwineRef>(sink_cell_type, sink_port_name)) ?
-						stringf("%s.%s[%d]", sink_cell_type.unescape(), module->design->twines.str(sink_port_name).c_str(), sink_bit_index) :
-						stringf("%s.%s", sink_cell_type.unescape(), module->design->twines.str(sink_port_name).c_str());
+						stringf("%s.%s[%d]", design->twines.unescaped_str(sink_cell_type), module->design->twines.str(sink_port_name).c_str(), sink_bit_index) :
+						stringf("%s.%s", design->twines.unescaped_str(sink_cell_type), module->design->twines.str(sink_port_name).c_str());
 
 				edge_cache.insert(source_str + " " + sink_str);
 			}

passes/cmds/example_dt.cc

@@ -77,13 +77,13 @@ struct ExampleDtPass : public Pass
 			auto enqueue = [&](DriveSpec const &spec) {
 				int index = queue(spec);
 				if (index == GetSize(graph_nodes))
-					graph_nodes.emplace_back(compute_graph.add(ID($pending), index).index());
+					graph_nodes.emplace_back(compute_graph.add(TW($pending), index).index());
 				//if (index >= GetSize(graph_nodes))
 				return compute_graph[graph_nodes[index]];
 			};
 
 			for (auto cell : module->cells()) {
-				if (cell->type.in(ID($assert), ID($assume), ID($cover), ID($check)))
+				if (cell->type.in(TW($assert), TW($assume), TW($cover), TW($check)))
 					enqueue(DriveBitMarker(cells(cell), 0));
 			}
 
@@ -99,7 +99,7 @@ struct ExampleDtPass : public Pass
 				ExampleGraph::Ref node = compute_graph[i];
 
 				if (spec.chunks().size() > 1) {
-					node.set_function(ID($$concat));
+					node.set_function(TW($$concat));
 
 					for (auto const &chunk : spec.chunks()) {
 						node.append_arg(enqueue(chunk));
@@ -111,39 +111,39 @@ struct ExampleDtPass : public Pass
 						if (wire_chunk.is_whole()) {
 							node.sparse_attr() = wire_chunk.wire->name;
 							if (wire_chunk.wire->port_input) {
-								node.set_function(ExampleFn(ID($$input), {{wire_chunk.wire->name, {}}}));
+								node.set_function(ExampleFn(TW($$input), {{wire_chunk.wire->name, {}}}));
 							} else {
 								DriveSpec driver = dm(DriveSpec(wire_chunk));
-								node.set_function(ID($$buf));
+								node.set_function(TW($$buf));
 
 								node.append_arg(enqueue(driver));
 							}
 						} else {
 							DriveChunkWire whole_wire(wire_chunk.wire, 0, wire_chunk.wire->width);
-							node.set_function(ExampleFn(ID($$slice), {{ID(offset), wire_chunk.offset}, {ID(width), wire_chunk.width}}));
+							node.set_function(ExampleFn(TW($$slice), {{ID(offset), wire_chunk.offset}, {ID(width), wire_chunk.width}}));
 							node.append_arg(enqueue(whole_wire));
 						}
 					} else if (chunk.is_port()) {
 						DriveChunkPort port_chunk = chunk.port();
 						if (port_chunk.is_whole()) {
-							if (dm.celltypes.cell_output(port_chunk.cell->type, port_chunk.port)) {
-								if (port_chunk.cell->type.in(ID($dff), ID($ff)))
+							if (dm.celltypes.cell_output(port_chunk.cell->type_impl, port_chunk.port)) {
+								if (port_chunk.cell->type.in(TW($dff), TW($ff)))
 								{
 									Cell *cell = port_chunk.cell;
-									node.set_function(ExampleFn(ID($$state), {{cell->name, {}}}));
+									node.set_function(ExampleFn(TW($$state), {{cell->name, {}}}));
 									for (auto const &conn : cell->connections()) {
-										if (!dm.celltypes.cell_input(cell->type, conn.first))
+										if (!dm.celltypes.cell_input(cell->type_impl, conn.first))
 											continue;
 										enqueue(DriveChunkPort(cell, conn)).assign_key(cell->name);
 									}
 								}
 								else
 								{
-									node.set_function(ExampleFn(ID($$cell_output), {{RTLIL::escape_id(module->design->twines.str(port_chunk.port)), {}}}));
+									node.set_function(ExampleFn(TW($$cell_output), {{RTLIL::escape_id(module->design->twines.str(port_chunk.port)), {}}}));
 									node.append_arg(enqueue(DriveBitMarker(cells(port_chunk.cell), 0)));
 								}
 							} else {
-								node.set_function(ID($$buf));
+								node.set_function(TW($$buf));
 
 								DriveSpec driver = dm(DriveSpec(port_chunk));
 								node.append_arg(enqueue(driver));
@@ -151,14 +151,14 @@ struct ExampleDtPass : public Pass
 
 						} else {
 							DriveChunkPort whole_port(port_chunk.cell, port_chunk.port, 0, GetSize(port_chunk.cell->connections().at(port_chunk.port)));
-							node.set_function(ExampleFn(ID($$slice), {{ID(offset), port_chunk.offset}}));
+							node.set_function(ExampleFn(TW($$slice), {{ID(offset), port_chunk.offset}}));
 							node.append_arg(enqueue(whole_port));
 						}
 					} else if (chunk.is_constant()) {
-						node.set_function(ExampleFn(ID($$const), {{ID(value), chunk.constant()}}));
+						node.set_function(ExampleFn(TW($$const), {{ID(value), chunk.constant()}}));
 
 					} else if (chunk.is_multiple()) {
-						node.set_function(ID($$multi));
+						node.set_function(TW($$multi));
 						for (auto const &driver : chunk.multiple().multiple())
 							node.append_arg(enqueue(driver));
 					} else if (chunk.is_marker()) {
@@ -166,13 +166,13 @@ struct ExampleDtPass : public Pass
 
 						node.set_function(ExampleFn(cell->type, cell->parameters));
 						for (auto const &conn : cell->connections()) {
-							if (!dm.celltypes.cell_input(cell->type, conn.first))
+							if (!dm.celltypes.cell_input(cell->type_impl, conn.first))
 								continue;
 
 							node.append_arg(enqueue(DriveChunkPort(cell, conn)));
 						}
 					} else if (chunk.is_none()) {
-						node.set_function(ID($$undriven));
+						node.set_function(TW($$undriven));
 
 					} else {
 						log_error("unhandled drivespec: %s\n", log_signal(chunk));
@@ -208,7 +208,7 @@ struct ExampleDtPass : public Pass
 
 			for (int i = 0; i < compute_graph.size(); ++i)
 			{
-				if (compute_graph[i].function().name == ID($$buf) && !compute_graph[i].has_sparse_attr() && compute_graph[i].arg(0).index() < i)
+				if (compute_graph[i].function().name == TW($$buf) && !compute_graph[i].has_sparse_attr() && compute_graph[i].arg(0).index() < i)
 				{
 
 					alias.push_back(alias[compute_graph[i].arg(0).index()]);

passes/cmds/future.cc

@@ -50,7 +50,7 @@ struct FutureWorker {
 
 		std::vector<Cell *> replaced_cells;
 		for (auto cell : module->selected_cells()) {
-			if (cell->type != ID($future_ff))
+			if (cell->type != TW($future_ff))
 				continue;
 
 			module->connect(cell->getPort(TW::Y), future_ff(cell->getPort(TW::A)));
@@ -92,7 +92,7 @@ struct FutureWorker {
 
 		if (!ff.has_clk && !ff.has_gclk)
 			log_error("Driver for future_ff target signal %s has cell type %s, which is not clocked\n", log_signal(bit),
-				  driver.cell->type.unescape());
+				  driver.cell->type);
 
 		ff.unmap_ce_srst();
 

passes/cmds/glift.cc

@@ -70,7 +70,7 @@ private:
 
 	void add_precise_GLIFT_logic(const RTLIL::Cell *cell, RTLIL::SigSpec &port_a, RTLIL::SigSpec &port_a_taint, RTLIL::SigSpec &port_b, RTLIL::SigSpec &port_b_taint, RTLIL::SigSpec &port_y_taint) {
 		//AKA AN2_SH2 or OR2_SH2
-		bool is_and = cell->type.in(ID($_AND_), ID($_NAND_));
+		bool is_and = cell->type.in(TW($_AND_), TW($_NAND_));
 		RTLIL::SigSpec n_port_a = module->LogicNot(Twine{cell->name.str() + "_t_1_1"}, port_a, false, cell->src_ref());
 		RTLIL::SigSpec n_port_b = module->LogicNot(Twine{cell->name.str() + "_t_1_2"}, port_b, false, cell->src_ref());
 		auto subexpr1 = module->And(Twine{cell->name.str() + "_t_1_3"}, is_and? port_a : n_port_a, port_b_taint, false, cell->src_ref());
@@ -82,7 +82,7 @@ private:
 
 	void add_imprecise_GLIFT_logic_1(const RTLIL::Cell *cell, RTLIL::SigSpec &port_a, RTLIL::SigSpec &port_a_taint, RTLIL::SigSpec &port_b, RTLIL::SigSpec &port_b_taint, RTLIL::SigSpec &port_y_taint) {
 		//AKA AN2_SH3 or OR2_SH3
-		bool is_and = cell->type.in(ID($_AND_), ID($_NAND_));
+		bool is_and = cell->type.in(TW($_AND_), TW($_NAND_));
 		RTLIL::SigSpec n_port_a = module->LogicNot(Twine{cell->name.str() + "_t_2_1"}, port_a, false, cell->src_ref());
 		auto subexpr1 = module->And(Twine{cell->name.str() + "_t_2_2"}, is_and? port_b : n_port_a, is_and? port_a_taint : port_b_taint, false, cell->src_ref());
 		module->addOr(Twine{cell->name.str() + "_t_2_3"}, is_and? port_b_taint : port_a_taint, subexpr1, port_y_taint, false, cell->src_ref());
@@ -90,7 +90,7 @@ private:
 
 	void add_imprecise_GLIFT_logic_2(const RTLIL::Cell *cell, RTLIL::SigSpec &port_a, RTLIL::SigSpec &port_a_taint, RTLIL::SigSpec &port_b, RTLIL::SigSpec &port_b_taint, RTLIL::SigSpec &port_y_taint) {
 		//AKA AN2_SH4 or OR2_SH4
-		bool is_and = cell->type.in(ID($_AND_), ID($_NAND_));
+		bool is_and = cell->type.in(TW($_AND_), TW($_NAND_));
 		RTLIL::SigSpec n_port_b = module->LogicNot(Twine{cell->name.str() + "_t_3_1"}, port_b, false, cell->src_ref());
 		auto subexpr1 = module->And(Twine{cell->name.str() + "_t_3_2"}, is_and? port_a : n_port_b, is_and? port_b_taint : port_a_taint, false, cell->src_ref());
 		module->addOr(Twine{cell->name.str() + "_t_3_3"}, is_and? port_a_taint : port_b_taint, subexpr1, port_y_taint, false, cell->src_ref());
@@ -150,13 +150,13 @@ private:
 			auto select_width = metamux_select.as_wire()->width;
 
 			std::vector<RTLIL::Const> costs;
-			if (celltype == ID($_AND_) || celltype == ID($_OR_)) {
+			if (celltype == TW($_AND_) || celltype == TW($_OR_)) {
 				costs = {5, 2, 2, 1, 0, 0, 0, 0};
 				log_assert(select_width == 2 || select_width == 3);
 				log_assert(opt_instrumentmore || select_width == 2);
 				log_assert(!opt_instrumentmore || select_width == 3);
 			}
-			else if (celltype == ID($_XOR_) || celltype == ID($_XNOR_)) {
+			else if (celltype == TW($_XOR_) || celltype == TW($_XNOR_)) {
 				costs = {1, 0, 0, 0};
 				log_assert(select_width == 2);
 			}
@@ -184,10 +184,10 @@ private:
 		std::vector<RTLIL::SigSig> connections(module->connections());
 
 		for(auto &cell : module->cells().to_vector()) {
-			if (!cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_MUX_), ID($_NMUX_), ID($_NOT_), ID($anyconst), ID($allconst), ID($assume), ID($assert)) && module->design->module(cell->type) == nullptr) {
+			if (!cell->type.in(TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_), TW($_XOR_), TW($_XNOR_), TW($_MUX_), TW($_NMUX_), TW($_NOT_), TW($anyconst), TW($allconst), TW($assume), TW($assert)) && module->design->module(cell->type) == nullptr) {
 				log_cmd_error("Unsupported cell type \"%s\" found.  Run `techmap` first.\n", cell->type);
 			}
-			if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_))) {
+			if (cell->type.in(TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_))) {
 				const unsigned int A = 0, B = 1, Y = 2;
 				const unsigned int NUM_PORTS = 3;
 				RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::B), cell->getPort(TW::Y)};
@@ -234,7 +234,7 @@ private:
 					auto select_width = log2(num_versions);
 					log_assert(exp2(select_width) == num_versions);
 					RTLIL::SigSpec meta_mux_select(module->addWire(Twine{cell->name.str() + "_sel"}, select_width));
-					meta_mux_selects.push_back(make_pair(meta_mux_select, cell->type));
+					meta_mux_selects.push_back(make_pair(meta_mux_select, RTLIL::IdString(cell->type)));
 					module->connect(meta_mux_select, module->Anyconst(module->design->twines.add(Twine{cell->name.str() + "_hole"}), select_width, cell->src_ref()));
 
 					std::vector<RTLIL::SigSpec> next_meta_mux_y_ports, meta_mux_y_ports(taint_version);
@@ -252,7 +252,7 @@ private:
 				}
 				else log_cmd_error("This is a bug (1).\n");
 			}
-			else if (cell->type.in(ID($_XOR_), ID($_XNOR_))) {
+			else if (cell->type.in(TW($_XOR_), TW($_XNOR_))) {
 				const unsigned int A = 0, B = 1, Y = 2;
 				const unsigned int NUM_PORTS = 3;
 				RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::B), cell->getPort(TW::Y)};
@@ -289,7 +289,7 @@ private:
 					}
 
 					RTLIL::SigSpec meta_mux_select(module->addWire(Twine{cell->name.str() + "_sel"}, select_width));
-					meta_mux_selects.push_back(make_pair(meta_mux_select, cell->type));
+					meta_mux_selects.push_back(make_pair(meta_mux_select, RTLIL::IdString(cell->type)));
 					module->connect(meta_mux_select, module->Anyconst(module->design->twines.add(Twine{cell->name.str() + "_hole"}), select_width, cell->src_ref()));
 
 					std::vector<RTLIL::SigSpec> next_meta_mux_y_ports, meta_mux_y_ports(taint_version);
@@ -308,7 +308,7 @@ private:
 				else log_cmd_error("This is a bug (2).\n");
 
 			}
-			else if (cell->type.in(ID($_MUX_), ID($_NMUX_))) {
+			else if (cell->type.in(TW($_MUX_), TW($_NMUX_))) {
 				const unsigned int A = 0, B = 1, S = 2, Y = 3;
 				const unsigned int NUM_PORTS = 4;
 				RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::B), cell->getPort(TW::S), cell->getPort(TW::Y)};
@@ -321,7 +321,7 @@ private:
 
 				add_precise_GLIFT_mux(cell, ports[A], port_taints[A], ports[B], port_taints[B], ports[S], port_taints[S], port_taints[Y]);
 			}
-			else if (cell->type.in(ID($_NOT_))) {
+			else if (cell->type.in(TW($_NOT_))) {
 				const unsigned int A = 0, Y = 1;
 				const unsigned int NUM_PORTS = 2;
 				RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::Y)};
@@ -332,7 +332,7 @@ private:
 				for (unsigned int i = 0; i < NUM_PORTS; ++i)
 					port_taints[i] = get_corresponding_taint_signal(ports[i]);
 
-				if (cell->type == ID($_NOT_)) {
+				if (cell->type == TW($_NOT_)) {
 					module->connect(port_taints[Y], port_taints[A]);
 				}
 				else log_cmd_error("This is a bug (3).\n");

passes/cmds/icell_liberty.cc

@@ -63,7 +63,7 @@ struct LibertyStubber {
 		}
 
 		f << "\tcell (\"" << derived_name << "\") {\n";
-		auto& base_type = ct.cell_types[base_name];
+		auto& base_type = ct.cell_types[base->name];
 		i.indent = 3;
 		auto sorted_ports = derived->ports;
 		// Hack for CLK and C coming before Q does
@@ -117,17 +117,17 @@ struct LibertyStubber {
 	}
 	void liberty_cell(Module* base, Module* derived, std::ostream& f)
 	{
-		auto base_name = base->design->twines.str(base->meta_->name).substr(1);
+		auto base_name = base->name.substr(1);
 		auto derived_name = derived->design->twines.str(derived->meta_->name).substr(1);
-		if (!ct.cell_types.count(base_name)) {
+		if (!ct.cell_types.count(base->name)) {
 			log_debug("skip skeleton for %s\n", base_name.c_str());
 			return;
 		}
 
-		if (StaticCellTypes::categories.is_ff(base_name))
+		if (StaticCellTypes::categories.is_ff(base->name))
 			return liberty_flop(base, derived, f);
 
-		auto& base_type = ct.cell_types[base_name];
+		auto& base_type = ct.cell_types[base->name];
 		f << "\tcell (\"" << derived_name << "\") {\n";
 		for (auto x : derived->ports) {
 			std::string port_name = derived->design->twines.str(x);

passes/cmds/linecoverage.cc

@@ -95,7 +95,7 @@ struct CoveragePass : public Pass {
 		{
 			log_debug("Module %s:\n", module);
 			for (auto wire: module->wires()) {
-				log_debug("%s\t%s\t%s\n", module->selected(wire) ? "*" : " ", wire->get_src_attribute(), wire->name.unescape());
+				log_debug("%s\t%s\t%s\n", module->selected(wire) ? "*" : " ", wire->get_src_attribute(), design->twines.unescaped_str(wire->name));
 				for (auto src: design->src_leaves(wire)) {
 					auto filename = extract_src_filename(src);
 					if (filename.empty()) continue;

passes/cmds/ltp.cc

@@ -64,7 +64,7 @@ struct LtpWorker
 						dst_bits.insert(bit);
 				}
 
-			if (noff && ff_celltypes.cell_known(cell->type)) {
+			if (noff && ff_celltypes.cell_known(cell->type_impl)) {
 				for (auto s : src_bits)
 					for (auto d : dst_bits) {
 						bit2ff[s] = tuple<SigBit, Cell*>(d, cell);

passes/cmds/portarcs.cc

@@ -31,7 +31,7 @@ static RTLIL::SigBit canonical_bit(RTLIL::SigBit bit)
 {
 	RTLIL::Wire *w;
 	while ((w = bit.wire) != NULL && !w->port_input &&
-			w->driverCell()->type.in(ID($buf), ID($_BUF_))) {
+			w->driverCell()->type.in(TW($buf), TW($_BUF_))) {
 		bit = w->driverCell()->getPort(TW::A)[bit.offset];
 	}
 	return bit;
@@ -125,10 +125,10 @@ struct PortarcsPass : Pass {
 
 				for (auto cell : m->cells())
 				// Ignore all bufnorm helper cells
-				if (!cell->type.in(ID($buf), ID($input_port), ID($output_port), ID($public), ID($connect), ID($tribuf))) {
+				if (!cell->type.in(TW($buf), TW($input_port), TW($output_port), TW($public), TW($connect), TW($tribuf))) {
 					auto tdata = tinfo.find(cell->type);
 					if (tdata == tinfo.end())
-						log_cmd_error("Missing timing data for module '%s'.\n", cell->type.unescape());
+						log_cmd_error("Missing timing data for module '%s'.\n", cell->type.unescaped());
 					for (auto [edge, delay] : tdata->second.comb) {
 						auto from = edge.first.get_connection(cell);
 						auto to = edge.second.get_connection(cell);
@@ -292,7 +292,7 @@ struct PortarcsPass : Pass {
 					int *p = annotations.at(canonical_bit(bit));
 					for (auto i = 0; i < inputs.size(); i++) {
 						if (p[i] >= 0) {
-							Cell *spec = m->addCell(NEW_TWINE, ID($specify2));
+							Cell *spec = m->addCell(NEW_TWINE, TW($specify2));
 							spec->setParam(ID::SRC_WIDTH, 1);
 							spec->setParam(ID::DST_WIDTH, 1);
 							spec->setParam(ID::T_FALL_MAX, p[i]);

passes/cmds/printattrs.cc

@@ -47,9 +47,9 @@ struct PrintAttrsPass : public Pass {
 
 	static void log_const(RTLIL::IdString s, const RTLIL::Const &x, const unsigned int indent) {
 		if (x.flags & RTLIL::CONST_FLAG_STRING)
-			log("%s(* %s=\"%s\" *)\n", get_indent_str(indent), s.unescape(), x.decode_string());
+			log("%s(* %s=\"%s\" *)\n", get_indent_str(indent), design->twines.unescaped_str(s), x.decode_string());
 		else if (x.flags == RTLIL::CONST_FLAG_NONE || x.flags == RTLIL::CONST_FLAG_SIGNED)
-			log("%s(* %s=%s *)\n", get_indent_str(indent), s.unescape(), x.as_string());
+			log("%s(* %s=%s *)\n", get_indent_str(indent), design->twines.unescaped_str(s), x.as_string());
 		else
 			log_assert(x.flags & RTLIL::CONST_FLAG_STRING || x.flags == RTLIL::CONST_FLAG_NONE); //intended to fail
 	}
@@ -88,7 +88,7 @@ struct PrintAttrsPass : public Pass {
 			}
 
 			for (auto wire : mod->selected_wires()) {
-				log("%s%s\n", get_indent_str(indent), wire->name.unescape());
+				log("%s%s\n", get_indent_str(indent), design->twines.unescaped_str(wire->name));
 				indent += 2;
 				log_src(design, wire, indent);
 				for (auto &it : wire->attributes)

passes/cmds/rename.cc

@@ -21,6 +21,7 @@
 #include "kernel/rtlil.h"
 #include "kernel/log.h"
 #include "backends/verilog/verilog_backend.h"
+#include "kernel/twine.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
@@ -149,11 +150,11 @@ static bool rename_witness(RTLIL::Design *design, dict<RTLIL::Module *, int> &ca
 			}
 		}
 
-		if (cell->type.in(ID($anyconst), ID($anyseq), ID($anyinit), ID($allconst), ID($allseq))) {
+		if (cell->type.in(TW($anyconst), TW($anyseq), TW($anyinit), TW($allconst), TW($allseq))) {
 			has_witness_signals = true;
 			IdString QY;
 			bool clk2fflogic = false;
-			if (cell->type == ID($anyinit))
+			if (cell->type == TW($anyinit))
 				QY = (clk2fflogic = cell->get_bool_attribute(ID(clk2fflogic))) ? ID::D : ID::Q;
 			else
 				QY = ID::Y;
@@ -179,7 +180,7 @@ static bool rename_witness(RTLIL::Design *design, dict<RTLIL::Module *, int> &ca
 		}
 
 
-		if (cell->type.in(ID($assert), ID($assume), ID($cover), ID($live), ID($fair), ID($check))) {
+		if (cell->type.in(TW($assert), TW($assume), TW($cover), TW($live), TW($fair), TW($check))) {
 			has_witness_signals = true;
 			if (cell->name.isPublic())
 				continue;
@@ -386,6 +387,7 @@ struct RenamePass : public Pass {
 		// TODO disable signorm due to rename I think?
 		design->sigNormalize(false);
 
+		TwineSearch search(&design->twines);
 		if (flag_src)
 		{
 			extra_args(args, argidx, design);
@@ -527,14 +529,14 @@ struct RenamePass : public Pass {
 			if (argidx+1 != args.size())
 				log_cmd_error("Invalid number of arguments!\n");
 
-			IdString new_name = RTLIL::escape_id(args[argidx]);
+			TwineRef new_name = design->twines.add(Twine{RTLIL::escape_id(args[argidx])});
 			RTLIL::Module *module = design->top_module();
 
 			if (module == nullptr)
 				log_cmd_error("No top module found!\n");
 
-			log("Renaming module %s to %s.\n", log_id(module), new_name.unescape());
-			design->rename(module, design->twines.add(Twine{new_name.str()}));
+			log("Renaming module %s to %s.\n", log_id(module), design->twines.unescaped_str(new_name));
+			design->rename(module, new_name);
 		}
 		else
 		if (flag_scramble_name)

passes/cmds/scatter.cc

@@ -53,7 +53,7 @@ struct ScatterPass : public Pass {
 				for (auto conn : cell->connections())
 					new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEW_TWINE, GetSize(conn.second))));
 				for (auto &it : new_connections) {
-					if (ct.cell_output(cell->type, it.first))
+					if (ct.cell_output(cell->type.ref(), it.first))
 						module->connect(RTLIL::SigSig(it.second.first, it.second.second));
 					else
 						module->connect(RTLIL::SigSig(it.second.second, it.second.first));

passes/cmds/scc.cc

@@ -117,7 +117,7 @@ struct SccWorker
 			for (auto mod : design->modules())
 				if (mod->get_blackbox_attribute(false))
 					for (auto cell : mod->cells())
-						if (cell->type == ID($specify2))
+						if (cell->type == TW($specify2))
 						{
 							specifyCells.setup_module(mod);
 							break;
@@ -138,18 +138,18 @@ struct SccWorker
 			if (!design->selected(module, cell))
 				continue;
 
-			if (!allCellTypes && !ct.cell_known(cell->type) && !specifyCells.cell_known(cell->type))
+			if (!allCellTypes && !ct.cell_known(cell->type.ref()) && !specifyCells.cell_known(cell->type.ref()))
 				continue;
 
 			workQueue.insert(cell);
 
 			RTLIL::SigSpec inputSignals, outputSignals;
 
-			if (specifyCells.cell_known(cell->type)) {
+			if (specifyCells.cell_known(cell->type.ref())) {
 				// Use specify rules of the type `(X => Y) = NN` to look for asynchronous paths in boxes.
 				for (auto subcell : design->module(cell->type)->cells())
 				{
-					if (subcell->type != ID($specify2))
+					if (subcell->type != TW($specify2))
 						continue;
 
 					for (auto bit : subcell->getPort(TW::SRC))
@@ -171,9 +171,9 @@ struct SccWorker
 				{
 					bool isInput = true, isOutput = true;
 
-					if (ct.cell_known(cell->type)) {
-						isInput = ct.cell_input(cell->type, conn.first);
-						isOutput = ct.cell_output(cell->type, conn.first);
+					if (ct.cell_known(cell->type.ref())) {
+						isInput = ct.cell_input(cell->type.ref(), conn.first);
+						isOutput = ct.cell_output(cell->type.ref(), conn.first);
 					}
 
 					RTLIL::SigSpec sig = selectedSignals.extract(sigmap(conn.second));

passes/cmds/sdc/sdc.cc

@@ -1,3 +1,4 @@
+#include "kernel/twine.h"
 #ifdef YOSYS_ENABLE_TCL
 
 #include "kernel/register.h"
@@ -97,7 +98,7 @@ struct SdcObjects {
 		// constraint-side tracking
 		FullConstraint,
 	} collect_mode;
-	using CellPin = std::pair<Cell*, IdString>;
+	using CellPin = std::pair<Cell*, TwineRef>;
 	Design* design;
 	std::vector<std::pair<std::string, Wire*>> design_ports;
 	std::vector<std::pair<std::string, Cell*>> design_cells;
@@ -149,8 +150,8 @@ struct SdcObjects {
 			path += name;
 			design_cells.push_back(std::make_pair(path, cell));
 			for (auto pin : cell->connections()) {
-				IdString pin_name = pin.first;
-				std::string pin_name_sdc = path + "/" + pin.first.str().substr(1);
+				TwineRef pin_name = pin.first;
+				std::string pin_name_sdc = path + "/" + design->twines.unescaped_str(pin.first);
 				design_pins.push_back(std::make_pair(pin_name_sdc, std::make_pair(cell, pin_name)));
 			}
 			if (auto sub_mod = mod->design->module(cell->type)) {
@@ -168,9 +169,9 @@ struct SdcObjects {
 			RTLIL::Wire *wire = top->wire(port);
 			if (!wire) {
 				// This should not be possible. See https://github.com/YosysHQ/yosys/pull/5594#issue-3791198573
-				log_error("Port %s doesn't exist", port.unescape());
+				log_error("Port %s doesn't exist", design->twines.unescaped_str(port));
 			}
-			design_ports.push_back(std::make_pair(port.str().substr(1), wire));
+			design_ports.push_back(std::make_pair(design->twines.unescaped_str(port), wire));
 		}
 		std::list<std::string> hierarchy{};
 		sniff_module(hierarchy, top);

passes/cmds/select.cc

@@ -17,6 +17,8 @@
  *
  */
 
+#include "kernel/rtlil.h"
+#include "kernel/twine.h"
 #include "kernel/yosys.h"
 #include "kernel/newcelltypes.h"
 #include "kernel/sigtools.h"
@@ -450,7 +452,7 @@ static void select_op_intersect(RTLIL::Design *design, RTLIL::Selection &lhs, co
 
 	select_all(design, lhs);
 
-	std::vector<RTLIL::IdString> del_list;
+	std::vector<TwineRef> del_list;
 
 	for (auto mod_name : lhs.selected_modules) {
 		if (rhs.selected_whole_module(mod_name))
@@ -471,7 +473,7 @@ static void select_op_intersect(RTLIL::Design *design, RTLIL::Selection &lhs, co
 			del_list.push_back(it.first);
 			continue;
 		}
-		std::vector<RTLIL::IdString> del_list2;
+		std::vector<TwineRef> del_list2;
 		for (auto &it2 : it.second)
 			if (!rhs.selected_member(it.first, it2))
 				del_list2.push_back(it2);
@@ -487,11 +489,11 @@ static void select_op_intersect(RTLIL::Design *design, RTLIL::Selection &lhs, co
 namespace {
 	struct expand_rule_t {
 		char mode;
-		std::set<RTLIL::IdString> cell_types, port_names;
+		std::set<std::string> cell_types, port_names;
 	};
 }
 
-static int parse_comma_list(std::set<RTLIL::IdString> &tokens, const std::string &str, size_t pos, std::string stopchar)
+static int parse_comma_list(std::set<std::string> &tokens, const std::string &str, size_t pos, std::string stopchar)
 {
 	stopchar += ',';
 	while (1) {
@@ -520,7 +522,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
 		auto selected_members = lhs.selected_members[mod->meta_->name];
 
 		for (auto wire : mod->wires())
-			if (lhs.selected_member(mod->meta_->name, wire->meta_->name) && limits.count(wire->meta_->name) == 0)
+			if (lhs.selected_member(mod->meta_->name, wire->meta_->name) && limits.count(RTLIL::IdString(design->twines.str(wire->meta_->name))) == 0)
 				selected_wires.insert(wire);
 
 		for (auto &conn : mod->connections())
@@ -538,17 +540,18 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
 			}
 		}
 
+		auto twines = design->twines;
 		for (auto cell : mod->cells())
 		for (auto &conn : cell->connections())
 		{
 			char last_mode = '-';
-			if (eval_only && !yosys_celltypes.cell_evaluable(cell->type))
+			if (eval_only && !yosys_celltypes.cell_evaluable(cell->type.ref()))
 				goto exclude_match;
 			for (auto &rule : rules) {
 				last_mode = rule.mode;
-				if (rule.cell_types.size() > 0 && rule.cell_types.count(cell->type) == 0)
+				if (rule.cell_types.size() > 0 && rule.cell_types.count(twines.unescaped_str(cell->type_impl)) == 0)
 					continue;
-				if (rule.port_names.size() > 0 && rule.port_names.count(conn.first) == 0)
+				if (rule.port_names.size() > 0 && rule.port_names.count(twines.unescaped_str(conn.first)) == 0)
 					continue;
 				if (rule.mode == '+')
 					goto include_match;
@@ -558,16 +561,16 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
 			if (last_mode == '+')
 				goto exclude_match;
 		include_match:
-			is_input = mode == 'x' || ct.cell_input(cell->type, conn.first);
-			is_output = mode == 'x' || ct.cell_output(cell->type, conn.first);
+			is_input = mode == 'x' || ct.cell_input(cell->type.ref(), conn.first);
+			is_output = mode == 'x' || ct.cell_output(cell->type.ref(), conn.first);
 			for (auto &chunk : conn.second.chunks())
 				if (chunk.wire != nullptr) {
-					if (max_objects != 0 && selected_wires.count(chunk.wire) > 0 && selected_members.count(cell->name) == 0)
+					if (max_objects != 0 && selected_wires.count(chunk.wire) > 0 && selected_members.count(cell->name.ref()) == 0)
 						if (mode == 'x' || (mode == 'i' && is_output) || (mode == 'o' && is_input))
-							lhs.selected_members[mod->name].insert(cell->name), sel_objects++, max_objects--;
-					if (max_objects != 0 && selected_members.count(cell->name) > 0 && limits.count(cell->name) == 0 && selected_members.count(chunk.wire->name) == 0)
+							lhs.selected_members[mod->meta_->name].insert(cell->name.ref()), sel_objects++, max_objects--;
+					if (max_objects != 0 && selected_members.count(cell->name.ref()) > 0 && limits.count(cell->name) == 0 && selected_members.count(chunk.wire->name.ref()) == 0)
 						if (mode == 'x' || (mode == 'i' && is_input) || (mode == 'o' && is_output))
-							lhs.selected_members[mod->name].insert(chunk.wire->name), sel_objects++, max_objects--;
+							lhs.selected_members[mod->meta_->name].insert(chunk.wire->name.ref()), sel_objects++, max_objects--;
 				}
 		exclude_match:;
 		}
@@ -634,7 +637,7 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char
 					if (design->selection_vars.count(str) > 0) {
 						for (auto i1 : design->selection_vars.at(str).selected_members)
 						for (auto i2 : i1.second)
-							limits.insert(i2);
+							limits.insert(RTLIL::IdString(design->twines.str(i2)));
 					} else
 						log_cmd_error("Selection %s is not defined!\n", RTLIL::unescape_id(str));
 				} else
@@ -682,7 +685,7 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char
 
 static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &sel)
 {
-	if (design->selected_active_module.empty())
+	if (!design->selected_active_module)
 		return;
 
 	if (sel.full_selection) {
@@ -691,7 +694,7 @@ static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &se
 		return;
 	}
 
-	std::vector<RTLIL::IdString> del_list;
+	std::vector<TwineRef> del_list;
 	for (auto mod_name : sel.selected_modules)
 		if (mod_name != design->selected_active_module)
 			del_list.push_back(mod_name);
@@ -845,8 +848,8 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
 		select_blackboxes = true;
 	}
 
-	if (!design->selected_active_module.empty()) {
-		arg_mod = design->selected_active_module;
+	if (design->selected_active_module) {
+		arg_mod = design->twines.str(design->selected_active_module);
 		arg_memb = arg;
 		if (!isprefixed(arg_memb))
 			arg_memb_found[arg_memb] = false;
@@ -898,29 +901,29 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
 			arg_mod_found[arg_mod] = true;
 
 		if (arg_memb == "") {
-			sel.selected_modules.insert(mod->name);
+			sel.selected_modules.insert(mod->meta_->name);
 			continue;
 		}
 
 		if (arg_memb.compare(0, 2, "w:") == 0) {
 			for (auto wire : mod->wires())
 				if (match_ids(wire->name, arg_memb.substr(2)))
-					sel.selected_members[mod->name].insert(wire->name);
+					sel.selected_members[mod->meta_->name].insert(wire->name.ref());
 		} else
 		if (arg_memb.compare(0, 2, "i:") == 0) {
 			for (auto wire : mod->wires())
 				if (wire->port_input && match_ids(wire->name, arg_memb.substr(2)))
-					sel.selected_members[mod->name].insert(wire->name);
+					sel.selected_members[mod->meta_->name].insert(wire->name.ref());
 		} else
 		if (arg_memb.compare(0, 2, "o:") == 0) {
 			for (auto wire : mod->wires())
 				if (wire->port_output && match_ids(wire->name, arg_memb.substr(2)))
-					sel.selected_members[mod->name].insert(wire->name);
+					sel.selected_members[mod->meta_->name].insert(wire->name.ref());
 		} else
 		if (arg_memb.compare(0, 2, "x:") == 0) {
 			for (auto wire : mod->wires())
 				if ((wire->port_input || wire->port_output) && match_ids(wire->name, arg_memb.substr(2)))
-					sel.selected_members[mod->name].insert(wire->name);
+					sel.selected_members[mod->meta_->name].insert(wire->name.ref());
 		} else
 		if (arg_memb.compare(0, 2, "s:") == 0) {
 			size_t delim = arg_memb.substr(2).find(':');
@@ -928,7 +931,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
 				int width = atoi(arg_memb.substr(2).c_str());
 				for (auto wire : mod->wires())
 					if (wire->width == width)
-						sel.selected_members[mod->name].insert(wire->name);
+						sel.selected_members[mod->meta_->name].insert(wire->name.ref());
 			} else {
 				std::string min_str = arg_memb.substr(2, delim);
 				std::string max_str = arg_memb.substr(2+delim+1);
@@ -936,18 +939,18 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
 				int max_width = max_str.empty() ? -1 : atoi(max_str.c_str());
 				for (auto wire : mod->wires())
 					if (min_width <= wire->width && (wire->width <= max_width || max_width == -1))
-						sel.selected_members[mod->name].insert(wire->name);
+						sel.selected_members[mod->meta_->name].insert(wire->name.ref());
 			}
 		} else
 		if (arg_memb.compare(0, 2, "m:") == 0) {
 			for (auto &it : mod->memories)
-				if (match_ids(it.first, arg_memb.substr(2)))
-					sel.selected_members[mod->name].insert(it.first);
+				if (match_ids(RTLIL::IdString(design->twines.str(it.first)), arg_memb.substr(2)))
+					sel.selected_members[mod->meta_->name].insert(it.first);
 		} else
 		if (arg_memb.compare(0, 2, "c:") == 0) {
 			for (auto cell : mod->cells())
 				if (match_ids(cell->name, arg_memb.substr(2)))
-					sel.selected_members[mod->name].insert(cell->name);
+					sel.selected_members[mod->meta_->name].insert(cell->name.ref());
 		} else
 		if (arg_memb.compare(0, 2, "t:") == 0) {
 			if (arg_memb.compare(2, 1, "@") == 0) {
@@ -957,59 +960,59 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
 
 				auto &muster = design->selection_vars[set_name];
 				for (auto cell : mod->cells())
-					if (muster.selected_modules.count(cell->type))
-						sel.selected_members[mod->name].insert(cell->name);
+					if (muster.selected_modules.count(cell->type.ref()))
+						sel.selected_members[mod->meta_->name].insert(cell->name.ref());
 			} else {
 				for (auto cell : mod->cells())
 					if (match_ids(cell->type, arg_memb.substr(2)))
-						sel.selected_members[mod->name].insert(cell->name);
+						sel.selected_members[mod->meta_->name].insert(cell->name.ref());
 			}
 		} else
 		if (arg_memb.compare(0, 2, "p:") == 0) {
 			for (auto &it : mod->processes)
-				if (match_ids(it.first, arg_memb.substr(2)))
-					sel.selected_members[mod->name].insert(it.first);
+				if (match_ids(RTLIL::IdString(design->twines.str(it.first)), arg_memb.substr(2)))
+					sel.selected_members[mod->meta_->name].insert(it.first);
 		} else
 		if (arg_memb.compare(0, 2, "a:") == 0) {
 			for (auto wire : mod->wires())
 				if (match_attr(design, wire, arg_memb.substr(2)))
-					sel.selected_members[mod->name].insert(wire->name);
+					sel.selected_members[mod->meta_->name].insert(wire->name.ref());
 			for (auto &it : mod->memories)
 				if (match_attr(design, it.second, arg_memb.substr(2)))
-					sel.selected_members[mod->name].insert(it.first);
+					sel.selected_members[mod->meta_->name].insert(it.first);
 			for (auto cell : mod->cells())
 				if (match_attr(design, cell, arg_memb.substr(2)))
-					sel.selected_members[mod->name].insert(cell->name);
+					sel.selected_members[mod->meta_->name].insert(cell->name.ref());
 			for (auto &it : mod->processes)
 				if (match_attr(design, it.second, arg_memb.substr(2)))
-					sel.selected_members[mod->name].insert(it.first);
+					sel.selected_members[mod->meta_->name].insert(it.first);
 		} else
 		if (arg_memb.compare(0, 2, "r:") == 0) {
 			for (auto cell : mod->cells())
 				if (match_attr(cell->parameters, arg_memb.substr(2)))
-					sel.selected_members[mod->name].insert(cell->name);
+					sel.selected_members[mod->meta_->name].insert(cell->name.ref());
 		} else {
 			std::string orig_arg_memb = arg_memb;
 			if (arg_memb.compare(0, 2, "n:") == 0)
 				arg_memb = arg_memb.substr(2);
 			for (auto wire : mod->wires())
 				if (match_ids(wire->name, arg_memb)) {
-					sel.selected_members[mod->name].insert(wire->name);
+					sel.selected_members[mod->meta_->name].insert(wire->name.ref());
 					arg_memb_found[orig_arg_memb] = true;
 				}
 			for (auto &it : mod->memories)
-				if (match_ids(it.first, arg_memb)) {
-					sel.selected_members[mod->name].insert(it.first);
+				if (match_ids(RTLIL::IdString(design->twines.str(it.first)), arg_memb)) {
+					sel.selected_members[mod->meta_->name].insert(it.first);
 					arg_memb_found[orig_arg_memb] = true;
 				}
 			for (auto cell : mod->cells())
 				if (match_ids(cell->name, arg_memb)) {
-					sel.selected_members[mod->name].insert(cell->name);
+					sel.selected_members[mod->meta_->name].insert(cell->name.ref());
 					arg_memb_found[orig_arg_memb] = true;
 				}
 			for (auto &it : mod->processes)
-				if (match_ids(it.first, arg_memb)) {
-					sel.selected_members[mod->name].insert(it.first);
+				if (match_ids(RTLIL::IdString(design->twines.str(it.first)), arg_memb)) {
+					sel.selected_members[mod->meta_->name].insert(it.first);
 					arg_memb_found[orig_arg_memb] = true;
 				}
 		}
@@ -1365,6 +1368,7 @@ struct SelectPass : public Pass {
 
 		work_stack.clear();
 
+		TwineSearch search(&design->twines);
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
@@ -1431,10 +1435,11 @@ struct SelectPass : public Pass {
 				continue;
 			}
 			if (arg == "-module" && argidx+1 < args.size()) {
-				RTLIL::IdString mod_name = RTLIL::escape_id(args[++argidx]);
-				if (design->module(mod_name) == nullptr)
-					log_cmd_error("No such module: %s\n", mod_name.unescape());
-				design->selected_active_module = mod_name.str();
+				std::string mod_name = RTLIL::escape_id(args[++argidx]);
+				TwineRef t = search.find(mod_name);
+				if (t == Twine::Null || design->module(t) == nullptr)
+					log_cmd_error("No such module: %s\n", RTLIL::unescape_id(mod_name));
+				design->selected_active_module = t;
 				got_module = true;
 				continue;
 			}
@@ -1475,7 +1480,7 @@ struct SelectPass : public Pass {
 				}
 				IdString mod_name = RTLIL::escape_id(line.substr(0, slash_pos));
 				IdString obj_name = RTLIL::escape_id(line.substr(slash_pos+1));
-				sel.selected_members[mod_name].insert(obj_name);
+				sel.selected_members[design->twines.add(Twine{mod_name.str()})].insert(design->twines.add(Twine{obj_name.str()}));
 			}
 
 			select_filter_active_mod(design, sel);
@@ -1493,7 +1498,7 @@ struct SelectPass : public Pass {
 		const char *common_flagset = "-add, -del, -assert-none, -assert-any, -assert-mod-count, -assert-count, -assert-max, or -assert-min";
 
 		if (common_flagset_tally > 1)
-			log_cmd_error("Options %s can not be combined.\n", common_flagset);                
+			log_cmd_error("Options %s can not be combined.\n", common_flagset);
 
 		if ((list_mode || !write_file.empty() || count_mode) && common_flagset_tally)
 			log_cmd_error("Options -list, -list-mod, -write and -count can not be combined with %s.\n", common_flagset);
@@ -1519,7 +1524,7 @@ struct SelectPass : public Pass {
 
 		if (clear_mode) {
 			design->selection() = RTLIL::Selection::FullSelection(design);
-			design->selected_active_module = std::string();
+			design->selected_active_module = TwineRef{};
 			return;
 		}
 
@@ -1545,11 +1550,11 @@ struct SelectPass : public Pass {
 			sel->optimize(design);
 			for (auto mod : design->all_selected_modules())
 			{
-				if (sel->selected_whole_module(mod->name) && list_mode)
+				if (sel->selected_whole_module(mod->meta_->name) && list_mode)
 					log("%s\n", mod);
 				if (!list_mod_mode)
 					for (auto it : mod->selected_members())
-						LOG_OBJECT("%s/%s\n", mod->name.unescape().c_str(), it->name.unescape().c_str())
+						LOG_OBJECT("%s/%s\n", design->twines.unescaped_str(mod->name).c_str(), mod->design->twines.unescaped_str(it->meta_->name).c_str())
 			}
 			if (count_mode)
 			{
@@ -1673,10 +1678,10 @@ struct SelectPass : public Pass {
 			if (sel.full_selection)
 				log("*\n");
 			for (auto &it : sel.selected_modules)
-				log("%s\n", it.unescape());
+				log("%s\n", design->twines.unescaped_str(it).c_str());
 			for (auto &it : sel.selected_members)
 				for (auto &it2 : it.second)
-					log("%s/%s\n", it.first.unescape(), it2.unescape());
+					log("%s/%s\n", design->twines.unescaped_str(it.first).c_str(), design->twines.unescaped_str(it2).c_str());
 			return;
 		}
 
@@ -1728,17 +1733,17 @@ struct CdPass : public Pass {
 		if (args.size() == 1 || args[1] == "/") {
 			design->pop_selection();
 			design->push_full_selection();
-			design->selected_active_module = std::string();
+			design->selected_active_module = TwineRef{};
 			return;
 		}
 
 		if (args[1] == "..")
 		{
-			string modname = design->selected_active_module;
+			string modname = design->twines.str(design->selected_active_module);
 
 			design->pop_selection();
 			design->push_full_selection();
-			design->selected_active_module = std::string();
+			design->selected_active_module = TwineRef{};
 
 			while (1)
 			{
@@ -1748,12 +1753,12 @@ struct CdPass : public Pass {
 					break;
 
 				modname = modname.substr(0, pos);
-				Module *mod = design->module(modname);
+				Module *mod = design->module(RTLIL::IdString(modname));
 
 				if (mod == nullptr)
 					continue;
 
-				design->selected_active_module = modname;
+				design->selected_active_module = design->twines.add(Twine{modname});
 				design->pop_selection();
 				design->push_full_selection();
 				select_filter_active_mod(design, design->selection());
@@ -1766,14 +1771,15 @@ struct CdPass : public Pass {
 
 		std::string modname = RTLIL::escape_id(args[1]);
 
-		if (design->module(modname) == nullptr && !design->selected_active_module.empty()) {
+		if (design->module(RTLIL::IdString(modname)) == nullptr && design->selected_active_module) {
 			RTLIL::Module *module = design->module(design->selected_active_module);
-			if (module != nullptr && module->cell(modname) != nullptr)
-				modname = module->cell(modname)->type.str();
+			TwineRef cell_ref = design->twines.lookup(modname);
+			if (module != nullptr && cell_ref && module->cell(cell_ref) != nullptr)
+				modname = design->twines.str(module->cell(cell_ref)->type.ref());
 		}
 
-		if (design->module(modname) != nullptr) {
-			design->selected_active_module = modname;
+		if (design->module(RTLIL::IdString(modname)) != nullptr) {
+			design->selected_active_module = design->twines.add(Twine{modname});
 			design->pop_selection();
 			design->push_full_selection();
 			select_filter_active_mod(design, design->selection());
@@ -1788,17 +1794,20 @@ struct CdPass : public Pass {
 template<typename T>
 static void log_matches(const char *title, Module *module, const T &list)
 {
-	std::vector<IdString> matches;
+	std::vector<TwineRef> matches;
 
 	for (auto &it : list)
 		if (module->selected(it.second))
-			matches.push_back(RTLIL::IdString(it.second->name));
+			matches.push_back(it.first);
 
 	if (!matches.empty()) {
 		log("\n%d %s:\n", int(matches.size()), title);
-		std::sort(matches.begin(), matches.end(), RTLIL::sort_by_id_str());
-		for (auto id : matches)
-			log("  %s\n", id.unescape());
+		auto &twines = module->design->twines;
+		std::sort(matches.begin(), matches.end(), [&](TwineRef a, TwineRef b) {
+			return twines.str(a) < twines.str(b);
+		});
+		for (auto ref : matches)
+			log("  %s\n", twines.unescaped_str(ref).c_str());
 	}
 }
 
@@ -1825,7 +1834,7 @@ struct LsPass : public Pass {
 		size_t argidx = 1;
 		extra_args(args, argidx, design);
 
-		if (design->selected_active_module.empty())
+		if (!design->selected_active_module)
 		{
 			std::vector<IdString> matches;
 
@@ -1836,7 +1845,7 @@ struct LsPass : public Pass {
 				log("\n%d %s:\n", int(matches.size()), "modules");
 				std::sort(matches.begin(), matches.end(), RTLIL::sort_by_id_str());
 				for (auto id : matches)
-					log("  %s%s\n", id.unescape(), design->selected_whole_module(design->module(id)) ? "" : "*");
+					log("  %s%s\n", design->twines.unescaped_str(id), design->selected_whole_module(design->module(id)) ? "" : "*");
 			}
 		}
 		else

passes/cmds/setundef.cc

@@ -39,7 +39,7 @@ static RTLIL::Wire * add_wire(RTLIL::Module *module, std::string name, int width
 	RTLIL::Wire *wire = NULL;
 	TwineRef t = module->design->twines.add(Twine{name});
 
-	if (module->count_id(name) != 0)
+	if (module->count_id(t) != 0)
 	{
 		log("Module %s already has such an object %s.\n", module->name, name);
 		name += "$";
@@ -47,7 +47,7 @@ static RTLIL::Wire * add_wire(RTLIL::Module *module, std::string name, int width
 	}
 	else
 	{
-		wire = module->addWire(name, width);
+		wire = module->addWire(t, width);
 		wire->port_input = flag_input;
 		wire->port_output = flag_output;
 
@@ -305,7 +305,7 @@ struct SetundefPass : public Pass {
 					CellTypes ct(design);
 					for (auto &it : module->cells_)
 					for (auto &conn : it.second->connections())
-						if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
+						if (!ct.cell_known(it.second->type.ref()) || ct.cell_output(it.second->type.ref(), conn.first))
 							undriven_signals.del(sigmap(conn.second));
 
 					RTLIL::SigSpec sig = undriven_signals.export_all();
@@ -340,7 +340,7 @@ struct SetundefPass : public Pass {
 					CellTypes ct(design);
 					for (auto &it : module->cells_)
 					for (auto &conn : it.second->connections())
-						if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
+						if (!ct.cell_known(it.second->type.ref()) || ct.cell_output(it.second->type.ref(), conn.first))
 							undriven_signals.del(sigmap(conn.second));
 
 					RTLIL::SigSpec sig = undriven_signals.export_all();

passes/cmds/show.cc

@@ -148,14 +148,15 @@ struct ShowWorker
 
 	std::string findColor(IdString member_name)
 	{
+		TwineRef member_ref = design->twines.lookup(member_name.str());
 		for (auto &s : color_selections)
-			if (s.second.selected_member(module->name, member_name)) {
+			if (member_ref && s.second.selected_member(module->meta_->name, member_ref)) {
 				return stringf("color=\"%s\", fontcolor=\"%s\"", s.first, s.first);
 			}
 
 		RTLIL::Const colorattr_value;
-		RTLIL::Cell *cell = module->cell(member_name);
-		RTLIL::Wire *wire = module->wire(member_name);
+		RTLIL::Cell *cell = member_ref ? module->cell(member_ref) : nullptr;
+		RTLIL::Wire *wire = member_ref ? module->wire(member_ref) : nullptr;
 
 		if (cell && cell->attributes.count(colorattr))
 			colorattr_value = cell->attributes.at(colorattr);
@@ -174,8 +175,9 @@ struct ShowWorker
 
 	const char *findLabel(std::string member_name)
 	{
+		TwineRef member_ref = design->twines.lookup(member_name);
 		for (auto &s : label_selections)
-			if (s.second.selected_member(module->name, member_name))
+			if (member_ref && s.second.selected_member(module->meta_->name, member_ref))
 				return escape(s.first);
 		return escape(member_name, true);
 	}
@@ -240,7 +242,7 @@ struct ShowWorker
 
 		if (sig.is_chunk()) {
 			const RTLIL::SigChunk &c = sig.as_chunk();
-			if (c.wire != nullptr && design->selected_member(module->name, c.wire->name)) {
+			if (c.wire != nullptr && design->selected_member(module->meta_->name, c.wire->name.ref())) {
 				if (!range_check || c.wire->width == c.width)
 						return stringf("n%d", id2num(c.wire->name));
 			} else {
@@ -472,10 +474,10 @@ struct ShowWorker
 			std::vector<std::string> in_label_pieces, out_label_pieces;
 
 			for (auto &conn : cell->connections()) {
-				if (!ct.cell_output(cell->type, conn.first))
-					in_ports.push_back(conn.first);
+				if (!ct.cell_output(cell->type.ref(), conn.first))
+					in_ports.push_back(RTLIL::IdString(design->twines.str(conn.first)));
 				else
-					out_ports.push_back(conn.first);
+					out_ports.push_back(RTLIL::IdString(design->twines.str(conn.first)));
 			}
 
 			std::sort(in_ports.begin(), in_ports.end(), RTLIL::sort_by_id_str());
@@ -501,8 +503,8 @@ struct ShowWorker
 
 			std::string code;
 			for (auto &conn : cell->connections()) {
-				code += gen_portbox(stringf("c%d:p%d", id2num(cell->name), id2num(conn.first)),
-						conn.second, ct.cell_output(cell->type, conn.first));
+				code += gen_portbox(stringf("c%d:p%d", id2num(cell->name), id2num(RTLIL::IdString(design->twines.str(conn.first)))),
+						conn.second, ct.cell_output(cell->type.ref(), conn.first));
 			}
 
 			std::string src_href;
@@ -523,7 +525,7 @@ struct ShowWorker
 		{
 			RTLIL::Process *proc = it.second;
 
-			if (!design->selected_member(module->name, proc->name))
+			if (!design->selected_member(module->meta_->name, it.first))
 				continue;
 
 			std::set<RTLIL::SigSpec> input_signals, output_signals;
@@ -549,22 +551,23 @@ struct ShowWorker
 				net_conn_map[node].color = nextColor(sig, net_conn_map[node].color);
 			}
 
-			std::string proc_src = proc->name.unescape();
+			std::string proc_name_str = design->twines.str(it.first);
+			std::string proc_src = design->twines.unescaped_str(it.first);
 			if (proc->has_attribute(ID::src) > 0)
 				proc_src = proc->get_src_attribute();
-			fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\", %s];\n", pidx, findLabel(proc->name.str()), proc_src.c_str(), findColor(proc->name).c_str());
+			fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\", %s];\n", pidx, findLabel(proc_name_str), proc_src.c_str(), findColor(RTLIL::IdString(proc_name_str)).c_str());
 		}
 
 		for (auto &conn : module->connections())
 		{
 			bool found_lhs_wire = false;
 			for (auto &c : conn.first.chunks()) {
-				if (c.wire == nullptr || design->selected_member(module->name, c.wire->name))
+				if (c.wire == nullptr || design->selected_member(module->meta_->name, c.wire->name.ref()))
 					found_lhs_wire = true;
 			}
 			bool found_rhs_wire = false;
 			for (auto &c : conn.second.chunks()) {
-				if (c.wire == nullptr || design->selected_member(module->name, c.wire->name))
+				if (c.wire == nullptr || design->selected_member(module->meta_->name, c.wire->name.ref()))
 					found_rhs_wire = true;
 			}
 			if (!found_lhs_wire || !found_rhs_wire)
@@ -645,16 +648,16 @@ struct ShowWorker
 			module = mod;
 			if (design->selected_whole_module(module->name)) {
 				if (module->get_blackbox_attribute()) {
-						//log("Skipping blackbox module %s.\n", module->name.unescape());
+						//log("Skipping blackbox module %s.\n", design->twines.unescaped_str(module->name));
 					continue;
 				} else
 				if (module->cells().size() == 0 && module->connections().empty() && module->processes.empty()) {
-					log("Skipping empty module %s.\n", module->name.unescape());
+					log("Skipping empty module %s.\n", design->twines.unescaped_str(module->name));
 					continue;
 				} else
-					log("Dumping module %s to page %d.\n", module->name.unescape(), ++page_counter);
+					log("Dumping module %s to page %d.\n", design->twines.unescaped_str(module->name), ++page_counter);
 			} else
-				log("Dumping selected parts of module %s to page %d.\n", module->name.unescape(), ++page_counter);
+				log("Dumping selected parts of module %s to page %d.\n", design->twines.unescaped_str(module->name), ++page_counter);
 			handle_module();
 		}
 	}

passes/cmds/splice.cc

@@ -75,7 +75,7 @@ struct SpliceWorker
 		RTLIL::SigSpec new_sig = sig;
 
 		if (sig_a.size() != sig.size()) {
-			RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($slice));
+			RTLIL::Cell *cell = module->addCell(NEW_TWINE, TW::$slice);
 			cell->parameters[ID::OFFSET] = offset;
 			cell->parameters[ID::A_WIDTH] = sig_a.size();
 			cell->parameters[ID::Y_WIDTH] = sig.size();
@@ -132,7 +132,7 @@ struct SpliceWorker
 		RTLIL::SigSpec new_sig = get_sliced_signal(chunks.front());
 		for (size_t i = 1; i < chunks.size(); i++) {
 			RTLIL::SigSpec sig2 = get_sliced_signal(chunks[i]);
-			RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($concat));
+			RTLIL::Cell *cell = module->addCell(NEW_TWINE, TW::$concat);
 			cell->parameters[ID::A_WIDTH] = new_sig.size();
 			cell->parameters[ID::B_WIDTH] = sig2.size();
 			cell->setPort(TW::A, new_sig);
@@ -149,7 +149,7 @@ struct SpliceWorker
 
 	void run()
 	{
-		log("Splicing signals in module %s:\n", module->name.unescape());
+		log("Splicing signals in module %s:\n", design->twines.unescaped_str(module->name));
 
 		driven_bits.push_back(RTLIL::State::Sm);
 		driven_bits.push_back(RTLIL::State::Sm);
@@ -165,7 +165,7 @@ struct SpliceWorker
 
 		for (auto cell : module->cells())
 		for (auto &conn : cell->connections())
-			if (!ct.cell_known(cell->type) || ct.cell_output(cell->type, conn.first)) {
+			if (!ct.cell_known(cell->type.ref()) || ct.cell_output(cell->type.ref(), conn.first)) {
 				RTLIL::SigSpec sig = sigmap(conn.second);
 				driven_chunks.insert(sig);
 				for (auto &bit : sig.to_sigbit_vector())
@@ -189,10 +189,10 @@ struct SpliceWorker
 			if (!sel_by_wire && !design->selected(module, cell))
 				continue;
 			for (auto &conn : cell->connections_)
-				if (ct.cell_input(cell->type, conn.first)) {
-					if (ports.size() > 0 && !ports.count(conn.first))
+				if (ct.cell_input(cell->type.ref(), conn.first)) {
+					if (ports.size() > 0 && !ports.count(RTLIL::IdString(design->twines.str(conn.first))))
 						continue;
-					if (no_ports.size() > 0 && no_ports.count(conn.first))
+					if (no_ports.size() > 0 && no_ports.count(RTLIL::IdString(design->twines.str(conn.first))))
 						continue;
 					RTLIL::SigSpec sig = sigmap(conn.second);
 					if (!sel_by_cell) {
@@ -231,8 +231,8 @@ struct SpliceWorker
 
 		for (auto &it : rework_wires)
 		{
-			RTLIL::IdString orig_name = it.first->name;
-			module->rename(it.first, NEW_ID);
+			TwineRef orig_name = it.first->name.ref();
+			module->rename(it.first, design->twines.add(NEW_TWINE));
 
 			RTLIL::Wire *new_port = module->addWire(orig_name, it.first);
 			it.first->port_id = 0;

passes/cmds/splitnets.cc

@@ -181,9 +181,9 @@ struct SplitnetsPass : public Pass {
 				for (auto c : module->cells())
 				for (auto &p : c->connections())
 				{
-					if (!ct.cell_known(c->type))
+					if (!ct.cell_known(c->type.ref()))
 						continue;
-					if (!ct.cell_output(c->type, p.first))
+					if (!ct.cell_output(c->type.ref(), p.first))
 						continue;
 
 					RTLIL::SigSpec sig = p.second;

passes/cmds/sta.cc

@@ -35,8 +35,8 @@ struct StaWorker
 
 	struct t_data {
 		Cell* driver;
-		IdString dst_port, src_port;
-		vector<tuple<SigBit,int,IdString>> fanouts;
+		TwineRef dst_port, src_port;
+		vector<tuple<SigBit,int,TwineRef>> fanouts;
 		SigBit backtrack;
 		t_data() : driver(nullptr) {}
 	};
@@ -44,7 +44,7 @@ struct StaWorker
 	std::deque<SigBit> queue;
 	struct t_endpoint {
 		Cell *sink;
-		IdString port;
+		TwineRef port;
 		int required;
 		t_endpoint() : sink(nullptr), required(0) {}
 	};
@@ -66,23 +66,23 @@ struct StaWorker
 			Module *inst_module = design->module(cell->type);
 			if (!inst_module) {
 				if (unrecognised_cells.insert(cell->type).second)
-					log_warning("Cell type '%s' not recognised! Ignoring.\n", cell->type.unescape());
+					log_warning("Cell type '%s' not recognised! Ignoring.\n", cell->type.unescaped());
 				continue;
 			}
 
 			if (!inst_module->get_blackbox_attribute()) {
-				log_warning("Cell type '%s' is not a black- nor white-box! Ignoring.\n", cell->type.unescape());
+				log_warning("Cell type '%s' is not a black- nor white-box! Ignoring.\n", cell->type.unescaped());
 				continue;
 			}
 
-			IdString derived_type = inst_module->derive(design, cell->parameters);
+			TwineRef derived_type = inst_module->derive(design, cell->parameters);
 			inst_module = design->module(derived_type);
 			log_assert(inst_module);
 
 			if (!timing.count(derived_type)) {
 				auto &t = timing.setup_module(inst_module);
 				if (t.has_inputs && t.comb.empty() && t.arrival.empty() && t.required.empty())
-					log_warning("Module '%s' has no timing arcs!\n", cell->type.unescape());
+					log_warning("Module '%s' has no timing arcs!\n", cell->type.unescaped());
 			}
 
 			auto &t = timing.at(derived_type);
@@ -206,7 +206,7 @@ struct StaWorker
 		log("Latest arrival time in '%s' is %d:\n", module, maxarrival);
 		auto it = endpoints.find(maxbit);
 		if (it != endpoints.end() && it->second.sink)
-			log("  %6d %s (%s.%s)\n", maxarrival, it->second.sink, it->second.sink->type.unescape(), it->second.port.unescape());
+			log("  %6d %s (%s.%s)\n", maxarrival, it->second.sink, design->twines.unescaped_str(it->second.sink->type), design->twines.unescaped_str(it->second.port));
 		else {
 			log("  %6d (%s)\n", maxarrival, b.wire->port_output ? "<primary output>" : "<unknown>");
 			if (!b.wire->port_output)
@@ -217,7 +217,7 @@ struct StaWorker
 			int arrival = b.wire->get_intvec_attribute(ID::sta_arrival)[b.offset];
 			if (jt->second.driver) {
 				log("           %s\n", log_signal(b));
-				log("  %6d %s (%s.%s->%s)\n", arrival, jt->second.driver, jt->second.driver->type.unescape(), jt->second.src_port.unescape(), jt->second.dst_port.unescape());
+				log("  %6d %s (%s.%s->%s)\n", arrival, jt->second.driver, design->twines.unescaped_str(jt->second.driver->type), design->twines.unescaped_str(jt->second.src_port), design->twines.unescaped_str(jt->second.dst_port));
 			}
 			else if (b.wire->port_input)
 				log("  %6d   %s (%s)\n", arrival, log_signal(b), "<primary input>");

passes/cmds/stat.cc

@@ -59,18 +59,18 @@ struct statdata_t {
 	double local_sequential_area = 0;
 	double submodule_area = 0;
 	int num_submodules = 0;
-	std::map<RTLIL::IdString, unsigned int, RTLIL::sort_by_id_str> num_submodules_by_type;
-	std::map<RTLIL::IdString, double, RTLIL::sort_by_id_str> submodules_area_by_type;
+	std::map<TwineRef, unsigned int, RTLIL::sort_by_id_str> num_submodules_by_type;
+	std::map<TwineRef, double, RTLIL::sort_by_id_str> submodules_area_by_type;
 
-	std::map<RTLIL::IdString, unsigned int, RTLIL::sort_by_id_str> local_num_cells_by_type;
-	std::map<RTLIL::IdString, double, RTLIL::sort_by_id_str> local_area_cells_by_type;
-	std::map<RTLIL::IdString, double, RTLIL::sort_by_id_str> local_seq_area_cells_by_type;
+	std::map<TwineRef, unsigned int, RTLIL::sort_by_id_str> local_num_cells_by_type;
+	std::map<TwineRef, double, RTLIL::sort_by_id_str> local_area_cells_by_type;
+	std::map<TwineRef, double, RTLIL::sort_by_id_str> local_seq_area_cells_by_type;
 	string tech;
 
-	std::map<RTLIL::IdString, unsigned int, RTLIL::sort_by_id_str> num_cells_by_type;
-	std::map<RTLIL::IdString, double, RTLIL::sort_by_id_str> area_cells_by_type;
-	std::map<RTLIL::IdString, double, RTLIL::sort_by_id_str> seq_area_cells_by_type;
-	std::set<RTLIL::IdString> unknown_cell_area;
+	std::map<TwineRef, unsigned int, RTLIL::sort_by_id_str> num_cells_by_type;
+	std::map<TwineRef, double, RTLIL::sort_by_id_str> area_cells_by_type;
+	std::map<TwineRef, double, RTLIL::sort_by_id_str> seq_area_cells_by_type;
+	std::set<TwineRef> unknown_cell_area;
 
 	statdata_t operator+(const statdata_t &other) const
 	{
@@ -141,7 +141,7 @@ struct statdata_t {
 		}
 	}
 
-	statdata_t(RTLIL::Design *design, const RTLIL::Module *mod, bool width_mode, dict<IdString, cell_area_t> &cell_area, string techname)
+	statdata_t(RTLIL::Design *design, const RTLIL::Module *mod, bool width_mode, dict<TwineRef, cell_area_t> &cell_area, string techname)
 	{
 		tech = techname;
 
@@ -183,35 +183,35 @@ struct statdata_t {
 			local_num_memory_bits += it.second->width * it.second->size;
 		}
 		for (auto cell : mod->selected_cells()) {
-			RTLIL::IdString cell_type = cell->type;
+			TwineRef cell_type = cell->type_impl;
 			if (width_mode) {
-				if (cell_type.in(ID($not), ID($pos), ID($neg), ID($logic_not), ID($logic_and), ID($logic_or), ID($reduce_and),
-						 ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($lut), ID($and), ID($or),
-						 ID($xor), ID($xnor), ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx), ID($lt),
-						 ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt), ID($add), ID($sub), ID($mul),
-						 ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow), ID($alu))) {
+				if (cell_type.in(TW($not), TW($pos), TW($neg), TW($logic_not), TW($logic_and), TW($logic_or), TW($reduce_and),
+						 TW($reduce_or), TW($reduce_xor), TW($reduce_xnor), TW($reduce_bool), TW($lut), TW($and), TW($or),
+						 TW($xor), TW($xnor), TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx), TW($lt),
+						 TW($le), TW($eq), TW($ne), TW($eqx), TW($nex), TW($ge), TW($gt), TW($add), TW($sub), TW($mul),
+						 TW($div), TW($mod), TW($divfloor), TW($modfloor), TW($pow), TW($alu))) {
 					int width_a = cell->hasPort(TW::A) ? GetSize(cell->getPort(TW::A)) : 0;
 					int width_b = cell->hasPort(TW::B) ? GetSize(cell->getPort(TW::B)) : 0;
 					int width_y = cell->hasPort(TW::Y) ? GetSize(cell->getPort(TW::Y)) : 0;
-					cell_type = stringf("%s_%d", cell_type, max<int>({width_a, width_b, width_y}));
-				} else if (cell_type.in(ID($mux)))
-					cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(TW::Y)));
-				else if (cell_type.in(ID($bmux), ID($pmux)))
+					cell_type = design->twines.add(Twine{stringf("%s_%d", cell_type, max<int>({width_a, width_b, width_y}))});
+				} else if (cell_type.in(TW($mux)))
+					cell_type = design->twines.add(Twine{stringf("%s_%d", cell_type, GetSize(cell->getPort(TW::Y)))});
+				else if (cell_type.in(TW($bmux), TW($pmux)))
 					cell_type =
-					  stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(TW::Y)), GetSize(cell->getPort(TW::S)));
-				else if (cell_type == ID($demux))
+					  design->twines.add(Twine{stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(TW::Y)), GetSize(cell->getPort(TW::S)))});
+				else if (cell_type == TW($demux))
 					cell_type =
-					  stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::S)));
-				else if (cell_type.in(ID($sr), ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe),
-						      ID($sdff), ID($sdffe), ID($sdffce), ID($aldff), ID($aldffe), ID($dlatch), ID($adlatch),
-						      ID($dlatchsr)))
-					cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(TW::Q)));
+					  design->twines.add(Twine{stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::S)))});
+				else if (cell_type.in(TW($sr), TW($ff), TW($dff), TW($dffe), TW($dffsr), TW($dffsre), TW($adff), TW($adffe),
+						      TW($sdff), TW($sdffe), TW($sdffce), TW($aldff), TW($aldffe), TW($dlatch), TW($adlatch),
+						      TW($dlatchsr)))
+					cell_type = design->twines.add(Twine{stringf("%s_%d", cell_type, GetSize(cell->getPort(TW::Q)))});
 			}
 
 			if (!cell_area.empty()) {
 				// check if cell_area provides a area calculator
-				if (cell_area.count(cell->type)) {
-					cell_area_t cell_data = cell_area.at(cell->type);
+				if (cell_area.count(cell->type_impl)) {
+					cell_area_t cell_data = cell_area.at(cell->type_impl);
 					if (cell_data.single_parameter_area.size() > 0) {
 						// assume that we just take the max of the A,B,Y ports
 
@@ -337,18 +337,16 @@ struct statdata_t {
 			num_processes++;
 			local_num_processes++;
 		}
-		RTLIL::IdString cell_name = mod->name;
-		auto s = cell_name.str();
 	}
 
 	unsigned int estimate_xilinx_lc()
 	{
-		unsigned int lut6_cnt = num_cells_by_type[ID(LUT6)];
-		unsigned int lut5_cnt = num_cells_by_type[ID(LUT5)];
-		unsigned int lut4_cnt = num_cells_by_type[ID(LUT4)];
-		unsigned int lut3_cnt = num_cells_by_type[ID(LUT3)];
-		unsigned int lut2_cnt = num_cells_by_type[ID(LUT2)];
-		unsigned int lut1_cnt = num_cells_by_type[ID(LUT1)];
+		unsigned int lut6_cnt = num_cells_by_type[TW::LUT6];
+		unsigned int lut5_cnt = num_cells_by_type[TW::LUT5];
+		unsigned int lut4_cnt = num_cells_by_type[TW::LUT4];
+		unsigned int lut3_cnt = num_cells_by_type[TW::LUT3];
+		unsigned int lut2_cnt = num_cells_by_type[TW::LUT2];
+		unsigned int lut1_cnt = num_cells_by_type[TW::LUT1];
 		unsigned int lc_cnt = 0;
 
 		lc_cnt += lut6_cnt;
@@ -505,7 +503,7 @@ struct statdata_t {
 		}
 	}
 
-	void log_data(RTLIL::IdString mod_name, bool top_mod, bool print_area = true, bool print_hierarchical = true, bool print_global_only = false)
+	void log_data(const TwinePool& twines, TwineRef mod_name, bool top_mod, bool print_area = true, bool print_hierarchical = true, bool print_global_only = false)
 	{
 
 		print_log_header(print_area, print_hierarchical, print_global_only);
@@ -523,7 +521,7 @@ struct statdata_t {
 		print_log_line("cells", local_num_cells, local_area, num_cells, area, 0, print_area, print_hierarchical, print_global_only);
 		for (auto &it : num_cells_by_type)
 			if (it.second) {
-				auto name = string(it.first.unescape());
+				auto name = twines.unescaped_str(it.first);
 				print_log_line(name, local_num_cells_by_type.count(it.first) ? local_num_cells_by_type.at(it.first) : 0,
 					       local_area_cells_by_type.count(it.first) ? local_area_cells_by_type.at(it.first) : 0, it.second,
 					       area_cells_by_type.at(it.first), 1, print_area, print_hierarchical, print_global_only);
@@ -533,7 +531,7 @@ struct statdata_t {
 				       print_global_only);
 			for (auto &it : num_submodules_by_type)
 				if (it.second)
-					print_log_line(string(it.first.unescape()), it.second, 0, it.second,
+					print_log_line(twines.unescaped_str(it.first), it.second, 0, it.second,
 						       submodules_area_by_type.count(it.first) ? submodules_area_by_type.at(it.first) : 0, 1,
 						       print_area, print_hierarchical, print_global_only);
 		}
@@ -582,7 +580,7 @@ struct statdata_t {
 			       count_local, area_local);
 	}
 
-	void log_data_json(const char *mod_name, bool first_module, bool hierarchical = false, bool global_only = false)
+	void log_data_json(const TwinePool& twines, const char *mod_name, bool first_module, bool hierarchical = false, bool global_only = false)
 	{
 		if (!first_module)
 			log(",\n");
@@ -607,7 +605,7 @@ struct statdata_t {
 				if (it.second) {
 					if (!first_line)
 						log(",\n");
-					log("            %s: %s", json11::Json(it.first.unescape()).dump(),
+					log("            %s: %s", json11::Json(twines.unescaped_str(it.first)).dump(),
 					    json_line(local_num_cells_by_type.count(it.first) ? local_num_cells_by_type.at(it.first) : 0,
 						      local_area_cells_by_type.count(it.first) ? local_area_cells_by_type.at(it.first) : 0, it.second,
 						      area_cells_by_type.at(it.first))
@@ -621,7 +619,7 @@ struct statdata_t {
 				if (it.second) {
 					if (!first_line)
 						log(",\n");
-					log("            %s: %s", json11::Json(it.first.unescape()).dump(),
+					log("            %s: %s", json11::Json(twines.unescaped_str(it.first)).dump(),
 					    json_line(0, 0, it.second,
 						      submodules_area_by_type.count(it.first) ? submodules_area_by_type.at(it.first) : 0)
 					      .c_str());
@@ -662,14 +660,14 @@ struct statdata_t {
 					if (it.second) {
 						if (!first_line)
 							log(",\n");
-						log("            %s: %u", json11::Json(it.first.unescape()).dump(), it.second);
+						log("            %s: %u", json11::Json(twines.unescaped_str(it.first)).dump(), it.second);
 						first_line = false;
 					}
 				for (auto &it : num_submodules_by_type)
 					if (it.second) {
 						if (!first_line)
 							log(",\n");
-						log("            %s: %u", json11::Json(it.first.unescape()).dump(), it.second);
+						log("            %s: %u", json11::Json(twines.unescaped_str(it.first)).dump(), it.second);
 						first_line = false;
 					}
 				log("\n");
@@ -697,14 +695,14 @@ struct statdata_t {
 					if (it.second) {
 						if (!first_line)
 							log(",\n");
-						log("            %s: %u", json11::Json(it.first.unescape()).dump(), it.second);
+						log("            %s: %u", json11::Json(twines.unescaped_str(it.first)).dump(), it.second);
 						first_line = false;
 					}
 				for (auto &it : num_submodules_by_type)
 					if (it.second) {
 						if (!first_line)
 							log(",\n");
-						log("            %s: %u", json11::Json(it.first.unescape()).dump(), it.second);
+						log("            %s: %u", json11::Json(twines.unescaped_str(it.first)).dump(), it.second);
 						first_line = false;
 					}
 				log("\n");
@@ -726,7 +724,7 @@ struct statdata_t {
 	}
 };
 
-statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTLIL::IdString mod, int level, bool quiet = false, bool has_area = true,
+statdata_t hierarchy_worker(const TwinePool& twines, std::map<TwineRef, statdata_t> &mod_stat, TwineRef mod, int level, bool quiet = false, bool has_area = true,
 			    bool hierarchy_mode = true)
 {
 	statdata_t mod_data = mod_stat.at(mod);
@@ -734,60 +732,60 @@ statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTL
 	for (auto &it : mod_data.num_submodules_by_type) {
 		if (mod_stat.count(it.first) > 0) {
 			if (!quiet)
-				mod_data.print_log_line(string(it.first.unescape()), mod_stat.at(it.first).local_num_cells,
+				mod_data.print_log_line(twines.unescaped_str(it.first), mod_stat.at(it.first).local_num_cells,
 							mod_stat.at(it.first).local_area, mod_stat.at(it.first).num_cells, mod_stat.at(it.first).area,
 							level, has_area, hierarchy_mode);
-			hierarchy_worker(mod_stat, it.first, level + 1, quiet, has_area, hierarchy_mode) * it.second;
+			hierarchy_worker(twines, mod_stat, it.first, level + 1, quiet, has_area, hierarchy_mode) * it.second;
 		}
 	}
 
 	return mod_data;
 }
 
-statdata_t hierarchy_builder(RTLIL::Design *design, const RTLIL::Module *top_mod, std::map<RTLIL::IdString, statdata_t> &mod_stat,
-			     bool width_mode, dict<IdString, cell_area_t> &cell_area, string techname)
+statdata_t hierarchy_builder(RTLIL::Design *design, const RTLIL::Module *top_mod, std::map<TwineRef, statdata_t> &mod_stat,
+			     bool width_mode, dict<TwineRef, cell_area_t> &cell_area, string techname)
 {
 	if (top_mod == nullptr)
 		top_mod = design->top_module();
 	statdata_t mod_data(design, top_mod, width_mode, cell_area, techname);
 	for (auto cell : top_mod->selected_cells()) {
-		if (cell_area.count(cell->type) == 0) {
-			if (design->has(cell->type)) {
+		if (cell_area.count(cell->type_impl) == 0) {
+			if (design->has(cell->type_impl)) {
 				if (!(design->module(cell->type)->attributes.count(ID::blackbox))) {
 					// deal with modules
 					mod_data.add(
 					  hierarchy_builder(design, design->module(cell->type), mod_stat, width_mode, cell_area, techname));
-					mod_data.num_submodules_by_type[cell->type]++;
-					mod_data.submodules_area_by_type[cell->type] += mod_stat.at(cell->type).area;
-					mod_data.submodule_area += mod_stat.at(cell->type).area;
+					mod_data.num_submodules_by_type[cell->type_impl]++;
+					mod_data.submodules_area_by_type[cell->type_impl] += mod_stat.at(cell->type_impl).area;
+					mod_data.submodule_area += mod_stat.at(cell->type_impl).area;
 					mod_data.num_submodules++;
-					mod_data.unknown_cell_area.erase(cell->type);
+					mod_data.unknown_cell_area.erase(cell->type_impl);
 					mod_data.num_cells -=
-					  (mod_data.num_cells_by_type.count(cell->type) != 0) ? mod_data.num_cells_by_type.at(cell->type) : 0;
-					mod_data.num_cells_by_type.erase(cell->type);
-					mod_data.local_num_cells -= (mod_data.local_num_cells_by_type.count(cell->type) != 0)
-								      ? mod_data.local_num_cells_by_type.at(cell->type)
+					  (mod_data.num_cells_by_type.count(cell->type_impl) != 0) ? mod_data.num_cells_by_type.at(cell->type_impl) : 0;
+					mod_data.num_cells_by_type.erase(cell->type_impl);
+					mod_data.local_num_cells -= (mod_data.local_num_cells_by_type.count(cell->type_impl) != 0)
+								      ? mod_data.local_num_cells_by_type.at(cell->type_impl)
 								      : 0;
-					mod_data.local_num_cells_by_type.erase(cell->type);
-					mod_data.local_area_cells_by_type.erase(cell->type);
+					mod_data.local_num_cells_by_type.erase(cell->type_impl);
+					mod_data.local_area_cells_by_type.erase(cell->type_impl);
 				} else {
 					// deal with blackbox cells
 					if (design->module(cell->type)->attributes.count(ID::area) &&
 					    design->module(cell->type)->attributes.at(ID::area).size() == 0) {
-						mod_data.num_submodules_by_type[cell->type]++;
+						mod_data.num_submodules_by_type[cell->type_impl]++;
 						mod_data.num_submodules++;
-						mod_data.submodules_area_by_type[cell->type] +=
-						  double(design->module(cell->type)->attributes.at(ID::area).as_int());
-						mod_data.area += double(design->module(cell->type)->attributes.at(ID::area).as_int());
-						mod_data.unknown_cell_area.erase(cell->type);
+						mod_data.submodules_area_by_type[cell->type_impl] +=
+						  double(design->module(cell->type_impl)->attributes.at(ID::area).as_int());
+						mod_data.area += double(design->module(cell->type_impl)->attributes.at(ID::area).as_int());
+						mod_data.unknown_cell_area.erase(cell->type_impl);
 						mod_data.num_cells -=
-						  (mod_data.num_cells_by_type.count(cell->type) != 0) ? mod_data.num_cells_by_type.at(cell->type) : 0;
-						mod_data.num_cells_by_type.erase(cell->type);
-						mod_data.local_num_cells -= (mod_data.local_num_cells_by_type.count(cell->type) != 0)
-									      ? mod_data.local_num_cells_by_type.at(cell->type)
+						  (mod_data.num_cells_by_type.count(cell->type_impl) != 0) ? mod_data.num_cells_by_type.at(cell->type_impl) : 0;
+						mod_data.num_cells_by_type.erase(cell->type_impl);
+						mod_data.local_num_cells -= (mod_data.local_num_cells_by_type.count(cell->type_impl) != 0)
+									      ? mod_data.local_num_cells_by_type.at(cell->type_impl)
 									      : 0;
-						mod_data.local_num_cells_by_type.erase(cell->type);
-						mod_data.local_area_cells_by_type.erase(cell->type);
+						mod_data.local_num_cells_by_type.erase(cell->type_impl);
+						mod_data.local_area_cells_by_type.erase(cell->type_impl);
 					}
 				}
 			}
@@ -797,7 +795,7 @@ statdata_t hierarchy_builder(RTLIL::Design *design, const RTLIL::Module *top_mod
 	return mod_data;
 }
 
-void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_area, string liberty_file)
+void read_liberty_cellarea(TwinePool& twines, dict<TwineRef, cell_area_t> &cell_area, string liberty_file)
 {
 	std::istream *f = uncompressed(liberty_file.c_str());
 	yosys_input_files.insert(liberty_file);
@@ -874,7 +872,8 @@ void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_area, string libert
 
 		if (ar != nullptr && !ar->value.empty()) {
 			string prefix = cell->args[0].substr(0, 1) == "$" ? "" : "\\";
-			cell_area[prefix + cell->args[0]] = {atof(ar->value.c_str()), is_flip_flop, single_parameter_area, double_parameter_area,
+			TwineRef t = twines.add(Twine{prefix + cell->args[0]});
+			cell_area[t] = {atof(ar->value.c_str()), is_flip_flop, single_parameter_area, double_parameter_area,
 							     port_names};
 		}
 	}
@@ -927,8 +926,8 @@ struct StatPass : public Pass {
 	{
 		bool width_mode = false, json_mode = false, hierarchy_mode = false;
 		RTLIL::Module *top_mod = nullptr;
-		std::map<RTLIL::IdString, statdata_t> mod_stat;
-		dict<IdString, cell_area_t> cell_area;
+		std::map<TwineRef, statdata_t> mod_stat;
+		dict<TwineRef, cell_area_t> cell_area;
 		string techname;
 
 		size_t argidx;
@@ -940,7 +939,7 @@ struct StatPass : public Pass {
 			if (args[argidx] == "-liberty" && argidx + 1 < args.size()) {
 				string liberty_file = args[++argidx];
 				rewrite_filename(liberty_file);
-				read_liberty_cellarea(cell_area, liberty_file);
+				read_liberty_cellarea(design->twines, cell_area, liberty_file);
 				continue;
 			}
 			if (args[argidx] == "-tech" && argidx + 1 < args.size()) {
@@ -1005,13 +1004,13 @@ struct StatPass : public Pass {
 					top_mod = mod;
 			statdata_t data = mod_stat.at(mod->name);
 			if (json_mode) {
-				data.log_data_json(mod->name.c_str(), first_module, hierarchy_mode);
+				data.log_data_json(design->twines, mod->name.c_str(), first_module, hierarchy_mode);
 				first_module = false;
 			} else {
 				log("\n");
-				log("=== %s%s ===\n", mod->name.unescape(), mod->is_selected_whole() ? "" : " (partially selected)");
+				log("=== %s%s ===\n", design->twines.unescaped_str(mod->name), mod->is_selected_whole() ? "" : " (partially selected)");
 				log("\n");
-				data.log_data(mod->name, false, has_area, hierarchy_mode);
+				data.log_data(design->twines, mod->name, false, has_area, hierarchy_mode);
 			}
 		}
 
@@ -1031,13 +1030,13 @@ struct StatPass : public Pass {
 								       mod_stat[top_mod->name].area, 0, has_area, hierarchy_mode, true);
 			}
 
-			statdata_t data = hierarchy_worker(mod_stat, top_mod->name, 0, /*quiet=*/json_mode, has_area, hierarchy_mode);
+			statdata_t data = hierarchy_worker(design->twines, mod_stat, top_mod->name, 0, /*quiet=*/json_mode, has_area, hierarchy_mode);
 
 			if (json_mode)
-				data.log_data_json("design", true, hierarchy_mode, true);
+				data.log_data_json(design->twines, "design", true, hierarchy_mode, true);
 			else if (GetSize(mod_stat) > 1) {
 				log("\n");
-				data.log_data(top_mod->name, true, has_area, hierarchy_mode, true);
+				data.log_data(design->twines, top_mod->name, true, has_area, hierarchy_mode, true);
 			}
 
 			design->scratchpad_set_int("stat.num_wires", data.num_wires);

passes/cmds/test_patch.cc

@@ -17,12 +17,12 @@ struct TestPatchPass : public Pass {
 		for (auto module : design->selected_modules()) {
 			SigMap sigmap(module);
 			for (auto cell : module->selected_cells()) {
-				if (cell->type == ID($add)) {
+				if (cell->type == TW($add)) {
 					Cell* add = cell;
 					log_assert(add->getPort(TW::B).is_wire());
 					log_assert(add->getPort(TW::B).known_driver());
 					auto neg = add->getPort(TW::B)[0].wire->driverCell();
-					log_assert(neg->type == ID($not));
+					log_assert(neg->type == TW($not));
 					RTLIL::Patch patcher(module, nullptr);
 					int width = cell->getPort(TW::A).size();
 					auto sub = patcher.addSub(NEW_TWINE,

passes/cmds/timeest.cc

@@ -66,8 +66,8 @@ struct EstimateSta {
 	// and to account for the AIG model not being balanced
 	int cell_type_factor(IdString type)
 	{
-		if (type.in(ID($gt), ID($ge), ID($lt), ID($le), ID($add), ID($sub),
-					ID($logic_not), ID($reduce_and), ID($reduce_or), ID($eq)))
+		if (type.in(TW($gt), TW($ge), TW($lt), TW($le), TW($add), TW($sub),
+					TW($logic_not), TW($reduce_and), TW($reduce_or), TW($eq)))
 			return 1;
 		else
 			return 2;
@@ -97,7 +97,7 @@ struct EstimateSta {
 				FfData ff(nullptr, cell);
 				if (!ff.has_clk) {
 					log_warning("Ignoring unsupported storage element '%s' (%s)\n",
-								cell, cell->type.unescape());
+								cell, cell->type.unescaped());
 					continue;
 				}
 				if (!clk || ff.sig_clk.as_bit() != *clk)
@@ -112,7 +112,7 @@ struct EstimateSta {
 			} else if (cell->is_mem_cell()) {
 				// memories handled separately
 				continue;
-			} else if (cell->type == ID($scopeinfo)) {
+			} else if (cell->type == TW($scopeinfo)) {
 				continue;
 			} else {
 				// find or build AIG model of combinational cell
@@ -121,7 +121,7 @@ struct EstimateSta {
 					aigs.emplace(fingerprint, Aig(cell));
 					if (aigs.at(fingerprint).name.empty()) {
 						log_error("Unsupported cell '%s' in module '%s'",
-								  cell->type.unescape(), m);
+								  cell->type.unescaped(), m);
 					}					
 				}
 
@@ -342,7 +342,7 @@ struct EstimateSta {
 						std::string src_attr = cell->get_src_attribute();
 						cell_src = stringf(" source: %s", src_attr);
 					}
-					log("    cell %s (%s)%s\n", cell, cell->type.unescape(), cell_src);
+					log("    cell %s (%s)%s\n", cell, cell->type.unescaped(), cell_src);
 					printed.insert(cell);
 				}
 			} else {

passes/cmds/torder.cc

@@ -83,13 +83,13 @@ struct TorderPass : public Pass {
 			for (auto cell : module->selected_cells())
 			for (auto conn : cell->connections())
 			{
-				if (stop_db.count(cell->type) && stop_db.at(cell->type).count(conn.first))
+				if (stop_db.count(RTLIL::IdString(cell->type)) && stop_db.at(RTLIL::IdString(cell->type)).count(RTLIL::IdString(design->twines.str(conn.first))))
 					continue;
 
-				if (!noautostop && yosys_celltypes.cell_known(cell->type)) {
+				if (!noautostop && yosys_celltypes.cell_known(cell->type.ref())) {
 					if (conn.first.in(ID::Q, ID::CTRL_OUT, ID::RD_DATA))
 						continue;
-					if (cell->type.in(ID($memrd), ID($memrd_v2)) && conn.first == ID::DATA)
+					if (cell->type.in(TW($memrd), TW($memrd_v2)) && conn.first == ID::DATA)
 						continue;
 				}
 

passes/cmds/trace.cc

@@ -38,7 +38,7 @@ struct TraceMonitor : public RTLIL::Monitor
 
 	void notify_connect(RTLIL::Cell *cell, TwineRef port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
 	{
-		log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", cell->module, cell, port.unescape(), log_signal(sig), log_signal(old_sig));
+		log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", cell->module, cell, cell->module->design->twines.unescaped_str(port).c_str(), log_signal(sig), log_signal(old_sig));
 	}
 
 	void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) override

passes/cmds/viz.cc

@@ -309,12 +309,12 @@ struct Graph {
 		{
 			GraphNode *g = nullptr;
 
-			if (!grp.second.selected_module(module->name))
+			if (!grp.second.selected_module(module->meta_->name))
 				continue;
 
 			for (auto wire : module->wires()) {
 				if (!wire->name.isPublic()) continue;
-				if (!grp.second.selected_member(module->name, wire->name)) continue;
+				if (!grp.second.selected_member(module->meta_->name, wire->name.ref())) continue;
 				for (auto bit : sigmap(wire)) {
 					auto it = wire_nodes.find(bit);
 					if (it == wire_nodes.end())
@@ -708,8 +708,8 @@ struct VizWorker
 			c->attributes.erase(vg_id);
 		for (auto g : graph.nodes) {
 			for (auto name : g->names()) {
-				auto w = module->wire(name);
-				auto c = module->cell(name);
+				auto w = module->wire(module->design->twines.lookup(name.str()));
+				auto c = module->cell(module->design->twines.lookup(name.str()));
 				if (w) w->attributes[vg_id] = g->index;
 				if (c) c->attributes[vg_id] = g->index;
 			}
@@ -718,7 +718,7 @@ struct VizWorker
 
 	void write_dot(FILE *f)
 	{
-		fprintf(f, "digraph \"%s\" {\n", module->name.unescape().c_str());
+		fprintf(f, "digraph \"%s\" {\n", design->twines.unescaped_str(module->name).c_str());
 		fprintf(f, "  rankdir = LR;\n");
 
 		dict<GraphNode*, std::vector<std::vector<std::string>>> extra_lines;
@@ -782,7 +782,7 @@ struct VizWorker
 				g->names().sort();
 				std::string label; // = stringf("vg=%d\\n", g->index);
 				for (auto n : g->names())
-					label = label + (label.empty() ? "" : "\\n") + n.unescape();
+					label = label + (label.empty() ? "" : "\\n") + design->twines.unescaped_str(n);
 				fprintf(f, "\tn%d [shape=rectangle,label=\"%s\"];\n", g->index, label.c_str());
 			} else {
 				std::string label = stringf("vg=%d | %d cells", g->index, GetSize(g->names()));

passes/cmds/wrapcell.cc

@@ -208,13 +208,13 @@ struct WrapcellPass : Pass {
 				Module *subm;
 				Cell *subcell;
 
-				if (!ct.cell_known(cell->type))
+				if (!ct.cell_known(cell->type_impl))
 					log_error("Non-internal cell type '%s' on cell '%s' in module '%s' unsupported\n",
-							  cell->type.unescape(), cell, module);
+							  cell->type.unescaped(), cell, module);
 
 				std::vector<std::pair<IdString, int>> unused_outputs, used_outputs;
 				for (auto conn : cell->connections()) {
-					if (ct.cell_output(cell->type, conn.first))
+					if (ct.cell_output(cell->type_impl, conn.first))
 					for (int i = 0; i < conn.second.size(); i++) {
 						if (tracking_unused && unused.check(conn.second[i]))
 							unused_outputs.emplace_back(conn.first, i);
@@ -227,7 +227,7 @@ struct WrapcellPass : Pass {
 				if (!unused_outputs.empty()) {
 					context.unused_outputs += "_unused";
 					for (auto chunk : collect_chunks(unused_outputs))
-						context.unused_outputs += "_" + chunk.format(cell).unescape();
+						context.unused_outputs += "_" + design->twines.unescaped_str(chunk.format(cell));
 				}
 
 				std::optional<std::string> unescaped_name = format_with_params(name_fmt, cell->parameters, context);
@@ -242,7 +242,7 @@ struct WrapcellPass : Pass {
 				subm = d->addModule(name);
 				subcell = subm->addCell("$1", cell->type);
 				for (auto conn : cell->connections()) {
-					if (ct.cell_output(cell->type, conn.first)) {
+					if (ct.cell_output(cell->type_impl, conn.first)) {
 						// Insert marker bits as placehodlers which need to be replaced
 						subcell->setPort(conn.first, SigSpec(RTLIL::Sm, conn.second.size()));
 					} else {
@@ -286,7 +286,7 @@ struct WrapcellPass : Pass {
 				dict<IdString, SigSpec> new_connections;
 
 				for (auto conn : cell->connections())
-				if (!ct.cell_output(cell->type, conn.first))
+				if (!ct.cell_output(cell->type_impl, conn.first))
 					new_connections[conn.first] = conn.second;
 
 				for (auto chunk : collect_chunks(used_outputs))

passes/cmds/xprop.cc

@@ -294,18 +294,18 @@ struct XpropWorker
 	}
 
 	void mark_maybe_x(Cell *cell) {
-		if (cell->type.in(ID($bweqx), ID($eqx), ID($nex), ID($initstate), ID($assert), ID($assume), ID($cover), ID($anyseq), ID($anyconst)))
+		if (cell->type.in(TW($bweqx), TW($eqx), TW($nex), TW($initstate), TW($assert), TW($assume), TW($cover), TW($anyseq), TW($anyconst)))
 			return;
 
-		if (cell->type.in(ID($pmux))) {
+		if (cell->type.in(TW($pmux))) {
 			mark_outputs_maybe_x(cell);
 			return;
 		}
 
-		if (cell->is_builtin_ff() || cell->type == ID($anyinit)) {
+		if (cell->is_builtin_ff() || cell->type == TW($anyinit)) {
 			FfData ff(&initvals, cell);
 
-			if (cell->type != ID($anyinit))
+			if (cell->type != TW($anyinit))
 				for (int i = 0; i < ff.width; i++)
 					if (ff.val_init[i] == State::Sx)
 						mark_maybe_x(ff.sig_q[i]);
@@ -318,7 +318,7 @@ struct XpropWorker
 				return;
 		}
 
-		if (cell->type == ID($not)) {
+		if (cell->type == TW($not)) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
 			for (int i = 0; i < GetSize(sig_y); i++)
@@ -327,7 +327,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
+		if (cell->type.in(TW($and), TW($or), TW($xor), TW($xnor))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
 			auto sig_b = cell->getPort(TW::B); sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
@@ -337,7 +337,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($bwmux))) {
+		if (cell->type.in(TW($bwmux))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto &sig_a = cell->getPort(TW::A);
 			auto &sig_b = cell->getPort(TW::B);
@@ -348,7 +348,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($_MUX_), ID($mux), ID($bmux))) {
+		if (cell->type.in(TW($_MUX_), TW($mux), TW($bmux))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto &sig_a = cell->getPort(TW::A);
 			auto &sig_b = cell->getPort(TW::B);
@@ -372,7 +372,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($demux))) {
+		if (cell->type.in(TW($demux))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto &sig_a = cell->getPort(TW::A);
 			auto &sig_s = cell->getPort(TW::S);
@@ -387,7 +387,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift))) {
+		if (cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift))) {
 			auto &sig_b = cell->getPort(TW::B);
 			auto &sig_y = cell->getPort(TW::Y);
 
@@ -407,7 +407,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($shiftx))) {
+		if (cell->type.in(TW($shiftx))) {
 			auto &sig_b = cell->getPort(TW::B);
 			auto &sig_y = cell->getPort(TW::Y);
 
@@ -438,24 +438,24 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($add), ID($sub), ID($mul), ID($neg))) {
+		if (cell->type.in(TW($add), TW($sub), TW($mul), TW($neg))) {
 			if (inputs_maybe_x(cell))
 				mark_outputs_maybe_x(cell);
 			return;
 		}
 
-		if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
+		if (cell->type.in(TW($div), TW($mod), TW($divfloor), TW($modfloor))) {
 			mark_outputs_maybe_x(cell);
 			return;
 		}
 
 		if (cell->type.in(
-			ID($le), ID($lt), ID($ge), ID($gt),
-			ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor),
-			ID($reduce_bool), ID($logic_not), ID($logic_or), ID($logic_and),
-			ID($eq), ID($ne),
+			TW($le), TW($lt), TW($ge), TW($gt),
+			TW($reduce_and), TW($reduce_or), TW($reduce_xor), TW($reduce_xnor),
+			TW($reduce_bool), TW($logic_not), TW($logic_or), TW($logic_and),
+			TW($eq), TW($ne),
 
-			ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_ANDNOT_), ID($_OR_), ID($_NOR_), ID($_ORNOT_), ID($_XOR_), ID($_XNOR_)
+			TW($_NOT_), TW($_AND_), TW($_NAND_), TW($_ANDNOT_), TW($_OR_), TW($_NOR_), TW($_ORNOT_), TW($_XOR_), TW($_XNOR_)
 		)) {
 			auto &sig_y = cell->getPort(TW::Y);
 			if (inputs_maybe_x(cell))
@@ -463,11 +463,11 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($scopeinfo))) {
+		if (cell->type.in(TW($scopeinfo))) {
 			return;
 		}
 
-		log_warning("Unhandled cell %s (%s) during maybe-x marking\n", cell, cell->type.unescape());
+		log_warning("Unhandled cell %s (%s) during maybe-x marking\n", cell, cell->type.unescaped());
 		mark_outputs_maybe_x(cell);
 	}
 
@@ -481,7 +481,7 @@ struct XpropWorker
 	{
 		if (!ports_maybe_x(cell)) {
 
-			if (cell->type == ID($bweq)) {
+			if (cell->type == TW($bweq)) {
 				auto sig_y = cell->getPort(TW::Y);
 				auto sig_a = cell->getPort(TW::A);
 				auto sig_b = cell->getPort(TW::B);
@@ -492,7 +492,7 @@ struct XpropWorker
 				return;
 			}
 
-			if (cell->type.in(ID($nex), ID($eqx))) {
+			if (cell->type.in(TW($nex), TW($eqx))) {
 				auto sig_y = cell->getPort(TW::Y);
 				auto sig_a = cell->getPort(TW::A);
 				auto sig_b = cell->getPort(TW::B);
@@ -500,7 +500,7 @@ struct XpropWorker
 				RTLIL::IdString name(cell->name);
 				auto type = cell->type;
 				module->remove(cell);
-				if (type == ID($eqx))
+				if (type == TW($eqx))
 					module->addEq(name, sig_a, sig_b, sig_y);
 				else
 					module->addNe(name, sig_a, sig_b, sig_y);
@@ -510,10 +510,10 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($not), ID($_NOT_))) {
+		if (cell->type.in(TW($not), TW($_NOT_))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A);
-			if (cell->type == ID($not))
+			if (cell->type == TW($not))
 				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
 
 			auto enc_a = encoded(sig_a);
@@ -527,11 +527,11 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($and), ID($or), ID($_AND_), ID($_OR_), ID($_NAND_), ID($_NOR_), ID($_ANDNOT_), ID($_ORNOT_))) {
+		if (cell->type.in(TW($and), TW($or), TW($_AND_), TW($_OR_), TW($_NAND_), TW($_NOR_), TW($_ANDNOT_), TW($_ORNOT_))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A);
 			auto sig_b = cell->getPort(TW::B);
-			if (cell->type.in(ID($and), ID($or))) {
+			if (cell->type.in(TW($and), TW($or))) {
 				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
 				sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
 			}
@@ -540,11 +540,11 @@ struct XpropWorker
 			auto enc_b = encoded(sig_b);
 			auto enc_y = encoded(sig_y, true);
 
-			if (cell->type.in(ID($or), ID($_OR_), ID($_NOR_), ID($_ORNOT_)))
+			if (cell->type.in(TW($or), TW($_OR_), TW($_NOR_), TW($_ORNOT_)))
 				enc_a.invert(), enc_b.invert(), enc_y.invert();
-			if (cell->type.in(ID($_NAND_), ID($_NOR_)))
+			if (cell->type.in(TW($_NAND_), TW($_NOR_)))
 				enc_y.invert();
-			if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
+			if (cell->type.in(TW($_ANDNOT_), TW($_ORNOT_)))
 				enc_b.invert();
 
 			enc_y.connect_0(module->Or(NEW_TWINE, enc_a.is_0, enc_b.is_0));
@@ -554,7 +554,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($logic_not))) {
+		if (cell->type.in(TW($reduce_and), TW($reduce_or), TW($reduce_bool), TW($logic_not))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto &sig_a = cell->getPort(TW::A);
 
@@ -563,9 +563,9 @@ struct XpropWorker
 
 			enc_y.connect_as_bool();
 
-			if (cell->type.in(ID($reduce_or), ID($reduce_bool)))
+			if (cell->type.in(TW($reduce_or), TW($reduce_bool)))
 				enc_a.invert(), enc_y.invert();
-			if (cell->type == ID($logic_not))
+			if (cell->type == TW($logic_not))
 				enc_a.invert();
 
 			enc_y.connect_0(module->ReduceOr(NEW_TWINE, enc_a.is_0));
@@ -576,7 +576,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
+		if (cell->type.in(TW($reduce_xor), TW($reduce_xnor))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto &sig_a = cell->getPort(TW::A);
 
@@ -584,7 +584,7 @@ struct XpropWorker
 			auto enc_y = encoded(sig_y, true);
 
 			enc_y.connect_as_bool();
-			if (cell->type == ID($reduce_xnor))
+			if (cell->type == TW($reduce_xnor))
 				enc_y.invert();
 
 
@@ -596,7 +596,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($logic_and), ID($logic_or))) {
+		if (cell->type.in(TW($logic_and), TW($logic_or))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto &sig_a = cell->getPort(TW::A);
 			auto &sig_b = cell->getPort(TW::B);
@@ -612,7 +612,7 @@ struct XpropWorker
 			auto b_is_1 = module->ReduceOr(NEW_TWINE, enc_b.is_1);
 			auto b_is_0 = module->ReduceAnd(NEW_TWINE, enc_b.is_0);
 
-			if (cell->type == ID($logic_or))
+			if (cell->type == TW($logic_or))
 				 enc_y.invert(), std::swap(a_is_0, a_is_1), std::swap(b_is_0, b_is_1);
 
 			enc_y.connect_0(module->Or(NEW_TWINE, a_is_0, b_is_0));
@@ -622,11 +622,11 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($xor), ID($xnor), ID($_XOR_), ID($_XNOR_))) {
+		if (cell->type.in(TW($xor), TW($xnor), TW($_XOR_), TW($_XNOR_))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A);
 			auto sig_b = cell->getPort(TW::B);
-			if (cell->type.in(ID($xor), ID($xnor))) {
+			if (cell->type.in(TW($xor), TW($xnor))) {
 				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
 				sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
 			}
@@ -635,7 +635,7 @@ struct XpropWorker
 			auto enc_b = encoded(sig_b);
 			auto enc_y = encoded(sig_y, true);
 
-			if (cell->type.in(ID($xnor), ID($_XNOR_)))
+			if (cell->type.in(TW($xnor), TW($_XNOR_)))
 				enc_y.invert();
 
 			enc_y.connect_x(module->Or(NEW_TWINE, enc_a.is_x, enc_b.is_x));
@@ -645,7 +645,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($eq), ID($ne))) {
+		if (cell->type.in(TW($eq), TW($ne))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A);
 			auto sig_b = cell->getPort(TW::B);
@@ -658,7 +658,7 @@ struct XpropWorker
 			auto enc_y = encoded(sig_y, true);
 			enc_y.connect_as_bool();
 
-			if (cell->type == ID($ne))
+			if (cell->type == TW($ne))
 				enc_y.invert();
 
 			auto delta = module->Xor(NEW_TWINE, enc_a.is_1, enc_b.is_1);
@@ -671,7 +671,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($eqx), ID($nex))) {
+		if (cell->type.in(TW($eqx), TW($nex))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A);
 			auto sig_b = cell->getPort(TW::B);
@@ -687,7 +687,7 @@ struct XpropWorker
 
 			auto eq = module->ReduceAnd(NEW_TWINE, {delta_0, delta_1});
 
-			auto res = cell->type == ID($nex) ? module->Not(NEW_TWINE, eq) : eq;
+			auto res = cell->type == TW($nex) ? module->Not(NEW_TWINE, eq) : eq;
 
 			module->connect(sig_y[0], res);
 			if (GetSize(sig_y) > 1)
@@ -696,7 +696,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($bweqx))) {
+		if (cell->type.in(TW($bweqx))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto &sig_a = cell->getPort(TW::A);
 			auto &sig_b = cell->getPort(TW::B);
@@ -711,13 +711,13 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($_MUX_), ID($mux), ID($bwmux))) {
+		if (cell->type.in(TW($_MUX_), TW($mux), TW($bwmux))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto &sig_a = cell->getPort(TW::A);
 			auto &sig_b = cell->getPort(TW::B);
 			auto sig_s = cell->getPort(TW::S);
 
-			if (cell->type == ID($mux))
+			if (cell->type == TW($mux))
 				sig_s = SigSpec(sig_s[0], GetSize(sig_y));
 
 			auto enc_a = encoded(sig_a);
@@ -736,7 +736,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($pmux))) {
+		if (cell->type.in(TW($pmux))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto &sig_a = cell->getPort(TW::A);
 			auto &sig_b = cell->getPort(TW::B);
@@ -771,7 +771,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) {
+		if (cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto &sig_a = cell->getPort(TW::A);
 			auto &sig_b = cell->getPort(TW::B);
@@ -787,9 +787,9 @@ struct XpropWorker
 			SigSpec y_1 = module->addWire(NEW_TWINE, GetSize(sig_y));
 			SigSpec y_x = module->addWire(NEW_TWINE, GetSize(sig_y));
 
-			auto encoded_type = cell->type == ID($shiftx) ? ID($shift) : cell->type;
+			auto encoded_type = cell->type == TW($shiftx) ? TW($shift) : cell->type;
 
-			if (cell->type == ID($shiftx)) {
+			if (cell->type == TW($shiftx)) {
 				std::swap(enc_a.is_0, enc_a.is_x);
 			}
 
@@ -813,7 +813,7 @@ struct XpropWorker
 
 			SigSpec y_0 = module->Not(NEW_TWINE, y_not_0);
 
-			if (cell->type == ID($shiftx))
+			if (cell->type == TW($shiftx))
 				std::swap(y_0, y_x);
 
 			enc_y.connect_0(module->And(NEW_TWINE, y_0, SigSpec(not_all_x, GetSize(sig_y))));
@@ -824,7 +824,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($ff))) {
+		if (cell->type.in(TW($ff))) {
 			auto &sig_d = cell->getPort(TW::D);
 			auto &sig_q = cell->getPort(TW::Q);
 
@@ -857,12 +857,12 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->is_builtin_ff() || cell->type == ID($anyinit)) {
+		if (cell->is_builtin_ff() || cell->type == TW($anyinit)) {
 			FfData ff(&initvals, cell);
 
 			if ((ff.has_clk || ff.has_gclk) && !ff.has_ce && !ff.has_aload && !ff.has_srst && !ff.has_arst && !ff.has_sr) {
 				if (ff.has_clk && maybe_x(ff.sig_clk)) {
-					log_warning("Only non-x CLK inputs are currently supported for %s (%s)\n", cell, cell->type.unescape());
+					log_warning("Only non-x CLK inputs are currently supported for %s (%s)\n", cell, cell->type.unescaped());
 				} else {
 					auto init_q = ff.val_init;
 					auto init_q_is_1 = init_q;
@@ -907,15 +907,15 @@ struct XpropWorker
 					return;
 				}
 			} else {
-				log_warning("Unhandled FF-cell %s (%s), consider running clk2fflogic, async2sync and/or dffunmap\n", cell, cell->type.unescape());
+				log_warning("Unhandled FF-cell %s (%s), consider running clk2fflogic, async2sync and/or dffunmap\n", cell, cell->type.unescaped());
 			}
 		}
 
 		// Celltypes where any input x bit makes the whole output x
 		if (cell->type.in(
-			ID($neg),
-			ID($le), ID($lt), ID($ge), ID($gt),
-			ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor)
+			TW($neg),
+			TW($le), TW($lt), TW($ge), TW($gt),
+			TW($add), TW($sub), TW($mul), TW($div), TW($mod), TW($divfloor), TW($modfloor)
 		)) {
 
 			SigSpec inbits_x;
@@ -927,7 +927,7 @@ struct XpropWorker
 				}
 			}
 
-			if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
+			if (cell->type.in(TW($div), TW($mod), TW($divfloor), TW($modfloor))) {
 				auto sig_b = cell->getPort(TW::B);
 				auto invalid = module->LogicNot(NEW_TWINE, sig_b);
 				inbits_x.append(invalid);
@@ -937,7 +937,7 @@ struct XpropWorker
 
 			SigBit outbits_x = (GetSize(inbits_x) == 1 ? inbits_x : module->ReduceOr(NEW_TWINE, inbits_x));
 
-			bool bool_out = cell->type.in(ID($le), ID($lt), ID($ge), ID($gt));
+			bool bool_out = cell->type.in(TW($le), TW($lt), TW($ge), TW($gt));
 
 			for (auto &conn : cell->connections()) {
 				if (cell->output(conn.first)) {
@@ -958,15 +958,15 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type == ID($bmux)) // TODO might want to support bmux natively anyway
+		if (cell->type == TW($bmux)) // TODO might want to support bmux natively anyway
 			log("Running 'bmuxmap' preserves x-propagation and can be run before 'xprop'.\n");
-		if (cell->type == ID($demux)) // TODO might want to support demux natively anyway
+		if (cell->type == TW($demux)) // TODO might want to support demux natively anyway
 			log("Running 'demuxmap' preserves x-propagation and can be run before 'xprop'.\n");
 
 		if (options.required)
-			log_error("Unhandled cell %s (%s)\n", cell, cell->type.unescape());
+			log_error("Unhandled cell %s (%s)\n", cell, cell->type.unescaped());
 		else
-			log_warning("Unhandled cell %s (%s)\n", cell, cell->type.unescape());
+			log_warning("Unhandled cell %s (%s)\n", cell, cell->type.unescaped());
 	}
 
 	void split_ports()