mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-18 05:05:45 +00:00
WIP
This commit is contained in:
Emil J. Tywoniak
parent
afdae7b87e
commit
c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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@ -50,7 +50,7 @@ OBJS += passes/cmds/xprop.o
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OBJS += passes/cmds/dft_tag.o
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OBJS += passes/cmds/future.o
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OBJS += passes/cmds/box_derive.o
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OBJS += passes/cmds/example_dt.o
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#OBJS += passes/cmds/example_dt.o
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OBJS += passes/cmds/portarcs.o
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OBJS += passes/cmds/wrapcell.o
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OBJS += passes/cmds/setenv.o
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@ -174,7 +174,7 @@ unsigned int abstract_state(Module* mod, EnableLogic enable, const std::vector<S
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std::vector<FfData> ffs;
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// Abstract flop inputs if they're driving a selected output rep
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for (auto cell : mod->cells()) {
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if (!ct.cell_types.count(cell->type))
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if (!ct.cell_types.count(cell->type_impl))
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continue;
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FfData ff(nullptr, cell);
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if (ff.has_sr)
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@ -265,7 +265,7 @@ unsigned int abstract_value(Module* mod, EnableLogic enable, const std::vector<S
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unsigned int changed = 0;
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std::vector<Cell*> cells_snapshot = mod->cells();
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for (auto cell : cells_snapshot) {
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if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
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if (cell->type.in(TW($input_port), TW($output_port), TW($public)))
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continue;
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for (auto conn : cell->connections())
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if (cell->output(conn.first)) {
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@ -42,7 +42,8 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const
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log_error("Could not find wire with name \"%s\".\n", name);
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}
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else {
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RTLIL::Cell *formal_cell = module->addCell(NEW_TWINE, "$" + celltype);
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TwineRef _type = module->design->twines.add(Twine{"$" + celltype});
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RTLIL::Cell *formal_cell = module->addCell(NEW_TWINE, _type);
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formal_cell->setPort(TW::A, wire);
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if(enable_name == "") {
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formal_cell->setPort(TW::EN, State::S1);
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@ -100,7 +100,7 @@ struct BoxDerivePass : Pass {
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continue;
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if (!done.count(index)) {
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IdString derived_type = base->derive(d, cell->parameters);
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TwineRef derived_type = base->derive(d, cell->parameters);
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Module *derived = d->module(derived_type);
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log_assert(derived && "Failed to derive module\n");
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log("derived %s\n", derived_type);
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@ -87,7 +87,7 @@ int check_bufnorm_wire(RTLIL::Module *module, RTLIL::Wire *wire)
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if (!dsig.is_wire() || dsig.as_wire() != wire)
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log_warning("bufNorm: wire %s.%s driverCell_ %s port %s does not connect back to this wire\n",
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log_id(module), log_id(wire), log_id(driver), module->design->twines.str(dport).c_str()), counter++;
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if (wire->port_input && !wire->port_output && driver->type != ID($input_port))
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if (wire->port_input && !wire->port_output && driver->type != TW($input_port))
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log_warning("bufNorm: module input wire %s.%s is driven by non-$input_port cell %s of type %s\n",
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log_id(module), log_id(wire), log_id(driver), log_id(driver->type)), counter++;
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}
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@ -295,14 +295,14 @@ struct CheckPass : public Pass {
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// Only those cell types for which the edge data can expode quadratically
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// in port widths are those for us to check.
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if (!cell->type.in(
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ID($add), ID($sub),
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ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),
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ID($pmux), ID($bmux)))
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TW($add), TW($sub),
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TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx),
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TW($pmux), TW($bmux)))
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return false;
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int in_widths = 0, out_widths = 0;
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if (cell->type.in(ID($pmux), ID($bmux))) {
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if (cell->type.in(TW($pmux), TW($bmux))) {
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// We're skipping inputs A and B, since each of their bits contributes only one edge
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in_widths = GetSize(cell->getPort(TW::S));
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out_widths = GetSize(cell->getPort(TW::Y));
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@ -358,17 +358,17 @@ struct CheckPass : public Pass {
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pool<Cell *> coarsened_cells;
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for (auto cell : module->cells())
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{
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if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
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if (cell->type.in(TW($input_port), TW($output_port), TW($public)))
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continue;
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if (mapped && cell->type.begins_with("$") && design->module(cell->type) == nullptr) {
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if (allow_tbuf && cell->type == ID($_TBUF_)) goto cell_allowed;
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log_warning("Cell %s.%s is an unmapped internal cell of type %s.\n", module, cell, cell->type.unescape());
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if (allow_tbuf && cell->type == TW($_TBUF_)) goto cell_allowed;
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log_warning("Cell %s.%s is an unmapped internal cell of type %s.\n", module, cell, cell->type.unescaped());
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counter++;
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cell_allowed:;
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}
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if (cell->type == ID($connect)) {
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if (cell->type == TW($connect)) {
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// Inefficient, but rare case in sane design
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auto sig_a = cell->getPort(TW::A);
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auto sig_b = cell->getPort(TW::B);
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@ -406,13 +406,13 @@ struct CheckPass : public Pass {
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wire_drivers_count[bit]++;
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if (output && (bit.wire || !input))
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wire_drivers[bit].push_back(stringf("port %s[%d] of cell %s (%s)", cell->module->design->twines.str(conn.first).c_str(), i,
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cell, cell->type.unescape()));
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cell, cell->type.unescaped()));
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if (output)
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driver_cells[bit] = cell;
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}
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}
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if (yosys_celltypes.cell_evaluable(cell->type) || cell->type.in(ID($mem_v2), ID($memrd), ID($memrd_v2)) \
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if (yosys_celltypes.cell_evaluable(cell->type.ref()) || cell->type.in(TW($mem_v2), TW($memrd), TW($memrd_v2)) \
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|| cell->is_builtin_ff()) {
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if (!edges_db.add_edges_from_cell(cell))
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coarsened_cells.insert(cell);
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@ -529,7 +529,7 @@ struct CheckPass : public Pass {
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driver_src = stringf(" source: %s", src_attr);
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}
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message += stringf(" cell %s (%s)%s\n", driver, driver->type.unescape(), driver_src);
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message += stringf(" cell %s (%s)%s\n", driver, design->twines.unescaped_str(driver->type), driver_src);
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if (!coarsened_cells.count(driver)) {
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MatchingEdgePrinter printer(message, sigmap, prev, bit);
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@ -24,42 +24,42 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static RTLIL::IdString formal_flavor(RTLIL::Cell *cell)
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static TwineRef formal_flavor(RTLIL::Cell *cell)
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{
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if (cell->type != ID($check))
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return cell->type;
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if (cell->type != TW($check))
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return cell->type_impl;
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std::string flavor_param = cell->getParam(ID(FLAVOR)).decode_string();
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if (flavor_param == "assert")
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return ID($assert);
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return TW($assert);
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else if (flavor_param == "assume")
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return ID($assume);
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return TW($assume);
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else if (flavor_param == "cover")
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return ID($cover);
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return TW($cover);
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else if (flavor_param == "live")
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return ID($live);
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return TW($live);
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else if (flavor_param == "fair")
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return ID($fair);
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return TW($fair);
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else
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log_abort();
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}
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static void set_formal_flavor(RTLIL::Cell *cell, RTLIL::IdString flavor)
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static void set_formal_flavor(RTLIL::Cell *cell, TwineRef flavor)
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{
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if (cell->type != ID($check)) {
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cell->type_impl = cell->module->design->twines.add(Twine{flavor.str()});
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if (cell->type != TW($check)) {
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cell->type_impl = flavor;
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return;
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}
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if (flavor == ID($assert))
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if (flavor == TW($assert))
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cell->setParam(ID(FLAVOR), std::string("assert"));
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else if (flavor == ID($assume))
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else if (flavor == TW($assume))
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cell->setParam(ID(FLAVOR), std::string("assume"));
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else if (flavor == ID($cover))
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else if (flavor == TW($cover))
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cell->setParam(ID(FLAVOR), std::string("cover"));
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else if (flavor == ID($live))
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else if (flavor == TW($live))
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cell->setParam(ID(FLAVOR), std::string("live"));
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else if (flavor == ID($fair))
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else if (flavor == TW($fair))
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cell->setParam(ID(FLAVOR), std::string("fair"));
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else
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log_abort();
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@ -67,7 +67,7 @@ static void set_formal_flavor(RTLIL::Cell *cell, RTLIL::IdString flavor)
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static bool is_triggered_check_cell(RTLIL::Cell * cell)
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{
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return cell->type == ID($check) && cell->getParam(ID(TRG_ENABLE)).as_bool();
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return cell->type == TW($check) && cell->getParam(ID(TRG_ENABLE)).as_bool();
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}
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struct ChformalPass : public Pass {
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@ -136,7 +136,7 @@ struct ChformalPass : public Pass {
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bool live2fair = false;
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bool fair2live = false;
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pool<IdString> constr_types;
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pool<TwineRef> constr_types;
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char mode = 0;
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int mode_arg = 0;
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@ -144,23 +144,23 @@ struct ChformalPass : public Pass {
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-assert") {
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constr_types.insert(ID($assert));
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constr_types.insert(TW($assert));
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continue;
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}
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if (args[argidx] == "-assume") {
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constr_types.insert(ID($assume));
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constr_types.insert(TW($assume));
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continue;
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}
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if (args[argidx] == "-live") {
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constr_types.insert(ID($live));
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constr_types.insert(TW($live));
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continue;
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}
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if (args[argidx] == "-fair") {
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constr_types.insert(ID($fair));
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constr_types.insert(TW($fair));
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continue;
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}
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if (args[argidx] == "-cover") {
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constr_types.insert(ID($cover));
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constr_types.insert(TW($cover));
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continue;
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}
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if (mode == 0 && args[argidx] == "-remove") {
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@ -222,11 +222,11 @@ struct ChformalPass : public Pass {
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design->sigNormalize(false);
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if (constr_types.empty()) {
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constr_types.insert(ID($assert));
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constr_types.insert(ID($assume));
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constr_types.insert(ID($live));
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constr_types.insert(ID($fair));
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constr_types.insert(ID($cover));
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constr_types.insert(TW($assert));
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constr_types.insert(TW($assume));
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constr_types.insert(TW($live));
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constr_types.insert(TW($fair));
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constr_types.insert(TW($cover));
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}
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if (assert2assume && assert2cover) {
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@ -274,13 +274,13 @@ struct ChformalPass : public Pass {
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for (auto cell : module->selected_cells())
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{
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if (cell->type == ID($ff)) {
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if (cell->type == TW($ff)) {
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SigSpec D = sigmap(cell->getPort(TW::D));
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SigSpec Q = sigmap(cell->getPort(TW::Q));
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for (int i = 0; i < GetSize(D); i++)
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ffmap[Q[i]] = make_pair(D[i], make_pair(State::Sm, false));
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}
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if (cell->type == ID($dff)) {
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if (cell->type == TW($dff)) {
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SigSpec D = sigmap(cell->getPort(TW::D));
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SigSpec Q = sigmap(cell->getPort(TW::Q));
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SigSpec C = sigmap(cell->getPort(TW::CLK));
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@ -301,7 +301,7 @@ struct ChformalPass : public Pass {
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cell->setParam(ID::TRG_POLARITY, false);
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}
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IdString flavor = formal_flavor(cell);
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TwineRef flavor = formal_flavor(cell);
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while (true)
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{
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@ -312,8 +312,8 @@ struct ChformalPass : public Pass {
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break;
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if (!init_zero.count(EN)) {
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if (flavor == ID($cover)) break;
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if (flavor.in(ID($assert), ID($assume)) && !init_one.count(A)) break;
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if (flavor == TW($cover)) break;
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if (flavor.in(TW($assert), TW($assume)) && !init_one.count(A)) break;
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}
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const auto &A_map = ffmap.at(A);
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@ -372,8 +372,8 @@ struct ChformalPass : public Pass {
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{
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for (auto cell : constr_cells)
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{
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if (cell->type == ID($check)) {
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Cell *cover = module->addCell(NEW_TWINE_SUFFIX("coverenable"), ID($check));
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if (cell->type == TW($check)) {
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Cell *cover = module->addCell(NEW_TWINE_SUFFIX("coverenable"), TW::$check);
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cover->attributes = cell->attributes;
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if (cell->src_id() != Twine::Null && module->design)
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cover->set_src_id(cell->src_id());
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@ -395,24 +395,24 @@ struct ChformalPass : public Pass {
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if (mode == 'c')
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{
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for (auto cell : constr_cells) {
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IdString flavor = formal_flavor(cell);
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if (assert2assume && flavor == ID($assert))
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set_formal_flavor(cell, ID($assume));
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if (assert2cover && flavor == ID($assert))
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set_formal_flavor(cell, ID($cover));
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else if (assume2assert && flavor == ID($assume))
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set_formal_flavor(cell, ID($assert));
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else if (live2fair && flavor == ID($live))
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set_formal_flavor(cell, ID($fair));
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else if (fair2live && flavor == ID($fair))
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set_formal_flavor(cell, ID($live));
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TwineRef flavor = formal_flavor(cell);
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if (assert2assume && flavor == TW($assert))
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set_formal_flavor(cell, TW($assume));
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if (assert2cover && flavor == TW($assert))
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set_formal_flavor(cell, TW($cover));
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else if (assume2assert && flavor == TW($assume))
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set_formal_flavor(cell, TW($assert));
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else if (live2fair && flavor == TW($live))
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set_formal_flavor(cell, TW($fair));
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else if (fair2live && flavor == TW($fair))
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set_formal_flavor(cell, TW($live));
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}
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}
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else
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if (mode == 'l')
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{
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for (auto cell : constr_cells) {
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if (cell->type != ID($check))
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if (cell->type != TW($check))
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continue;
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if (is_triggered_check_cell(cell))
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@ -431,7 +431,7 @@ struct ChformalPass : public Pass {
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plain_cell->setPort(TW::A, sig_a);
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plain_cell->setPort(TW::EN, sig_en);
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if (plain_cell->type.in(ID($assert), ID($assume)))
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if (plain_cell->type.in(TW($assert), TW($assume)))
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sig_a = module->Not(NEW_TWINE, sig_a);
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SigBit combined_en = module->And(NEW_TWINE, sig_a, sig_en);
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@ -66,7 +66,7 @@ struct CleanZeroWidthPass : public Pass {
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{
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for (auto cell : module->selected_cells())
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{
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if (!ct.cell_known(cell->type)) {
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if (!ct.cell_known(cell->type_impl)) {
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// User-defined cell: just prune zero-width connections.
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for (auto it: cell->connections()) {
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if (GetSize(it.second) == 0) {
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@ -80,7 +80,7 @@ struct CleanZeroWidthPass : public Pass {
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if (GetSize(cell->getPort(TW::Q)) == 0) {
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module->remove(cell);
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}
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} else if (cell->type.in(ID($pmux), ID($bmux), ID($demux))) {
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} else if (cell->type.in(TW($pmux), TW($bmux), TW($demux))) {
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// Remove altogether if WIDTH is 0, replace with
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// a connection if S_WIDTH is 0.
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if (cell->getParam(ID::WIDTH).as_int() == 0) {
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@ -90,7 +90,7 @@ struct CleanZeroWidthPass : public Pass {
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module->connect(cell->getPort(TW::Y), cell->getPort(TW::A));
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module->remove(cell);
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}
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} else if (cell->type == ID($concat)) {
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} else if (cell->type == TW($concat)) {
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// If a concat has a zero-width input: replace with direct
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// connection to the other input.
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if (cell->getParam(ID::A_WIDTH).as_int() == 0) {
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@ -100,17 +100,17 @@ struct CleanZeroWidthPass : public Pass {
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module->connect(cell->getPort(TW::Y), cell->getPort(TW::A));
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module->remove(cell);
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}
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} else if (cell->type == ID($fsm)) {
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} else if (cell->type == TW($fsm)) {
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// TODO: not supported
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} else if (cell->is_mem_cell()) {
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// Skip — will be handled below.
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} else if (cell->type == ID($lut)) {
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} else if (cell->type == TW($lut)) {
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// Zero-width LUT is just a const driver.
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if (cell->getParam(ID::WIDTH).as_int() == 0) {
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module->connect(cell->getPort(TW::Y), cell->getParam(ID::LUT)[0]);
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module->remove(cell);
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||||
}
|
||||
} else if (cell->type == ID($sop)) {
|
||||
} else if (cell->type == TW($sop)) {
|
||||
// Zero-width SOP is just a const driver.
|
||||
if (cell->getParam(ID::WIDTH).as_int() == 0) {
|
||||
// The value is 1 iff DEPTH is non-0.
|
||||
|
|
@ -128,7 +128,7 @@ struct CleanZeroWidthPass : public Pass {
|
|||
// A and B to 1-bit if their width is 0.
|
||||
if (cell->getParam(ID::Y_WIDTH).as_int() == 0) {
|
||||
module->remove(cell);
|
||||
} else if (cell->type.in(ID($macc), ID($macc_v2))) {
|
||||
} else if (cell->type.in(TW($macc), TW($macc_v2))) {
|
||||
// TODO: fixing zero-width A and B not supported.
|
||||
} else {
|
||||
if (cell->getParam(ID::A_WIDTH).as_int() == 0) {
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
|
|||
|
||||
for (auto cell : module->cells())
|
||||
for (auto &port : cell->connections_)
|
||||
if (ct.cell_output(cell->type, port.first))
|
||||
if (ct.cell_output(cell->type.ref(), port.first))
|
||||
sigmap(port.second).replace(sig, dummy_wire, &port.second);
|
||||
|
||||
bool need_fixup = false;
|
||||
|
|
|
|||
|
|
@ -268,7 +268,7 @@ struct DesignPass : public Pass {
|
|||
{
|
||||
log("Importing %s as %s.\n", mod, RTLIL::unescape_id(prefix));
|
||||
|
||||
RTLIL::Module *t = mod->clone(copy_to_design, RTLIL::IdString(prefix));
|
||||
RTLIL::Module *t = mod->clone(copy_to_design, copy_to_design->twines.add(Twine{prefix}));
|
||||
t->attributes.erase(ID::top);
|
||||
|
||||
queue.insert(t);
|
||||
|
|
@ -297,7 +297,7 @@ struct DesignPass : public Pass {
|
|||
if (copy_to_design->module(trg_name) != nullptr)
|
||||
copy_to_design->remove(copy_to_design->module(trg_name));
|
||||
|
||||
RTLIL::Module *t = fmod->clone(copy_to_design, RTLIL::IdString(trg_name));
|
||||
RTLIL::Module *t = fmod->clone(copy_to_design, copy_to_design->twines.add(Twine{trg_name}));
|
||||
t->attributes.erase(ID::top);
|
||||
|
||||
queue.insert(t);
|
||||
|
|
@ -321,7 +321,7 @@ struct DesignPass : public Pass {
|
|||
if (copy_to_design->module(trg_name) != nullptr)
|
||||
copy_to_design->remove(copy_to_design->module(trg_name));
|
||||
|
||||
mod->clone(copy_to_design, RTLIL::IdString(trg_name));
|
||||
mod->clone(copy_to_design, copy_to_design->twines.add(Twine{trg_name}));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -90,10 +90,10 @@ struct DftTagWorker {
|
|||
bool design_changed = false;
|
||||
|
||||
for (auto cell : module->cells()) {
|
||||
if (cell->type == ID($overwrite_tag))
|
||||
if (cell->type == TW($overwrite_tag))
|
||||
overwrite_cells.push_back(cell);
|
||||
|
||||
if (cell->type == ID($original_tag))
|
||||
if (cell->type == TW($original_tag))
|
||||
original_cells.push_back(cell);
|
||||
}
|
||||
|
||||
|
|
@ -137,7 +137,7 @@ struct DftTagWorker {
|
|||
if (found == modwalker.signal_consumers.end())
|
||||
return;
|
||||
for (auto &consumer : found->second) {
|
||||
if (consumer.cell->type.in(ID($original_tag)))
|
||||
if (consumer.cell->type.in(TW($original_tag)))
|
||||
continue;
|
||||
if (sigmap(consumer.cell->getPort(consumer.port)[consumer.offset]) != driver_bit)
|
||||
continue;
|
||||
|
|
@ -249,7 +249,7 @@ struct DftTagWorker {
|
|||
void propagate_tags()
|
||||
{
|
||||
for (auto cell : module->cells()) {
|
||||
if (cell->type == ID($set_tag)) {
|
||||
if (cell->type == TW($set_tag)) {
|
||||
pending_cells.insert(cell);
|
||||
pending_cell_queue.push_back(cell);
|
||||
}
|
||||
|
|
@ -371,7 +371,7 @@ struct DftTagWorker {
|
|||
|
||||
void propagate_tags(Cell *cell)
|
||||
{
|
||||
if (cell->type == ID($set_tag)) {
|
||||
if (cell->type == TW($set_tag)) {
|
||||
IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string());
|
||||
if (all_tags.insert(tag).second) {
|
||||
auto group_sep = tag.str().find(':');
|
||||
|
|
@ -388,25 +388,25 @@ struct DftTagWorker {
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type == ID($get_tag)) {
|
||||
if (cell->type == TW($get_tag)) {
|
||||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($not), ID($pos))) {
|
||||
if (cell->type.in(TW($not), TW($pos))) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto sig_a = cell->getPort(TW::A);
|
||||
if (cell->type.in(ID($not), ID($or))) {
|
||||
if (cell->type.in(TW($not), TW($or))) {
|
||||
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
|
||||
}
|
||||
forward_tags(sig_y, sig_a);
|
||||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($bweqx))) {
|
||||
if (cell->type.in(TW($and), TW($or), TW($xor), TW($xnor), TW($bweqx))) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto sig_a = cell->getPort(TW::A);
|
||||
auto sig_b = cell->getPort(TW::B);
|
||||
if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
|
||||
if (cell->type.in(TW($and), TW($or), TW($xor), TW($xnor))) {
|
||||
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
|
||||
sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
|
||||
}
|
||||
|
|
@ -415,13 +415,13 @@ struct DftTagWorker {
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($mux), ID($bwmux))) {
|
||||
if (cell->type.in(TW($mux), TW($bwmux))) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto &sig_a = cell->getPort(TW::A);
|
||||
auto &sig_b = cell->getPort(TW::B);
|
||||
auto sig_s = cell->getPort(TW::S);
|
||||
|
||||
if (cell->type == ID($mux))
|
||||
if (cell->type == TW($mux))
|
||||
sig_s = SigSpec(sig_s[0], GetSize(sig_y));
|
||||
|
||||
forward_tags(sig_y, sig_a);
|
||||
|
|
@ -430,7 +430,7 @@ struct DftTagWorker {
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->is_builtin_ff() || cell->type == ID($anyinit)) {
|
||||
if (cell->is_builtin_ff() || cell->type == TW($anyinit)) {
|
||||
FfData ff(&initvals, cell);
|
||||
|
||||
if (ff.has_clk || ff.has_gclk)
|
||||
|
|
@ -440,10 +440,10 @@ struct DftTagWorker {
|
|||
|
||||
// Single output but, sensitive to all inputs
|
||||
if (cell->type.in(
|
||||
ID($le), ID($lt), ID($ge), ID($gt),
|
||||
ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor),
|
||||
ID($reduce_bool), ID($logic_not), ID($logic_or), ID($logic_and),
|
||||
ID($eq), ID($ne)
|
||||
TW($le), TW($lt), TW($ge), TW($gt),
|
||||
TW($reduce_and), TW($reduce_or), TW($reduce_xor), TW($reduce_xnor),
|
||||
TW($reduce_bool), TW($logic_not), TW($logic_or), TW($logic_and),
|
||||
TW($eq), TW($ne)
|
||||
)) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
|
||||
|
|
@ -456,10 +456,10 @@ struct DftTagWorker {
|
|||
add_tags(cell, tags(cell));
|
||||
|
||||
if (cell->type.in(
|
||||
ID($_AND_), ID($_OR_), ID($_NAND_), ID($_NOR_), ID($_ANDNOT_), ID($_ORNOT_),
|
||||
ID($_XOR_), ID($_XNOR_), ID($_NOT_), ID($_BUF_), ID($_MUX_),
|
||||
TW($_AND_), TW($_OR_), TW($_NAND_), TW($_NOR_), TW($_ANDNOT_), TW($_ORNOT_),
|
||||
TW($_XOR_), TW($_XNOR_), TW($_NOT_), TW($_BUF_), TW($_MUX_),
|
||||
|
||||
ID($assert), ID($assume)
|
||||
TW($assert), TW($assume)
|
||||
)) {
|
||||
return;
|
||||
}
|
||||
|
|
@ -477,7 +477,7 @@ struct DftTagWorker {
|
|||
|
||||
void process_cell(IdString tag, Cell *cell)
|
||||
{
|
||||
if (cell->type == ID($set_tag)) {
|
||||
if (cell->type == TW($set_tag)) {
|
||||
IdString cell_tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string());
|
||||
|
||||
auto tag_sig_a = tag_signal(tag, cell->getPort(TW::A));
|
||||
|
|
@ -494,14 +494,14 @@ struct DftTagWorker {
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type == ID($get_tag)) {
|
||||
if (cell->type == TW($get_tag)) {
|
||||
log_assert(false);
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($not), ID($pos), ID($_NOT_), ID($_BUF_))) {
|
||||
if (cell->type.in(TW($not), TW($pos), TW($_NOT_), TW($_BUF_))) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto sig_a = cell->getPort(TW::A);
|
||||
if (cell->type.in(ID($not), ID($or))) {
|
||||
if (cell->type.in(TW($not), TW($or))) {
|
||||
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
|
||||
}
|
||||
emit_tag_signal(tag, sig_y, tag_signal(tag, sig_a));
|
||||
|
|
@ -509,13 +509,13 @@ struct DftTagWorker {
|
|||
}
|
||||
|
||||
if (cell->type.in(
|
||||
ID($and), ID($or),
|
||||
ID($_AND_), ID($_OR_), ID($_NAND_), ID($_NOR_), ID($_ANDNOT_), ID($_ORNOT_)
|
||||
TW($and), TW($or),
|
||||
TW($_AND_), TW($_OR_), TW($_NAND_), TW($_NOR_), TW($_ANDNOT_), TW($_ORNOT_)
|
||||
)) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto sig_a = cell->getPort(TW::A);
|
||||
auto sig_b = cell->getPort(TW::B);
|
||||
if (cell->type.in(ID($and), ID($or))) {
|
||||
if (cell->type.in(TW($and), TW($or))) {
|
||||
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
|
||||
sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
|
||||
}
|
||||
|
|
@ -523,9 +523,9 @@ struct DftTagWorker {
|
|||
bool inv_a = false;
|
||||
bool inv_b = false;
|
||||
|
||||
if (cell->type.in(ID($or), ID($_OR_), ID($_NOR_), ID($_ORNOT_)))
|
||||
if (cell->type.in(TW($or), TW($_OR_), TW($_NOR_), TW($_ORNOT_)))
|
||||
inv_a ^= true, inv_b ^= true;
|
||||
if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
|
||||
if (cell->type.in(TW($_ANDNOT_), TW($_ORNOT_)))
|
||||
inv_b ^= true;
|
||||
|
||||
if (inv_a)
|
||||
|
|
@ -554,11 +554,11 @@ struct DftTagWorker {
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($xor), ID($xnor), ID($bweqx), ID($_XOR_), ID($_XNOR_))) {
|
||||
if (cell->type.in(TW($xor), TW($xnor), TW($bweqx), TW($_XOR_), TW($_XNOR_))) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto sig_a = cell->getPort(TW::A);
|
||||
auto sig_b = cell->getPort(TW::B);
|
||||
if (cell->type.in(ID($xor), ID($xnor))) {
|
||||
if (cell->type.in(TW($xor), TW($xnor))) {
|
||||
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
|
||||
sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
|
||||
}
|
||||
|
|
@ -572,13 +572,13 @@ struct DftTagWorker {
|
|||
}
|
||||
|
||||
|
||||
if (cell->type.in(ID($_MUX_), ID($mux), ID($bwmux))) {
|
||||
if (cell->type.in(TW($_MUX_), TW($mux), TW($bwmux))) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto &sig_a = cell->getPort(TW::A);
|
||||
auto &sig_b = cell->getPort(TW::B);
|
||||
auto sig_s = cell->getPort(TW::S);
|
||||
|
||||
if (cell->type == ID($mux))
|
||||
if (cell->type == TW($mux))
|
||||
sig_s = SigSpec(sig_s[0], GetSize(sig_y));
|
||||
|
||||
auto group_sig_a = tag_group_signal(tag, sig_a);
|
||||
|
|
@ -606,7 +606,7 @@ struct DftTagWorker {
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex))) {
|
||||
if (cell->type.in(TW($eq), TW($ne), TW($eqx), TW($nex))) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto sig_a = cell->getPort(TW::A);
|
||||
auto sig_b = cell->getPort(TW::B);
|
||||
|
|
@ -635,7 +635,7 @@ struct DftTagWorker {
|
|||
}
|
||||
|
||||
|
||||
if (cell->type.in(ID($lt), ID($gt), ID($le), ID($ge))) {
|
||||
if (cell->type.in(TW($lt), TW($gt), TW($le), TW($ge))) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto sig_a = cell->getPort(TW::A);
|
||||
auto sig_b = cell->getPort(TW::B);
|
||||
|
|
@ -643,7 +643,7 @@ struct DftTagWorker {
|
|||
sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool());
|
||||
sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool());
|
||||
|
||||
if (cell->type.in(ID($gt), ID($le)))
|
||||
if (cell->type.in(TW($gt), TW($le)))
|
||||
std::swap(sig_a, sig_b);
|
||||
|
||||
auto group_sig_a = tag_group_signal(tag, sig_a);
|
||||
|
|
@ -666,14 +666,14 @@ struct DftTagWorker {
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($logic_not))) {
|
||||
if (cell->type.in(TW($reduce_and), TW($reduce_or), TW($reduce_bool), TW($logic_not))) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto sig_a = cell->getPort(TW::A);
|
||||
|
||||
auto group_sig_a = tag_group_signal(tag, sig_a);
|
||||
auto tag_sig_a = tag_signal(tag, sig_a);
|
||||
|
||||
if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not)))
|
||||
if (cell->type.in(TW($reduce_or), TW($reduce_bool), TW($logic_not)))
|
||||
sig_a = autoNot(NEW_TWINE, sig_a);
|
||||
|
||||
auto filled = autoOr(NEW_TWINE, sig_a, group_sig_a);
|
||||
|
|
@ -686,12 +686,12 @@ struct DftTagWorker {
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->is_builtin_ff() || cell->type == ID($anyinit)) {
|
||||
if (cell->is_builtin_ff() || cell->type == TW($anyinit)) {
|
||||
FfData ff(&initvals, cell);
|
||||
// TODO handle some more variants
|
||||
if ((ff.has_clk || ff.has_gclk) && !ff.has_ce && !ff.has_aload && !ff.has_srst && !ff.has_arst && !ff.has_sr) {
|
||||
if (ff.has_clk && !tags(ff.sig_clk).empty())
|
||||
log_warning("Tags on CLK input ignored for %s (%s)\n", cell, cell->type.unescape());
|
||||
log_warning("Tags on CLK input ignored for %s (%s)\n", cell, cell->type);
|
||||
|
||||
int width = ff.width;
|
||||
|
||||
|
|
@ -709,7 +709,7 @@ struct DftTagWorker {
|
|||
emit_tag_signal(tag, sig_q, ff.sig_q);
|
||||
return;
|
||||
} else {
|
||||
log_warning("Unhandled FF-cell %s (%s), consider running clk2fflogic, async2sync and/or dffunmap\n", cell, cell->type.unescape());
|
||||
log_warning("Unhandled FF-cell %s (%s), consider running clk2fflogic, async2sync and/or dffunmap\n", cell, cell->type);
|
||||
|
||||
// For unhandled FFs, the default propagation would cause combinational loops
|
||||
emit_tag_signal(tag, ff.sig_q, Const(0, ff.width));
|
||||
|
|
@ -739,7 +739,7 @@ struct DftTagWorker {
|
|||
// which is an over-approximation (unless the cell is a module that
|
||||
// generates tags itself in which case it could be arbitrary).
|
||||
if (warned_cells.insert(cell).second)
|
||||
log_warning("Unhandled cell %s (%s) while emitting tag signals\n", cell, cell->type.unescape());
|
||||
log_warning("Unhandled cell %s (%s) while emitting tag signals\n", cell, cell->type);
|
||||
}
|
||||
|
||||
void emit_tags()
|
||||
|
|
@ -747,7 +747,7 @@ struct DftTagWorker {
|
|||
warned_cells.clear();
|
||||
std::vector<Cell *> get_tag_cells;
|
||||
for (auto cell : module->selected_cells())
|
||||
if (cell->type == ID($get_tag))
|
||||
if (cell->type == TW($get_tag))
|
||||
get_tag_cells.push_back(cell);
|
||||
|
||||
for (auto cell : get_tag_cells) {
|
||||
|
|
@ -798,13 +798,13 @@ struct DftTagWorker {
|
|||
std::vector<Cell *> get_tag_cells;
|
||||
std::vector<Cell *> set_tag_cells;
|
||||
for (auto cell : module->cells()) {
|
||||
if (cell->type == ID($get_tag))
|
||||
if (cell->type == TW($get_tag))
|
||||
get_tag_cells.push_back(cell);
|
||||
|
||||
if (cell->type == ID($set_tag))
|
||||
if (cell->type == TW($set_tag))
|
||||
set_tag_cells.push_back(cell);
|
||||
|
||||
log_assert(!cell->type.in(ID($overwrite_tag), ID($original_tag)));
|
||||
log_assert(!cell->type.in(TW($overwrite_tag), TW($original_tag)));
|
||||
}
|
||||
|
||||
for (auto cell : set_tag_cells) {
|
||||
|
|
|
|||
|
|
@ -92,12 +92,12 @@ struct EdgetypePass : public Pass {
|
|||
auto sink_bit_index = std::get<2>(sink);
|
||||
|
||||
string source_str = multibit_ports.count(std::pair<IdString, TwineRef>(source_cell_type, source_port_name)) ?
|
||||
stringf("%s.%s[%d]", source_cell_type.unescape(), module->design->twines.str(source_port_name).c_str(), source_bit_index) :
|
||||
stringf("%s.%s", source_cell_type.unescape(), module->design->twines.str(source_port_name).c_str());
|
||||
stringf("%s.%s[%d]", design->twines.unescaped_str(source_cell_type), module->design->twines.str(source_port_name).c_str(), source_bit_index) :
|
||||
stringf("%s.%s", design->twines.unescaped_str(source_cell_type), module->design->twines.str(source_port_name).c_str());
|
||||
|
||||
string sink_str = multibit_ports.count(std::pair<IdString, TwineRef>(sink_cell_type, sink_port_name)) ?
|
||||
stringf("%s.%s[%d]", sink_cell_type.unescape(), module->design->twines.str(sink_port_name).c_str(), sink_bit_index) :
|
||||
stringf("%s.%s", sink_cell_type.unescape(), module->design->twines.str(sink_port_name).c_str());
|
||||
stringf("%s.%s[%d]", design->twines.unescaped_str(sink_cell_type), module->design->twines.str(sink_port_name).c_str(), sink_bit_index) :
|
||||
stringf("%s.%s", design->twines.unescaped_str(sink_cell_type), module->design->twines.str(sink_port_name).c_str());
|
||||
|
||||
edge_cache.insert(source_str + " " + sink_str);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -77,13 +77,13 @@ struct ExampleDtPass : public Pass
|
|||
auto enqueue = [&](DriveSpec const &spec) {
|
||||
int index = queue(spec);
|
||||
if (index == GetSize(graph_nodes))
|
||||
graph_nodes.emplace_back(compute_graph.add(ID($pending), index).index());
|
||||
graph_nodes.emplace_back(compute_graph.add(TW($pending), index).index());
|
||||
//if (index >= GetSize(graph_nodes))
|
||||
return compute_graph[graph_nodes[index]];
|
||||
};
|
||||
|
||||
for (auto cell : module->cells()) {
|
||||
if (cell->type.in(ID($assert), ID($assume), ID($cover), ID($check)))
|
||||
if (cell->type.in(TW($assert), TW($assume), TW($cover), TW($check)))
|
||||
enqueue(DriveBitMarker(cells(cell), 0));
|
||||
}
|
||||
|
||||
|
|
@ -99,7 +99,7 @@ struct ExampleDtPass : public Pass
|
|||
ExampleGraph::Ref node = compute_graph[i];
|
||||
|
||||
if (spec.chunks().size() > 1) {
|
||||
node.set_function(ID($$concat));
|
||||
node.set_function(TW($$concat));
|
||||
|
||||
for (auto const &chunk : spec.chunks()) {
|
||||
node.append_arg(enqueue(chunk));
|
||||
|
|
@ -111,39 +111,39 @@ struct ExampleDtPass : public Pass
|
|||
if (wire_chunk.is_whole()) {
|
||||
node.sparse_attr() = wire_chunk.wire->name;
|
||||
if (wire_chunk.wire->port_input) {
|
||||
node.set_function(ExampleFn(ID($$input), {{wire_chunk.wire->name, {}}}));
|
||||
node.set_function(ExampleFn(TW($$input), {{wire_chunk.wire->name, {}}}));
|
||||
} else {
|
||||
DriveSpec driver = dm(DriveSpec(wire_chunk));
|
||||
node.set_function(ID($$buf));
|
||||
node.set_function(TW($$buf));
|
||||
|
||||
node.append_arg(enqueue(driver));
|
||||
}
|
||||
} else {
|
||||
DriveChunkWire whole_wire(wire_chunk.wire, 0, wire_chunk.wire->width);
|
||||
node.set_function(ExampleFn(ID($$slice), {{ID(offset), wire_chunk.offset}, {ID(width), wire_chunk.width}}));
|
||||
node.set_function(ExampleFn(TW($$slice), {{ID(offset), wire_chunk.offset}, {ID(width), wire_chunk.width}}));
|
||||
node.append_arg(enqueue(whole_wire));
|
||||
}
|
||||
} else if (chunk.is_port()) {
|
||||
DriveChunkPort port_chunk = chunk.port();
|
||||
if (port_chunk.is_whole()) {
|
||||
if (dm.celltypes.cell_output(port_chunk.cell->type, port_chunk.port)) {
|
||||
if (port_chunk.cell->type.in(ID($dff), ID($ff)))
|
||||
if (dm.celltypes.cell_output(port_chunk.cell->type_impl, port_chunk.port)) {
|
||||
if (port_chunk.cell->type.in(TW($dff), TW($ff)))
|
||||
{
|
||||
Cell *cell = port_chunk.cell;
|
||||
node.set_function(ExampleFn(ID($$state), {{cell->name, {}}}));
|
||||
node.set_function(ExampleFn(TW($$state), {{cell->name, {}}}));
|
||||
for (auto const &conn : cell->connections()) {
|
||||
if (!dm.celltypes.cell_input(cell->type, conn.first))
|
||||
if (!dm.celltypes.cell_input(cell->type_impl, conn.first))
|
||||
continue;
|
||||
enqueue(DriveChunkPort(cell, conn)).assign_key(cell->name);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
node.set_function(ExampleFn(ID($$cell_output), {{RTLIL::escape_id(module->design->twines.str(port_chunk.port)), {}}}));
|
||||
node.set_function(ExampleFn(TW($$cell_output), {{RTLIL::escape_id(module->design->twines.str(port_chunk.port)), {}}}));
|
||||
node.append_arg(enqueue(DriveBitMarker(cells(port_chunk.cell), 0)));
|
||||
}
|
||||
} else {
|
||||
node.set_function(ID($$buf));
|
||||
node.set_function(TW($$buf));
|
||||
|
||||
DriveSpec driver = dm(DriveSpec(port_chunk));
|
||||
node.append_arg(enqueue(driver));
|
||||
|
|
@ -151,14 +151,14 @@ struct ExampleDtPass : public Pass
|
|||
|
||||
} else {
|
||||
DriveChunkPort whole_port(port_chunk.cell, port_chunk.port, 0, GetSize(port_chunk.cell->connections().at(port_chunk.port)));
|
||||
node.set_function(ExampleFn(ID($$slice), {{ID(offset), port_chunk.offset}}));
|
||||
node.set_function(ExampleFn(TW($$slice), {{ID(offset), port_chunk.offset}}));
|
||||
node.append_arg(enqueue(whole_port));
|
||||
}
|
||||
} else if (chunk.is_constant()) {
|
||||
node.set_function(ExampleFn(ID($$const), {{ID(value), chunk.constant()}}));
|
||||
node.set_function(ExampleFn(TW($$const), {{ID(value), chunk.constant()}}));
|
||||
|
||||
} else if (chunk.is_multiple()) {
|
||||
node.set_function(ID($$multi));
|
||||
node.set_function(TW($$multi));
|
||||
for (auto const &driver : chunk.multiple().multiple())
|
||||
node.append_arg(enqueue(driver));
|
||||
} else if (chunk.is_marker()) {
|
||||
|
|
@ -166,13 +166,13 @@ struct ExampleDtPass : public Pass
|
|||
|
||||
node.set_function(ExampleFn(cell->type, cell->parameters));
|
||||
for (auto const &conn : cell->connections()) {
|
||||
if (!dm.celltypes.cell_input(cell->type, conn.first))
|
||||
if (!dm.celltypes.cell_input(cell->type_impl, conn.first))
|
||||
continue;
|
||||
|
||||
node.append_arg(enqueue(DriveChunkPort(cell, conn)));
|
||||
}
|
||||
} else if (chunk.is_none()) {
|
||||
node.set_function(ID($$undriven));
|
||||
node.set_function(TW($$undriven));
|
||||
|
||||
} else {
|
||||
log_error("unhandled drivespec: %s\n", log_signal(chunk));
|
||||
|
|
@ -208,7 +208,7 @@ struct ExampleDtPass : public Pass
|
|||
|
||||
for (int i = 0; i < compute_graph.size(); ++i)
|
||||
{
|
||||
if (compute_graph[i].function().name == ID($$buf) && !compute_graph[i].has_sparse_attr() && compute_graph[i].arg(0).index() < i)
|
||||
if (compute_graph[i].function().name == TW($$buf) && !compute_graph[i].has_sparse_attr() && compute_graph[i].arg(0).index() < i)
|
||||
{
|
||||
|
||||
alias.push_back(alias[compute_graph[i].arg(0).index()]);
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ struct FutureWorker {
|
|||
|
||||
std::vector<Cell *> replaced_cells;
|
||||
for (auto cell : module->selected_cells()) {
|
||||
if (cell->type != ID($future_ff))
|
||||
if (cell->type != TW($future_ff))
|
||||
continue;
|
||||
|
||||
module->connect(cell->getPort(TW::Y), future_ff(cell->getPort(TW::A)));
|
||||
|
|
@ -92,7 +92,7 @@ struct FutureWorker {
|
|||
|
||||
if (!ff.has_clk && !ff.has_gclk)
|
||||
log_error("Driver for future_ff target signal %s has cell type %s, which is not clocked\n", log_signal(bit),
|
||||
driver.cell->type.unescape());
|
||||
driver.cell->type);
|
||||
|
||||
ff.unmap_ce_srst();
|
||||
|
||||
|
|
|
|||
|
|
@ -70,7 +70,7 @@ private:
|
|||
|
||||
void add_precise_GLIFT_logic(const RTLIL::Cell *cell, RTLIL::SigSpec &port_a, RTLIL::SigSpec &port_a_taint, RTLIL::SigSpec &port_b, RTLIL::SigSpec &port_b_taint, RTLIL::SigSpec &port_y_taint) {
|
||||
//AKA AN2_SH2 or OR2_SH2
|
||||
bool is_and = cell->type.in(ID($_AND_), ID($_NAND_));
|
||||
bool is_and = cell->type.in(TW($_AND_), TW($_NAND_));
|
||||
RTLIL::SigSpec n_port_a = module->LogicNot(Twine{cell->name.str() + "_t_1_1"}, port_a, false, cell->src_ref());
|
||||
RTLIL::SigSpec n_port_b = module->LogicNot(Twine{cell->name.str() + "_t_1_2"}, port_b, false, cell->src_ref());
|
||||
auto subexpr1 = module->And(Twine{cell->name.str() + "_t_1_3"}, is_and? port_a : n_port_a, port_b_taint, false, cell->src_ref());
|
||||
|
|
@ -82,7 +82,7 @@ private:
|
|||
|
||||
void add_imprecise_GLIFT_logic_1(const RTLIL::Cell *cell, RTLIL::SigSpec &port_a, RTLIL::SigSpec &port_a_taint, RTLIL::SigSpec &port_b, RTLIL::SigSpec &port_b_taint, RTLIL::SigSpec &port_y_taint) {
|
||||
//AKA AN2_SH3 or OR2_SH3
|
||||
bool is_and = cell->type.in(ID($_AND_), ID($_NAND_));
|
||||
bool is_and = cell->type.in(TW($_AND_), TW($_NAND_));
|
||||
RTLIL::SigSpec n_port_a = module->LogicNot(Twine{cell->name.str() + "_t_2_1"}, port_a, false, cell->src_ref());
|
||||
auto subexpr1 = module->And(Twine{cell->name.str() + "_t_2_2"}, is_and? port_b : n_port_a, is_and? port_a_taint : port_b_taint, false, cell->src_ref());
|
||||
module->addOr(Twine{cell->name.str() + "_t_2_3"}, is_and? port_b_taint : port_a_taint, subexpr1, port_y_taint, false, cell->src_ref());
|
||||
|
|
@ -90,7 +90,7 @@ private:
|
|||
|
||||
void add_imprecise_GLIFT_logic_2(const RTLIL::Cell *cell, RTLIL::SigSpec &port_a, RTLIL::SigSpec &port_a_taint, RTLIL::SigSpec &port_b, RTLIL::SigSpec &port_b_taint, RTLIL::SigSpec &port_y_taint) {
|
||||
//AKA AN2_SH4 or OR2_SH4
|
||||
bool is_and = cell->type.in(ID($_AND_), ID($_NAND_));
|
||||
bool is_and = cell->type.in(TW($_AND_), TW($_NAND_));
|
||||
RTLIL::SigSpec n_port_b = module->LogicNot(Twine{cell->name.str() + "_t_3_1"}, port_b, false, cell->src_ref());
|
||||
auto subexpr1 = module->And(Twine{cell->name.str() + "_t_3_2"}, is_and? port_a : n_port_b, is_and? port_b_taint : port_a_taint, false, cell->src_ref());
|
||||
module->addOr(Twine{cell->name.str() + "_t_3_3"}, is_and? port_a_taint : port_b_taint, subexpr1, port_y_taint, false, cell->src_ref());
|
||||
|
|
@ -150,13 +150,13 @@ private:
|
|||
auto select_width = metamux_select.as_wire()->width;
|
||||
|
||||
std::vector<RTLIL::Const> costs;
|
||||
if (celltype == ID($_AND_) || celltype == ID($_OR_)) {
|
||||
if (celltype == TW($_AND_) || celltype == TW($_OR_)) {
|
||||
costs = {5, 2, 2, 1, 0, 0, 0, 0};
|
||||
log_assert(select_width == 2 || select_width == 3);
|
||||
log_assert(opt_instrumentmore || select_width == 2);
|
||||
log_assert(!opt_instrumentmore || select_width == 3);
|
||||
}
|
||||
else if (celltype == ID($_XOR_) || celltype == ID($_XNOR_)) {
|
||||
else if (celltype == TW($_XOR_) || celltype == TW($_XNOR_)) {
|
||||
costs = {1, 0, 0, 0};
|
||||
log_assert(select_width == 2);
|
||||
}
|
||||
|
|
@ -184,10 +184,10 @@ private:
|
|||
std::vector<RTLIL::SigSig> connections(module->connections());
|
||||
|
||||
for(auto &cell : module->cells().to_vector()) {
|
||||
if (!cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_MUX_), ID($_NMUX_), ID($_NOT_), ID($anyconst), ID($allconst), ID($assume), ID($assert)) && module->design->module(cell->type) == nullptr) {
|
||||
if (!cell->type.in(TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_), TW($_XOR_), TW($_XNOR_), TW($_MUX_), TW($_NMUX_), TW($_NOT_), TW($anyconst), TW($allconst), TW($assume), TW($assert)) && module->design->module(cell->type) == nullptr) {
|
||||
log_cmd_error("Unsupported cell type \"%s\" found. Run `techmap` first.\n", cell->type);
|
||||
}
|
||||
if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_))) {
|
||||
if (cell->type.in(TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_))) {
|
||||
const unsigned int A = 0, B = 1, Y = 2;
|
||||
const unsigned int NUM_PORTS = 3;
|
||||
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::B), cell->getPort(TW::Y)};
|
||||
|
|
@ -234,7 +234,7 @@ private:
|
|||
auto select_width = log2(num_versions);
|
||||
log_assert(exp2(select_width) == num_versions);
|
||||
RTLIL::SigSpec meta_mux_select(module->addWire(Twine{cell->name.str() + "_sel"}, select_width));
|
||||
meta_mux_selects.push_back(make_pair(meta_mux_select, cell->type));
|
||||
meta_mux_selects.push_back(make_pair(meta_mux_select, RTLIL::IdString(cell->type)));
|
||||
module->connect(meta_mux_select, module->Anyconst(module->design->twines.add(Twine{cell->name.str() + "_hole"}), select_width, cell->src_ref()));
|
||||
|
||||
std::vector<RTLIL::SigSpec> next_meta_mux_y_ports, meta_mux_y_ports(taint_version);
|
||||
|
|
@ -252,7 +252,7 @@ private:
|
|||
}
|
||||
else log_cmd_error("This is a bug (1).\n");
|
||||
}
|
||||
else if (cell->type.in(ID($_XOR_), ID($_XNOR_))) {
|
||||
else if (cell->type.in(TW($_XOR_), TW($_XNOR_))) {
|
||||
const unsigned int A = 0, B = 1, Y = 2;
|
||||
const unsigned int NUM_PORTS = 3;
|
||||
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::B), cell->getPort(TW::Y)};
|
||||
|
|
@ -289,7 +289,7 @@ private:
|
|||
}
|
||||
|
||||
RTLIL::SigSpec meta_mux_select(module->addWire(Twine{cell->name.str() + "_sel"}, select_width));
|
||||
meta_mux_selects.push_back(make_pair(meta_mux_select, cell->type));
|
||||
meta_mux_selects.push_back(make_pair(meta_mux_select, RTLIL::IdString(cell->type)));
|
||||
module->connect(meta_mux_select, module->Anyconst(module->design->twines.add(Twine{cell->name.str() + "_hole"}), select_width, cell->src_ref()));
|
||||
|
||||
std::vector<RTLIL::SigSpec> next_meta_mux_y_ports, meta_mux_y_ports(taint_version);
|
||||
|
|
@ -308,7 +308,7 @@ private:
|
|||
else log_cmd_error("This is a bug (2).\n");
|
||||
|
||||
}
|
||||
else if (cell->type.in(ID($_MUX_), ID($_NMUX_))) {
|
||||
else if (cell->type.in(TW($_MUX_), TW($_NMUX_))) {
|
||||
const unsigned int A = 0, B = 1, S = 2, Y = 3;
|
||||
const unsigned int NUM_PORTS = 4;
|
||||
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::B), cell->getPort(TW::S), cell->getPort(TW::Y)};
|
||||
|
|
@ -321,7 +321,7 @@ private:
|
|||
|
||||
add_precise_GLIFT_mux(cell, ports[A], port_taints[A], ports[B], port_taints[B], ports[S], port_taints[S], port_taints[Y]);
|
||||
}
|
||||
else if (cell->type.in(ID($_NOT_))) {
|
||||
else if (cell->type.in(TW($_NOT_))) {
|
||||
const unsigned int A = 0, Y = 1;
|
||||
const unsigned int NUM_PORTS = 2;
|
||||
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::Y)};
|
||||
|
|
@ -332,7 +332,7 @@ private:
|
|||
for (unsigned int i = 0; i < NUM_PORTS; ++i)
|
||||
port_taints[i] = get_corresponding_taint_signal(ports[i]);
|
||||
|
||||
if (cell->type == ID($_NOT_)) {
|
||||
if (cell->type == TW($_NOT_)) {
|
||||
module->connect(port_taints[Y], port_taints[A]);
|
||||
}
|
||||
else log_cmd_error("This is a bug (3).\n");
|
||||
|
|
|
|||
|
|
@ -63,7 +63,7 @@ struct LibertyStubber {
|
|||
}
|
||||
|
||||
f << "\tcell (\"" << derived_name << "\") {\n";
|
||||
auto& base_type = ct.cell_types[base_name];
|
||||
auto& base_type = ct.cell_types[base->name];
|
||||
i.indent = 3;
|
||||
auto sorted_ports = derived->ports;
|
||||
// Hack for CLK and C coming before Q does
|
||||
|
|
@ -117,17 +117,17 @@ struct LibertyStubber {
|
|||
}
|
||||
void liberty_cell(Module* base, Module* derived, std::ostream& f)
|
||||
{
|
||||
auto base_name = base->design->twines.str(base->meta_->name).substr(1);
|
||||
auto base_name = base->name.substr(1);
|
||||
auto derived_name = derived->design->twines.str(derived->meta_->name).substr(1);
|
||||
if (!ct.cell_types.count(base_name)) {
|
||||
if (!ct.cell_types.count(base->name)) {
|
||||
log_debug("skip skeleton for %s\n", base_name.c_str());
|
||||
return;
|
||||
}
|
||||
|
||||
if (StaticCellTypes::categories.is_ff(base_name))
|
||||
if (StaticCellTypes::categories.is_ff(base->name))
|
||||
return liberty_flop(base, derived, f);
|
||||
|
||||
auto& base_type = ct.cell_types[base_name];
|
||||
auto& base_type = ct.cell_types[base->name];
|
||||
f << "\tcell (\"" << derived_name << "\") {\n";
|
||||
for (auto x : derived->ports) {
|
||||
std::string port_name = derived->design->twines.str(x);
|
||||
|
|
|
|||
|
|
@ -95,7 +95,7 @@ struct CoveragePass : public Pass {
|
|||
{
|
||||
log_debug("Module %s:\n", module);
|
||||
for (auto wire: module->wires()) {
|
||||
log_debug("%s\t%s\t%s\n", module->selected(wire) ? "*" : " ", wire->get_src_attribute(), wire->name.unescape());
|
||||
log_debug("%s\t%s\t%s\n", module->selected(wire) ? "*" : " ", wire->get_src_attribute(), design->twines.unescaped_str(wire->name));
|
||||
for (auto src: design->src_leaves(wire)) {
|
||||
auto filename = extract_src_filename(src);
|
||||
if (filename.empty()) continue;
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ struct LtpWorker
|
|||
dst_bits.insert(bit);
|
||||
}
|
||||
|
||||
if (noff && ff_celltypes.cell_known(cell->type)) {
|
||||
if (noff && ff_celltypes.cell_known(cell->type_impl)) {
|
||||
for (auto s : src_bits)
|
||||
for (auto d : dst_bits) {
|
||||
bit2ff[s] = tuple<SigBit, Cell*>(d, cell);
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ static RTLIL::SigBit canonical_bit(RTLIL::SigBit bit)
|
|||
{
|
||||
RTLIL::Wire *w;
|
||||
while ((w = bit.wire) != NULL && !w->port_input &&
|
||||
w->driverCell()->type.in(ID($buf), ID($_BUF_))) {
|
||||
w->driverCell()->type.in(TW($buf), TW($_BUF_))) {
|
||||
bit = w->driverCell()->getPort(TW::A)[bit.offset];
|
||||
}
|
||||
return bit;
|
||||
|
|
@ -125,10 +125,10 @@ struct PortarcsPass : Pass {
|
|||
|
||||
for (auto cell : m->cells())
|
||||
// Ignore all bufnorm helper cells
|
||||
if (!cell->type.in(ID($buf), ID($input_port), ID($output_port), ID($public), ID($connect), ID($tribuf))) {
|
||||
if (!cell->type.in(TW($buf), TW($input_port), TW($output_port), TW($public), TW($connect), TW($tribuf))) {
|
||||
auto tdata = tinfo.find(cell->type);
|
||||
if (tdata == tinfo.end())
|
||||
log_cmd_error("Missing timing data for module '%s'.\n", cell->type.unescape());
|
||||
log_cmd_error("Missing timing data for module '%s'.\n", cell->type.unescaped());
|
||||
for (auto [edge, delay] : tdata->second.comb) {
|
||||
auto from = edge.first.get_connection(cell);
|
||||
auto to = edge.second.get_connection(cell);
|
||||
|
|
@ -292,7 +292,7 @@ struct PortarcsPass : Pass {
|
|||
int *p = annotations.at(canonical_bit(bit));
|
||||
for (auto i = 0; i < inputs.size(); i++) {
|
||||
if (p[i] >= 0) {
|
||||
Cell *spec = m->addCell(NEW_TWINE, ID($specify2));
|
||||
Cell *spec = m->addCell(NEW_TWINE, TW($specify2));
|
||||
spec->setParam(ID::SRC_WIDTH, 1);
|
||||
spec->setParam(ID::DST_WIDTH, 1);
|
||||
spec->setParam(ID::T_FALL_MAX, p[i]);
|
||||
|
|
|
|||
|
|
@ -47,9 +47,9 @@ struct PrintAttrsPass : public Pass {
|
|||
|
||||
static void log_const(RTLIL::IdString s, const RTLIL::Const &x, const unsigned int indent) {
|
||||
if (x.flags & RTLIL::CONST_FLAG_STRING)
|
||||
log("%s(* %s=\"%s\" *)\n", get_indent_str(indent), s.unescape(), x.decode_string());
|
||||
log("%s(* %s=\"%s\" *)\n", get_indent_str(indent), design->twines.unescaped_str(s), x.decode_string());
|
||||
else if (x.flags == RTLIL::CONST_FLAG_NONE || x.flags == RTLIL::CONST_FLAG_SIGNED)
|
||||
log("%s(* %s=%s *)\n", get_indent_str(indent), s.unescape(), x.as_string());
|
||||
log("%s(* %s=%s *)\n", get_indent_str(indent), design->twines.unescaped_str(s), x.as_string());
|
||||
else
|
||||
log_assert(x.flags & RTLIL::CONST_FLAG_STRING || x.flags == RTLIL::CONST_FLAG_NONE); //intended to fail
|
||||
}
|
||||
|
|
@ -88,7 +88,7 @@ struct PrintAttrsPass : public Pass {
|
|||
}
|
||||
|
||||
for (auto wire : mod->selected_wires()) {
|
||||
log("%s%s\n", get_indent_str(indent), wire->name.unescape());
|
||||
log("%s%s\n", get_indent_str(indent), design->twines.unescaped_str(wire->name));
|
||||
indent += 2;
|
||||
log_src(design, wire, indent);
|
||||
for (auto &it : wire->attributes)
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
#include "kernel/rtlil.h"
|
||||
#include "kernel/log.h"
|
||||
#include "backends/verilog/verilog_backend.h"
|
||||
#include "kernel/twine.h"
|
||||
|
||||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
|
@ -149,11 +150,11 @@ static bool rename_witness(RTLIL::Design *design, dict<RTLIL::Module *, int> &ca
|
|||
}
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($anyconst), ID($anyseq), ID($anyinit), ID($allconst), ID($allseq))) {
|
||||
if (cell->type.in(TW($anyconst), TW($anyseq), TW($anyinit), TW($allconst), TW($allseq))) {
|
||||
has_witness_signals = true;
|
||||
IdString QY;
|
||||
bool clk2fflogic = false;
|
||||
if (cell->type == ID($anyinit))
|
||||
if (cell->type == TW($anyinit))
|
||||
QY = (clk2fflogic = cell->get_bool_attribute(ID(clk2fflogic))) ? ID::D : ID::Q;
|
||||
else
|
||||
QY = ID::Y;
|
||||
|
|
@ -179,7 +180,7 @@ static bool rename_witness(RTLIL::Design *design, dict<RTLIL::Module *, int> &ca
|
|||
}
|
||||
|
||||
|
||||
if (cell->type.in(ID($assert), ID($assume), ID($cover), ID($live), ID($fair), ID($check))) {
|
||||
if (cell->type.in(TW($assert), TW($assume), TW($cover), TW($live), TW($fair), TW($check))) {
|
||||
has_witness_signals = true;
|
||||
if (cell->name.isPublic())
|
||||
continue;
|
||||
|
|
@ -386,6 +387,7 @@ struct RenamePass : public Pass {
|
|||
// TODO disable signorm due to rename I think?
|
||||
design->sigNormalize(false);
|
||||
|
||||
TwineSearch search(&design->twines);
|
||||
if (flag_src)
|
||||
{
|
||||
extra_args(args, argidx, design);
|
||||
|
|
@ -527,14 +529,14 @@ struct RenamePass : public Pass {
|
|||
if (argidx+1 != args.size())
|
||||
log_cmd_error("Invalid number of arguments!\n");
|
||||
|
||||
IdString new_name = RTLIL::escape_id(args[argidx]);
|
||||
TwineRef new_name = design->twines.add(Twine{RTLIL::escape_id(args[argidx])});
|
||||
RTLIL::Module *module = design->top_module();
|
||||
|
||||
if (module == nullptr)
|
||||
log_cmd_error("No top module found!\n");
|
||||
|
||||
log("Renaming module %s to %s.\n", log_id(module), new_name.unescape());
|
||||
design->rename(module, design->twines.add(Twine{new_name.str()}));
|
||||
log("Renaming module %s to %s.\n", log_id(module), design->twines.unescaped_str(new_name));
|
||||
design->rename(module, new_name);
|
||||
}
|
||||
else
|
||||
if (flag_scramble_name)
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@ struct ScatterPass : public Pass {
|
|||
for (auto conn : cell->connections())
|
||||
new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEW_TWINE, GetSize(conn.second))));
|
||||
for (auto &it : new_connections) {
|
||||
if (ct.cell_output(cell->type, it.first))
|
||||
if (ct.cell_output(cell->type.ref(), it.first))
|
||||
module->connect(RTLIL::SigSig(it.second.first, it.second.second));
|
||||
else
|
||||
module->connect(RTLIL::SigSig(it.second.second, it.second.first));
|
||||
|
|
|
|||
|
|
@ -117,7 +117,7 @@ struct SccWorker
|
|||
for (auto mod : design->modules())
|
||||
if (mod->get_blackbox_attribute(false))
|
||||
for (auto cell : mod->cells())
|
||||
if (cell->type == ID($specify2))
|
||||
if (cell->type == TW($specify2))
|
||||
{
|
||||
specifyCells.setup_module(mod);
|
||||
break;
|
||||
|
|
@ -138,18 +138,18 @@ struct SccWorker
|
|||
if (!design->selected(module, cell))
|
||||
continue;
|
||||
|
||||
if (!allCellTypes && !ct.cell_known(cell->type) && !specifyCells.cell_known(cell->type))
|
||||
if (!allCellTypes && !ct.cell_known(cell->type.ref()) && !specifyCells.cell_known(cell->type.ref()))
|
||||
continue;
|
||||
|
||||
workQueue.insert(cell);
|
||||
|
||||
RTLIL::SigSpec inputSignals, outputSignals;
|
||||
|
||||
if (specifyCells.cell_known(cell->type)) {
|
||||
if (specifyCells.cell_known(cell->type.ref())) {
|
||||
// Use specify rules of the type `(X => Y) = NN` to look for asynchronous paths in boxes.
|
||||
for (auto subcell : design->module(cell->type)->cells())
|
||||
{
|
||||
if (subcell->type != ID($specify2))
|
||||
if (subcell->type != TW($specify2))
|
||||
continue;
|
||||
|
||||
for (auto bit : subcell->getPort(TW::SRC))
|
||||
|
|
@ -171,9 +171,9 @@ struct SccWorker
|
|||
{
|
||||
bool isInput = true, isOutput = true;
|
||||
|
||||
if (ct.cell_known(cell->type)) {
|
||||
isInput = ct.cell_input(cell->type, conn.first);
|
||||
isOutput = ct.cell_output(cell->type, conn.first);
|
||||
if (ct.cell_known(cell->type.ref())) {
|
||||
isInput = ct.cell_input(cell->type.ref(), conn.first);
|
||||
isOutput = ct.cell_output(cell->type.ref(), conn.first);
|
||||
}
|
||||
|
||||
RTLIL::SigSpec sig = selectedSignals.extract(sigmap(conn.second));
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
#include "kernel/twine.h"
|
||||
#ifdef YOSYS_ENABLE_TCL
|
||||
|
||||
#include "kernel/register.h"
|
||||
|
|
@ -97,7 +98,7 @@ struct SdcObjects {
|
|||
// constraint-side tracking
|
||||
FullConstraint,
|
||||
} collect_mode;
|
||||
using CellPin = std::pair<Cell*, IdString>;
|
||||
using CellPin = std::pair<Cell*, TwineRef>;
|
||||
Design* design;
|
||||
std::vector<std::pair<std::string, Wire*>> design_ports;
|
||||
std::vector<std::pair<std::string, Cell*>> design_cells;
|
||||
|
|
@ -149,8 +150,8 @@ struct SdcObjects {
|
|||
path += name;
|
||||
design_cells.push_back(std::make_pair(path, cell));
|
||||
for (auto pin : cell->connections()) {
|
||||
IdString pin_name = pin.first;
|
||||
std::string pin_name_sdc = path + "/" + pin.first.str().substr(1);
|
||||
TwineRef pin_name = pin.first;
|
||||
std::string pin_name_sdc = path + "/" + design->twines.unescaped_str(pin.first);
|
||||
design_pins.push_back(std::make_pair(pin_name_sdc, std::make_pair(cell, pin_name)));
|
||||
}
|
||||
if (auto sub_mod = mod->design->module(cell->type)) {
|
||||
|
|
@ -168,9 +169,9 @@ struct SdcObjects {
|
|||
RTLIL::Wire *wire = top->wire(port);
|
||||
if (!wire) {
|
||||
// This should not be possible. See https://github.com/YosysHQ/yosys/pull/5594#issue-3791198573
|
||||
log_error("Port %s doesn't exist", port.unescape());
|
||||
log_error("Port %s doesn't exist", design->twines.unescaped_str(port));
|
||||
}
|
||||
design_ports.push_back(std::make_pair(port.str().substr(1), wire));
|
||||
design_ports.push_back(std::make_pair(design->twines.unescaped_str(port), wire));
|
||||
}
|
||||
std::list<std::string> hierarchy{};
|
||||
sniff_module(hierarchy, top);
|
||||
|
|
|
|||
|
|
@ -17,6 +17,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#include "kernel/rtlil.h"
|
||||
#include "kernel/twine.h"
|
||||
#include "kernel/yosys.h"
|
||||
#include "kernel/newcelltypes.h"
|
||||
#include "kernel/sigtools.h"
|
||||
|
|
@ -450,7 +452,7 @@ static void select_op_intersect(RTLIL::Design *design, RTLIL::Selection &lhs, co
|
|||
|
||||
select_all(design, lhs);
|
||||
|
||||
std::vector<RTLIL::IdString> del_list;
|
||||
std::vector<TwineRef> del_list;
|
||||
|
||||
for (auto mod_name : lhs.selected_modules) {
|
||||
if (rhs.selected_whole_module(mod_name))
|
||||
|
|
@ -471,7 +473,7 @@ static void select_op_intersect(RTLIL::Design *design, RTLIL::Selection &lhs, co
|
|||
del_list.push_back(it.first);
|
||||
continue;
|
||||
}
|
||||
std::vector<RTLIL::IdString> del_list2;
|
||||
std::vector<TwineRef> del_list2;
|
||||
for (auto &it2 : it.second)
|
||||
if (!rhs.selected_member(it.first, it2))
|
||||
del_list2.push_back(it2);
|
||||
|
|
@ -487,11 +489,11 @@ static void select_op_intersect(RTLIL::Design *design, RTLIL::Selection &lhs, co
|
|||
namespace {
|
||||
struct expand_rule_t {
|
||||
char mode;
|
||||
std::set<RTLIL::IdString> cell_types, port_names;
|
||||
std::set<std::string> cell_types, port_names;
|
||||
};
|
||||
}
|
||||
|
||||
static int parse_comma_list(std::set<RTLIL::IdString> &tokens, const std::string &str, size_t pos, std::string stopchar)
|
||||
static int parse_comma_list(std::set<std::string> &tokens, const std::string &str, size_t pos, std::string stopchar)
|
||||
{
|
||||
stopchar += ',';
|
||||
while (1) {
|
||||
|
|
@ -520,7 +522,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
|
|||
auto selected_members = lhs.selected_members[mod->meta_->name];
|
||||
|
||||
for (auto wire : mod->wires())
|
||||
if (lhs.selected_member(mod->meta_->name, wire->meta_->name) && limits.count(wire->meta_->name) == 0)
|
||||
if (lhs.selected_member(mod->meta_->name, wire->meta_->name) && limits.count(RTLIL::IdString(design->twines.str(wire->meta_->name))) == 0)
|
||||
selected_wires.insert(wire);
|
||||
|
||||
for (auto &conn : mod->connections())
|
||||
|
|
@ -538,17 +540,18 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
|
|||
}
|
||||
}
|
||||
|
||||
auto twines = design->twines;
|
||||
for (auto cell : mod->cells())
|
||||
for (auto &conn : cell->connections())
|
||||
{
|
||||
char last_mode = '-';
|
||||
if (eval_only && !yosys_celltypes.cell_evaluable(cell->type))
|
||||
if (eval_only && !yosys_celltypes.cell_evaluable(cell->type.ref()))
|
||||
goto exclude_match;
|
||||
for (auto &rule : rules) {
|
||||
last_mode = rule.mode;
|
||||
if (rule.cell_types.size() > 0 && rule.cell_types.count(cell->type) == 0)
|
||||
if (rule.cell_types.size() > 0 && rule.cell_types.count(twines.unescaped_str(cell->type_impl)) == 0)
|
||||
continue;
|
||||
if (rule.port_names.size() > 0 && rule.port_names.count(conn.first) == 0)
|
||||
if (rule.port_names.size() > 0 && rule.port_names.count(twines.unescaped_str(conn.first)) == 0)
|
||||
continue;
|
||||
if (rule.mode == '+')
|
||||
goto include_match;
|
||||
|
|
@ -558,16 +561,16 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
|
|||
if (last_mode == '+')
|
||||
goto exclude_match;
|
||||
include_match:
|
||||
is_input = mode == 'x' || ct.cell_input(cell->type, conn.first);
|
||||
is_output = mode == 'x' || ct.cell_output(cell->type, conn.first);
|
||||
is_input = mode == 'x' || ct.cell_input(cell->type.ref(), conn.first);
|
||||
is_output = mode == 'x' || ct.cell_output(cell->type.ref(), conn.first);
|
||||
for (auto &chunk : conn.second.chunks())
|
||||
if (chunk.wire != nullptr) {
|
||||
if (max_objects != 0 && selected_wires.count(chunk.wire) > 0 && selected_members.count(cell->name) == 0)
|
||||
if (max_objects != 0 && selected_wires.count(chunk.wire) > 0 && selected_members.count(cell->name.ref()) == 0)
|
||||
if (mode == 'x' || (mode == 'i' && is_output) || (mode == 'o' && is_input))
|
||||
lhs.selected_members[mod->name].insert(cell->name), sel_objects++, max_objects--;
|
||||
if (max_objects != 0 && selected_members.count(cell->name) > 0 && limits.count(cell->name) == 0 && selected_members.count(chunk.wire->name) == 0)
|
||||
lhs.selected_members[mod->meta_->name].insert(cell->name.ref()), sel_objects++, max_objects--;
|
||||
if (max_objects != 0 && selected_members.count(cell->name.ref()) > 0 && limits.count(cell->name) == 0 && selected_members.count(chunk.wire->name.ref()) == 0)
|
||||
if (mode == 'x' || (mode == 'i' && is_input) || (mode == 'o' && is_output))
|
||||
lhs.selected_members[mod->name].insert(chunk.wire->name), sel_objects++, max_objects--;
|
||||
lhs.selected_members[mod->meta_->name].insert(chunk.wire->name.ref()), sel_objects++, max_objects--;
|
||||
}
|
||||
exclude_match:;
|
||||
}
|
||||
|
|
@ -634,7 +637,7 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char
|
|||
if (design->selection_vars.count(str) > 0) {
|
||||
for (auto i1 : design->selection_vars.at(str).selected_members)
|
||||
for (auto i2 : i1.second)
|
||||
limits.insert(i2);
|
||||
limits.insert(RTLIL::IdString(design->twines.str(i2)));
|
||||
} else
|
||||
log_cmd_error("Selection %s is not defined!\n", RTLIL::unescape_id(str));
|
||||
} else
|
||||
|
|
@ -682,7 +685,7 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char
|
|||
|
||||
static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &sel)
|
||||
{
|
||||
if (design->selected_active_module.empty())
|
||||
if (!design->selected_active_module)
|
||||
return;
|
||||
|
||||
if (sel.full_selection) {
|
||||
|
|
@ -691,7 +694,7 @@ static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &se
|
|||
return;
|
||||
}
|
||||
|
||||
std::vector<RTLIL::IdString> del_list;
|
||||
std::vector<TwineRef> del_list;
|
||||
for (auto mod_name : sel.selected_modules)
|
||||
if (mod_name != design->selected_active_module)
|
||||
del_list.push_back(mod_name);
|
||||
|
|
@ -845,8 +848,8 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
|
|||
select_blackboxes = true;
|
||||
}
|
||||
|
||||
if (!design->selected_active_module.empty()) {
|
||||
arg_mod = design->selected_active_module;
|
||||
if (design->selected_active_module) {
|
||||
arg_mod = design->twines.str(design->selected_active_module);
|
||||
arg_memb = arg;
|
||||
if (!isprefixed(arg_memb))
|
||||
arg_memb_found[arg_memb] = false;
|
||||
|
|
@ -898,29 +901,29 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
|
|||
arg_mod_found[arg_mod] = true;
|
||||
|
||||
if (arg_memb == "") {
|
||||
sel.selected_modules.insert(mod->name);
|
||||
sel.selected_modules.insert(mod->meta_->name);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (arg_memb.compare(0, 2, "w:") == 0) {
|
||||
for (auto wire : mod->wires())
|
||||
if (match_ids(wire->name, arg_memb.substr(2)))
|
||||
sel.selected_members[mod->name].insert(wire->name);
|
||||
sel.selected_members[mod->meta_->name].insert(wire->name.ref());
|
||||
} else
|
||||
if (arg_memb.compare(0, 2, "i:") == 0) {
|
||||
for (auto wire : mod->wires())
|
||||
if (wire->port_input && match_ids(wire->name, arg_memb.substr(2)))
|
||||
sel.selected_members[mod->name].insert(wire->name);
|
||||
sel.selected_members[mod->meta_->name].insert(wire->name.ref());
|
||||
} else
|
||||
if (arg_memb.compare(0, 2, "o:") == 0) {
|
||||
for (auto wire : mod->wires())
|
||||
if (wire->port_output && match_ids(wire->name, arg_memb.substr(2)))
|
||||
sel.selected_members[mod->name].insert(wire->name);
|
||||
sel.selected_members[mod->meta_->name].insert(wire->name.ref());
|
||||
} else
|
||||
if (arg_memb.compare(0, 2, "x:") == 0) {
|
||||
for (auto wire : mod->wires())
|
||||
if ((wire->port_input || wire->port_output) && match_ids(wire->name, arg_memb.substr(2)))
|
||||
sel.selected_members[mod->name].insert(wire->name);
|
||||
sel.selected_members[mod->meta_->name].insert(wire->name.ref());
|
||||
} else
|
||||
if (arg_memb.compare(0, 2, "s:") == 0) {
|
||||
size_t delim = arg_memb.substr(2).find(':');
|
||||
|
|
@ -928,7 +931,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
|
|||
int width = atoi(arg_memb.substr(2).c_str());
|
||||
for (auto wire : mod->wires())
|
||||
if (wire->width == width)
|
||||
sel.selected_members[mod->name].insert(wire->name);
|
||||
sel.selected_members[mod->meta_->name].insert(wire->name.ref());
|
||||
} else {
|
||||
std::string min_str = arg_memb.substr(2, delim);
|
||||
std::string max_str = arg_memb.substr(2+delim+1);
|
||||
|
|
@ -936,18 +939,18 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
|
|||
int max_width = max_str.empty() ? -1 : atoi(max_str.c_str());
|
||||
for (auto wire : mod->wires())
|
||||
if (min_width <= wire->width && (wire->width <= max_width || max_width == -1))
|
||||
sel.selected_members[mod->name].insert(wire->name);
|
||||
sel.selected_members[mod->meta_->name].insert(wire->name.ref());
|
||||
}
|
||||
} else
|
||||
if (arg_memb.compare(0, 2, "m:") == 0) {
|
||||
for (auto &it : mod->memories)
|
||||
if (match_ids(it.first, arg_memb.substr(2)))
|
||||
sel.selected_members[mod->name].insert(it.first);
|
||||
if (match_ids(RTLIL::IdString(design->twines.str(it.first)), arg_memb.substr(2)))
|
||||
sel.selected_members[mod->meta_->name].insert(it.first);
|
||||
} else
|
||||
if (arg_memb.compare(0, 2, "c:") == 0) {
|
||||
for (auto cell : mod->cells())
|
||||
if (match_ids(cell->name, arg_memb.substr(2)))
|
||||
sel.selected_members[mod->name].insert(cell->name);
|
||||
sel.selected_members[mod->meta_->name].insert(cell->name.ref());
|
||||
} else
|
||||
if (arg_memb.compare(0, 2, "t:") == 0) {
|
||||
if (arg_memb.compare(2, 1, "@") == 0) {
|
||||
|
|
@ -957,59 +960,59 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
|
|||
|
||||
auto &muster = design->selection_vars[set_name];
|
||||
for (auto cell : mod->cells())
|
||||
if (muster.selected_modules.count(cell->type))
|
||||
sel.selected_members[mod->name].insert(cell->name);
|
||||
if (muster.selected_modules.count(cell->type.ref()))
|
||||
sel.selected_members[mod->meta_->name].insert(cell->name.ref());
|
||||
} else {
|
||||
for (auto cell : mod->cells())
|
||||
if (match_ids(cell->type, arg_memb.substr(2)))
|
||||
sel.selected_members[mod->name].insert(cell->name);
|
||||
sel.selected_members[mod->meta_->name].insert(cell->name.ref());
|
||||
}
|
||||
} else
|
||||
if (arg_memb.compare(0, 2, "p:") == 0) {
|
||||
for (auto &it : mod->processes)
|
||||
if (match_ids(it.first, arg_memb.substr(2)))
|
||||
sel.selected_members[mod->name].insert(it.first);
|
||||
if (match_ids(RTLIL::IdString(design->twines.str(it.first)), arg_memb.substr(2)))
|
||||
sel.selected_members[mod->meta_->name].insert(it.first);
|
||||
} else
|
||||
if (arg_memb.compare(0, 2, "a:") == 0) {
|
||||
for (auto wire : mod->wires())
|
||||
if (match_attr(design, wire, arg_memb.substr(2)))
|
||||
sel.selected_members[mod->name].insert(wire->name);
|
||||
sel.selected_members[mod->meta_->name].insert(wire->name.ref());
|
||||
for (auto &it : mod->memories)
|
||||
if (match_attr(design, it.second, arg_memb.substr(2)))
|
||||
sel.selected_members[mod->name].insert(it.first);
|
||||
sel.selected_members[mod->meta_->name].insert(it.first);
|
||||
for (auto cell : mod->cells())
|
||||
if (match_attr(design, cell, arg_memb.substr(2)))
|
||||
sel.selected_members[mod->name].insert(cell->name);
|
||||
sel.selected_members[mod->meta_->name].insert(cell->name.ref());
|
||||
for (auto &it : mod->processes)
|
||||
if (match_attr(design, it.second, arg_memb.substr(2)))
|
||||
sel.selected_members[mod->name].insert(it.first);
|
||||
sel.selected_members[mod->meta_->name].insert(it.first);
|
||||
} else
|
||||
if (arg_memb.compare(0, 2, "r:") == 0) {
|
||||
for (auto cell : mod->cells())
|
||||
if (match_attr(cell->parameters, arg_memb.substr(2)))
|
||||
sel.selected_members[mod->name].insert(cell->name);
|
||||
sel.selected_members[mod->meta_->name].insert(cell->name.ref());
|
||||
} else {
|
||||
std::string orig_arg_memb = arg_memb;
|
||||
if (arg_memb.compare(0, 2, "n:") == 0)
|
||||
arg_memb = arg_memb.substr(2);
|
||||
for (auto wire : mod->wires())
|
||||
if (match_ids(wire->name, arg_memb)) {
|
||||
sel.selected_members[mod->name].insert(wire->name);
|
||||
sel.selected_members[mod->meta_->name].insert(wire->name.ref());
|
||||
arg_memb_found[orig_arg_memb] = true;
|
||||
}
|
||||
for (auto &it : mod->memories)
|
||||
if (match_ids(it.first, arg_memb)) {
|
||||
sel.selected_members[mod->name].insert(it.first);
|
||||
if (match_ids(RTLIL::IdString(design->twines.str(it.first)), arg_memb)) {
|
||||
sel.selected_members[mod->meta_->name].insert(it.first);
|
||||
arg_memb_found[orig_arg_memb] = true;
|
||||
}
|
||||
for (auto cell : mod->cells())
|
||||
if (match_ids(cell->name, arg_memb)) {
|
||||
sel.selected_members[mod->name].insert(cell->name);
|
||||
sel.selected_members[mod->meta_->name].insert(cell->name.ref());
|
||||
arg_memb_found[orig_arg_memb] = true;
|
||||
}
|
||||
for (auto &it : mod->processes)
|
||||
if (match_ids(it.first, arg_memb)) {
|
||||
sel.selected_members[mod->name].insert(it.first);
|
||||
if (match_ids(RTLIL::IdString(design->twines.str(it.first)), arg_memb)) {
|
||||
sel.selected_members[mod->meta_->name].insert(it.first);
|
||||
arg_memb_found[orig_arg_memb] = true;
|
||||
}
|
||||
}
|
||||
|
|
@ -1365,6 +1368,7 @@ struct SelectPass : public Pass {
|
|||
|
||||
work_stack.clear();
|
||||
|
||||
TwineSearch search(&design->twines);
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++)
|
||||
{
|
||||
|
|
@ -1431,10 +1435,11 @@ struct SelectPass : public Pass {
|
|||
continue;
|
||||
}
|
||||
if (arg == "-module" && argidx+1 < args.size()) {
|
||||
RTLIL::IdString mod_name = RTLIL::escape_id(args[++argidx]);
|
||||
if (design->module(mod_name) == nullptr)
|
||||
log_cmd_error("No such module: %s\n", mod_name.unescape());
|
||||
design->selected_active_module = mod_name.str();
|
||||
std::string mod_name = RTLIL::escape_id(args[++argidx]);
|
||||
TwineRef t = search.find(mod_name);
|
||||
if (t == Twine::Null || design->module(t) == nullptr)
|
||||
log_cmd_error("No such module: %s\n", RTLIL::unescape_id(mod_name));
|
||||
design->selected_active_module = t;
|
||||
got_module = true;
|
||||
continue;
|
||||
}
|
||||
|
|
@ -1475,7 +1480,7 @@ struct SelectPass : public Pass {
|
|||
}
|
||||
IdString mod_name = RTLIL::escape_id(line.substr(0, slash_pos));
|
||||
IdString obj_name = RTLIL::escape_id(line.substr(slash_pos+1));
|
||||
sel.selected_members[mod_name].insert(obj_name);
|
||||
sel.selected_members[design->twines.add(Twine{mod_name.str()})].insert(design->twines.add(Twine{obj_name.str()}));
|
||||
}
|
||||
|
||||
select_filter_active_mod(design, sel);
|
||||
|
|
@ -1493,7 +1498,7 @@ struct SelectPass : public Pass {
|
|||
const char *common_flagset = "-add, -del, -assert-none, -assert-any, -assert-mod-count, -assert-count, -assert-max, or -assert-min";
|
||||
|
||||
if (common_flagset_tally > 1)
|
||||
log_cmd_error("Options %s can not be combined.\n", common_flagset);
|
||||
log_cmd_error("Options %s can not be combined.\n", common_flagset);
|
||||
|
||||
if ((list_mode || !write_file.empty() || count_mode) && common_flagset_tally)
|
||||
log_cmd_error("Options -list, -list-mod, -write and -count can not be combined with %s.\n", common_flagset);
|
||||
|
|
@ -1519,7 +1524,7 @@ struct SelectPass : public Pass {
|
|||
|
||||
if (clear_mode) {
|
||||
design->selection() = RTLIL::Selection::FullSelection(design);
|
||||
design->selected_active_module = std::string();
|
||||
design->selected_active_module = TwineRef{};
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -1545,11 +1550,11 @@ struct SelectPass : public Pass {
|
|||
sel->optimize(design);
|
||||
for (auto mod : design->all_selected_modules())
|
||||
{
|
||||
if (sel->selected_whole_module(mod->name) && list_mode)
|
||||
if (sel->selected_whole_module(mod->meta_->name) && list_mode)
|
||||
log("%s\n", mod);
|
||||
if (!list_mod_mode)
|
||||
for (auto it : mod->selected_members())
|
||||
LOG_OBJECT("%s/%s\n", mod->name.unescape().c_str(), it->name.unescape().c_str())
|
||||
LOG_OBJECT("%s/%s\n", design->twines.unescaped_str(mod->name).c_str(), mod->design->twines.unescaped_str(it->meta_->name).c_str())
|
||||
}
|
||||
if (count_mode)
|
||||
{
|
||||
|
|
@ -1673,10 +1678,10 @@ struct SelectPass : public Pass {
|
|||
if (sel.full_selection)
|
||||
log("*\n");
|
||||
for (auto &it : sel.selected_modules)
|
||||
log("%s\n", it.unescape());
|
||||
log("%s\n", design->twines.unescaped_str(it).c_str());
|
||||
for (auto &it : sel.selected_members)
|
||||
for (auto &it2 : it.second)
|
||||
log("%s/%s\n", it.first.unescape(), it2.unescape());
|
||||
log("%s/%s\n", design->twines.unescaped_str(it.first).c_str(), design->twines.unescaped_str(it2).c_str());
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -1728,17 +1733,17 @@ struct CdPass : public Pass {
|
|||
if (args.size() == 1 || args[1] == "/") {
|
||||
design->pop_selection();
|
||||
design->push_full_selection();
|
||||
design->selected_active_module = std::string();
|
||||
design->selected_active_module = TwineRef{};
|
||||
return;
|
||||
}
|
||||
|
||||
if (args[1] == "..")
|
||||
{
|
||||
string modname = design->selected_active_module;
|
||||
string modname = design->twines.str(design->selected_active_module);
|
||||
|
||||
design->pop_selection();
|
||||
design->push_full_selection();
|
||||
design->selected_active_module = std::string();
|
||||
design->selected_active_module = TwineRef{};
|
||||
|
||||
while (1)
|
||||
{
|
||||
|
|
@ -1748,12 +1753,12 @@ struct CdPass : public Pass {
|
|||
break;
|
||||
|
||||
modname = modname.substr(0, pos);
|
||||
Module *mod = design->module(modname);
|
||||
Module *mod = design->module(RTLIL::IdString(modname));
|
||||
|
||||
if (mod == nullptr)
|
||||
continue;
|
||||
|
||||
design->selected_active_module = modname;
|
||||
design->selected_active_module = design->twines.add(Twine{modname});
|
||||
design->pop_selection();
|
||||
design->push_full_selection();
|
||||
select_filter_active_mod(design, design->selection());
|
||||
|
|
@ -1766,14 +1771,15 @@ struct CdPass : public Pass {
|
|||
|
||||
std::string modname = RTLIL::escape_id(args[1]);
|
||||
|
||||
if (design->module(modname) == nullptr && !design->selected_active_module.empty()) {
|
||||
if (design->module(RTLIL::IdString(modname)) == nullptr && design->selected_active_module) {
|
||||
RTLIL::Module *module = design->module(design->selected_active_module);
|
||||
if (module != nullptr && module->cell(modname) != nullptr)
|
||||
modname = module->cell(modname)->type.str();
|
||||
TwineRef cell_ref = design->twines.lookup(modname);
|
||||
if (module != nullptr && cell_ref && module->cell(cell_ref) != nullptr)
|
||||
modname = design->twines.str(module->cell(cell_ref)->type.ref());
|
||||
}
|
||||
|
||||
if (design->module(modname) != nullptr) {
|
||||
design->selected_active_module = modname;
|
||||
if (design->module(RTLIL::IdString(modname)) != nullptr) {
|
||||
design->selected_active_module = design->twines.add(Twine{modname});
|
||||
design->pop_selection();
|
||||
design->push_full_selection();
|
||||
select_filter_active_mod(design, design->selection());
|
||||
|
|
@ -1788,17 +1794,20 @@ struct CdPass : public Pass {
|
|||
template<typename T>
|
||||
static void log_matches(const char *title, Module *module, const T &list)
|
||||
{
|
||||
std::vector<IdString> matches;
|
||||
std::vector<TwineRef> matches;
|
||||
|
||||
for (auto &it : list)
|
||||
if (module->selected(it.second))
|
||||
matches.push_back(RTLIL::IdString(it.second->name));
|
||||
matches.push_back(it.first);
|
||||
|
||||
if (!matches.empty()) {
|
||||
log("\n%d %s:\n", int(matches.size()), title);
|
||||
std::sort(matches.begin(), matches.end(), RTLIL::sort_by_id_str());
|
||||
for (auto id : matches)
|
||||
log(" %s\n", id.unescape());
|
||||
auto &twines = module->design->twines;
|
||||
std::sort(matches.begin(), matches.end(), [&](TwineRef a, TwineRef b) {
|
||||
return twines.str(a) < twines.str(b);
|
||||
});
|
||||
for (auto ref : matches)
|
||||
log(" %s\n", twines.unescaped_str(ref).c_str());
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1825,7 +1834,7 @@ struct LsPass : public Pass {
|
|||
size_t argidx = 1;
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
if (design->selected_active_module.empty())
|
||||
if (!design->selected_active_module)
|
||||
{
|
||||
std::vector<IdString> matches;
|
||||
|
||||
|
|
@ -1836,7 +1845,7 @@ struct LsPass : public Pass {
|
|||
log("\n%d %s:\n", int(matches.size()), "modules");
|
||||
std::sort(matches.begin(), matches.end(), RTLIL::sort_by_id_str());
|
||||
for (auto id : matches)
|
||||
log(" %s%s\n", id.unescape(), design->selected_whole_module(design->module(id)) ? "" : "*");
|
||||
log(" %s%s\n", design->twines.unescaped_str(id), design->selected_whole_module(design->module(id)) ? "" : "*");
|
||||
}
|
||||
}
|
||||
else
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ static RTLIL::Wire * add_wire(RTLIL::Module *module, std::string name, int width
|
|||
RTLIL::Wire *wire = NULL;
|
||||
TwineRef t = module->design->twines.add(Twine{name});
|
||||
|
||||
if (module->count_id(name) != 0)
|
||||
if (module->count_id(t) != 0)
|
||||
{
|
||||
log("Module %s already has such an object %s.\n", module->name, name);
|
||||
name += "$";
|
||||
|
|
@ -47,7 +47,7 @@ static RTLIL::Wire * add_wire(RTLIL::Module *module, std::string name, int width
|
|||
}
|
||||
else
|
||||
{
|
||||
wire = module->addWire(name, width);
|
||||
wire = module->addWire(t, width);
|
||||
wire->port_input = flag_input;
|
||||
wire->port_output = flag_output;
|
||||
|
||||
|
|
@ -305,7 +305,7 @@ struct SetundefPass : public Pass {
|
|||
CellTypes ct(design);
|
||||
for (auto &it : module->cells_)
|
||||
for (auto &conn : it.second->connections())
|
||||
if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
|
||||
if (!ct.cell_known(it.second->type.ref()) || ct.cell_output(it.second->type.ref(), conn.first))
|
||||
undriven_signals.del(sigmap(conn.second));
|
||||
|
||||
RTLIL::SigSpec sig = undriven_signals.export_all();
|
||||
|
|
@ -340,7 +340,7 @@ struct SetundefPass : public Pass {
|
|||
CellTypes ct(design);
|
||||
for (auto &it : module->cells_)
|
||||
for (auto &conn : it.second->connections())
|
||||
if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
|
||||
if (!ct.cell_known(it.second->type.ref()) || ct.cell_output(it.second->type.ref(), conn.first))
|
||||
undriven_signals.del(sigmap(conn.second));
|
||||
|
||||
RTLIL::SigSpec sig = undriven_signals.export_all();
|
||||
|
|
|
|||
|
|
@ -148,14 +148,15 @@ struct ShowWorker
|
|||
|
||||
std::string findColor(IdString member_name)
|
||||
{
|
||||
TwineRef member_ref = design->twines.lookup(member_name.str());
|
||||
for (auto &s : color_selections)
|
||||
if (s.second.selected_member(module->name, member_name)) {
|
||||
if (member_ref && s.second.selected_member(module->meta_->name, member_ref)) {
|
||||
return stringf("color=\"%s\", fontcolor=\"%s\"", s.first, s.first);
|
||||
}
|
||||
|
||||
RTLIL::Const colorattr_value;
|
||||
RTLIL::Cell *cell = module->cell(member_name);
|
||||
RTLIL::Wire *wire = module->wire(member_name);
|
||||
RTLIL::Cell *cell = member_ref ? module->cell(member_ref) : nullptr;
|
||||
RTLIL::Wire *wire = member_ref ? module->wire(member_ref) : nullptr;
|
||||
|
||||
if (cell && cell->attributes.count(colorattr))
|
||||
colorattr_value = cell->attributes.at(colorattr);
|
||||
|
|
@ -174,8 +175,9 @@ struct ShowWorker
|
|||
|
||||
const char *findLabel(std::string member_name)
|
||||
{
|
||||
TwineRef member_ref = design->twines.lookup(member_name);
|
||||
for (auto &s : label_selections)
|
||||
if (s.second.selected_member(module->name, member_name))
|
||||
if (member_ref && s.second.selected_member(module->meta_->name, member_ref))
|
||||
return escape(s.first);
|
||||
return escape(member_name, true);
|
||||
}
|
||||
|
|
@ -240,7 +242,7 @@ struct ShowWorker
|
|||
|
||||
if (sig.is_chunk()) {
|
||||
const RTLIL::SigChunk &c = sig.as_chunk();
|
||||
if (c.wire != nullptr && design->selected_member(module->name, c.wire->name)) {
|
||||
if (c.wire != nullptr && design->selected_member(module->meta_->name, c.wire->name.ref())) {
|
||||
if (!range_check || c.wire->width == c.width)
|
||||
return stringf("n%d", id2num(c.wire->name));
|
||||
} else {
|
||||
|
|
@ -472,10 +474,10 @@ struct ShowWorker
|
|||
std::vector<std::string> in_label_pieces, out_label_pieces;
|
||||
|
||||
for (auto &conn : cell->connections()) {
|
||||
if (!ct.cell_output(cell->type, conn.first))
|
||||
in_ports.push_back(conn.first);
|
||||
if (!ct.cell_output(cell->type.ref(), conn.first))
|
||||
in_ports.push_back(RTLIL::IdString(design->twines.str(conn.first)));
|
||||
else
|
||||
out_ports.push_back(conn.first);
|
||||
out_ports.push_back(RTLIL::IdString(design->twines.str(conn.first)));
|
||||
}
|
||||
|
||||
std::sort(in_ports.begin(), in_ports.end(), RTLIL::sort_by_id_str());
|
||||
|
|
@ -501,8 +503,8 @@ struct ShowWorker
|
|||
|
||||
std::string code;
|
||||
for (auto &conn : cell->connections()) {
|
||||
code += gen_portbox(stringf("c%d:p%d", id2num(cell->name), id2num(conn.first)),
|
||||
conn.second, ct.cell_output(cell->type, conn.first));
|
||||
code += gen_portbox(stringf("c%d:p%d", id2num(cell->name), id2num(RTLIL::IdString(design->twines.str(conn.first)))),
|
||||
conn.second, ct.cell_output(cell->type.ref(), conn.first));
|
||||
}
|
||||
|
||||
std::string src_href;
|
||||
|
|
@ -523,7 +525,7 @@ struct ShowWorker
|
|||
{
|
||||
RTLIL::Process *proc = it.second;
|
||||
|
||||
if (!design->selected_member(module->name, proc->name))
|
||||
if (!design->selected_member(module->meta_->name, it.first))
|
||||
continue;
|
||||
|
||||
std::set<RTLIL::SigSpec> input_signals, output_signals;
|
||||
|
|
@ -549,22 +551,23 @@ struct ShowWorker
|
|||
net_conn_map[node].color = nextColor(sig, net_conn_map[node].color);
|
||||
}
|
||||
|
||||
std::string proc_src = proc->name.unescape();
|
||||
std::string proc_name_str = design->twines.str(it.first);
|
||||
std::string proc_src = design->twines.unescaped_str(it.first);
|
||||
if (proc->has_attribute(ID::src) > 0)
|
||||
proc_src = proc->get_src_attribute();
|
||||
fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\", %s];\n", pidx, findLabel(proc->name.str()), proc_src.c_str(), findColor(proc->name).c_str());
|
||||
fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\", %s];\n", pidx, findLabel(proc_name_str), proc_src.c_str(), findColor(RTLIL::IdString(proc_name_str)).c_str());
|
||||
}
|
||||
|
||||
for (auto &conn : module->connections())
|
||||
{
|
||||
bool found_lhs_wire = false;
|
||||
for (auto &c : conn.first.chunks()) {
|
||||
if (c.wire == nullptr || design->selected_member(module->name, c.wire->name))
|
||||
if (c.wire == nullptr || design->selected_member(module->meta_->name, c.wire->name.ref()))
|
||||
found_lhs_wire = true;
|
||||
}
|
||||
bool found_rhs_wire = false;
|
||||
for (auto &c : conn.second.chunks()) {
|
||||
if (c.wire == nullptr || design->selected_member(module->name, c.wire->name))
|
||||
if (c.wire == nullptr || design->selected_member(module->meta_->name, c.wire->name.ref()))
|
||||
found_rhs_wire = true;
|
||||
}
|
||||
if (!found_lhs_wire || !found_rhs_wire)
|
||||
|
|
@ -645,16 +648,16 @@ struct ShowWorker
|
|||
module = mod;
|
||||
if (design->selected_whole_module(module->name)) {
|
||||
if (module->get_blackbox_attribute()) {
|
||||
//log("Skipping blackbox module %s.\n", module->name.unescape());
|
||||
//log("Skipping blackbox module %s.\n", design->twines.unescaped_str(module->name));
|
||||
continue;
|
||||
} else
|
||||
if (module->cells().size() == 0 && module->connections().empty() && module->processes.empty()) {
|
||||
log("Skipping empty module %s.\n", module->name.unescape());
|
||||
log("Skipping empty module %s.\n", design->twines.unescaped_str(module->name));
|
||||
continue;
|
||||
} else
|
||||
log("Dumping module %s to page %d.\n", module->name.unescape(), ++page_counter);
|
||||
log("Dumping module %s to page %d.\n", design->twines.unescaped_str(module->name), ++page_counter);
|
||||
} else
|
||||
log("Dumping selected parts of module %s to page %d.\n", module->name.unescape(), ++page_counter);
|
||||
log("Dumping selected parts of module %s to page %d.\n", design->twines.unescaped_str(module->name), ++page_counter);
|
||||
handle_module();
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -75,7 +75,7 @@ struct SpliceWorker
|
|||
RTLIL::SigSpec new_sig = sig;
|
||||
|
||||
if (sig_a.size() != sig.size()) {
|
||||
RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($slice));
|
||||
RTLIL::Cell *cell = module->addCell(NEW_TWINE, TW::$slice);
|
||||
cell->parameters[ID::OFFSET] = offset;
|
||||
cell->parameters[ID::A_WIDTH] = sig_a.size();
|
||||
cell->parameters[ID::Y_WIDTH] = sig.size();
|
||||
|
|
@ -132,7 +132,7 @@ struct SpliceWorker
|
|||
RTLIL::SigSpec new_sig = get_sliced_signal(chunks.front());
|
||||
for (size_t i = 1; i < chunks.size(); i++) {
|
||||
RTLIL::SigSpec sig2 = get_sliced_signal(chunks[i]);
|
||||
RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($concat));
|
||||
RTLIL::Cell *cell = module->addCell(NEW_TWINE, TW::$concat);
|
||||
cell->parameters[ID::A_WIDTH] = new_sig.size();
|
||||
cell->parameters[ID::B_WIDTH] = sig2.size();
|
||||
cell->setPort(TW::A, new_sig);
|
||||
|
|
@ -149,7 +149,7 @@ struct SpliceWorker
|
|||
|
||||
void run()
|
||||
{
|
||||
log("Splicing signals in module %s:\n", module->name.unescape());
|
||||
log("Splicing signals in module %s:\n", design->twines.unescaped_str(module->name));
|
||||
|
||||
driven_bits.push_back(RTLIL::State::Sm);
|
||||
driven_bits.push_back(RTLIL::State::Sm);
|
||||
|
|
@ -165,7 +165,7 @@ struct SpliceWorker
|
|||
|
||||
for (auto cell : module->cells())
|
||||
for (auto &conn : cell->connections())
|
||||
if (!ct.cell_known(cell->type) || ct.cell_output(cell->type, conn.first)) {
|
||||
if (!ct.cell_known(cell->type.ref()) || ct.cell_output(cell->type.ref(), conn.first)) {
|
||||
RTLIL::SigSpec sig = sigmap(conn.second);
|
||||
driven_chunks.insert(sig);
|
||||
for (auto &bit : sig.to_sigbit_vector())
|
||||
|
|
@ -189,10 +189,10 @@ struct SpliceWorker
|
|||
if (!sel_by_wire && !design->selected(module, cell))
|
||||
continue;
|
||||
for (auto &conn : cell->connections_)
|
||||
if (ct.cell_input(cell->type, conn.first)) {
|
||||
if (ports.size() > 0 && !ports.count(conn.first))
|
||||
if (ct.cell_input(cell->type.ref(), conn.first)) {
|
||||
if (ports.size() > 0 && !ports.count(RTLIL::IdString(design->twines.str(conn.first))))
|
||||
continue;
|
||||
if (no_ports.size() > 0 && no_ports.count(conn.first))
|
||||
if (no_ports.size() > 0 && no_ports.count(RTLIL::IdString(design->twines.str(conn.first))))
|
||||
continue;
|
||||
RTLIL::SigSpec sig = sigmap(conn.second);
|
||||
if (!sel_by_cell) {
|
||||
|
|
@ -231,8 +231,8 @@ struct SpliceWorker
|
|||
|
||||
for (auto &it : rework_wires)
|
||||
{
|
||||
RTLIL::IdString orig_name = it.first->name;
|
||||
module->rename(it.first, NEW_ID);
|
||||
TwineRef orig_name = it.first->name.ref();
|
||||
module->rename(it.first, design->twines.add(NEW_TWINE));
|
||||
|
||||
RTLIL::Wire *new_port = module->addWire(orig_name, it.first);
|
||||
it.first->port_id = 0;
|
||||
|
|
|
|||
|
|
@ -181,9 +181,9 @@ struct SplitnetsPass : public Pass {
|
|||
for (auto c : module->cells())
|
||||
for (auto &p : c->connections())
|
||||
{
|
||||
if (!ct.cell_known(c->type))
|
||||
if (!ct.cell_known(c->type.ref()))
|
||||
continue;
|
||||
if (!ct.cell_output(c->type, p.first))
|
||||
if (!ct.cell_output(c->type.ref(), p.first))
|
||||
continue;
|
||||
|
||||
RTLIL::SigSpec sig = p.second;
|
||||
|
|
|
|||
|
|
@ -35,8 +35,8 @@ struct StaWorker
|
|||
|
||||
struct t_data {
|
||||
Cell* driver;
|
||||
IdString dst_port, src_port;
|
||||
vector<tuple<SigBit,int,IdString>> fanouts;
|
||||
TwineRef dst_port, src_port;
|
||||
vector<tuple<SigBit,int,TwineRef>> fanouts;
|
||||
SigBit backtrack;
|
||||
t_data() : driver(nullptr) {}
|
||||
};
|
||||
|
|
@ -44,7 +44,7 @@ struct StaWorker
|
|||
std::deque<SigBit> queue;
|
||||
struct t_endpoint {
|
||||
Cell *sink;
|
||||
IdString port;
|
||||
TwineRef port;
|
||||
int required;
|
||||
t_endpoint() : sink(nullptr), required(0) {}
|
||||
};
|
||||
|
|
@ -66,23 +66,23 @@ struct StaWorker
|
|||
Module *inst_module = design->module(cell->type);
|
||||
if (!inst_module) {
|
||||
if (unrecognised_cells.insert(cell->type).second)
|
||||
log_warning("Cell type '%s' not recognised! Ignoring.\n", cell->type.unescape());
|
||||
log_warning("Cell type '%s' not recognised! Ignoring.\n", cell->type.unescaped());
|
||||
continue;
|
||||
}
|
||||
|
||||
if (!inst_module->get_blackbox_attribute()) {
|
||||
log_warning("Cell type '%s' is not a black- nor white-box! Ignoring.\n", cell->type.unescape());
|
||||
log_warning("Cell type '%s' is not a black- nor white-box! Ignoring.\n", cell->type.unescaped());
|
||||
continue;
|
||||
}
|
||||
|
||||
IdString derived_type = inst_module->derive(design, cell->parameters);
|
||||
TwineRef derived_type = inst_module->derive(design, cell->parameters);
|
||||
inst_module = design->module(derived_type);
|
||||
log_assert(inst_module);
|
||||
|
||||
if (!timing.count(derived_type)) {
|
||||
auto &t = timing.setup_module(inst_module);
|
||||
if (t.has_inputs && t.comb.empty() && t.arrival.empty() && t.required.empty())
|
||||
log_warning("Module '%s' has no timing arcs!\n", cell->type.unescape());
|
||||
log_warning("Module '%s' has no timing arcs!\n", cell->type.unescaped());
|
||||
}
|
||||
|
||||
auto &t = timing.at(derived_type);
|
||||
|
|
@ -206,7 +206,7 @@ struct StaWorker
|
|||
log("Latest arrival time in '%s' is %d:\n", module, maxarrival);
|
||||
auto it = endpoints.find(maxbit);
|
||||
if (it != endpoints.end() && it->second.sink)
|
||||
log(" %6d %s (%s.%s)\n", maxarrival, it->second.sink, it->second.sink->type.unescape(), it->second.port.unescape());
|
||||
log(" %6d %s (%s.%s)\n", maxarrival, it->second.sink, design->twines.unescaped_str(it->second.sink->type), design->twines.unescaped_str(it->second.port));
|
||||
else {
|
||||
log(" %6d (%s)\n", maxarrival, b.wire->port_output ? "<primary output>" : "<unknown>");
|
||||
if (!b.wire->port_output)
|
||||
|
|
@ -217,7 +217,7 @@ struct StaWorker
|
|||
int arrival = b.wire->get_intvec_attribute(ID::sta_arrival)[b.offset];
|
||||
if (jt->second.driver) {
|
||||
log(" %s\n", log_signal(b));
|
||||
log(" %6d %s (%s.%s->%s)\n", arrival, jt->second.driver, jt->second.driver->type.unescape(), jt->second.src_port.unescape(), jt->second.dst_port.unescape());
|
||||
log(" %6d %s (%s.%s->%s)\n", arrival, jt->second.driver, design->twines.unescaped_str(jt->second.driver->type), design->twines.unescaped_str(jt->second.src_port), design->twines.unescaped_str(jt->second.dst_port));
|
||||
}
|
||||
else if (b.wire->port_input)
|
||||
log(" %6d %s (%s)\n", arrival, log_signal(b), "<primary input>");
|
||||
|
|
|
|||
|
|
@ -59,18 +59,18 @@ struct statdata_t {
|
|||
double local_sequential_area = 0;
|
||||
double submodule_area = 0;
|
||||
int num_submodules = 0;
|
||||
std::map<RTLIL::IdString, unsigned int, RTLIL::sort_by_id_str> num_submodules_by_type;
|
||||
std::map<RTLIL::IdString, double, RTLIL::sort_by_id_str> submodules_area_by_type;
|
||||
std::map<TwineRef, unsigned int, RTLIL::sort_by_id_str> num_submodules_by_type;
|
||||
std::map<TwineRef, double, RTLIL::sort_by_id_str> submodules_area_by_type;
|
||||
|
||||
std::map<RTLIL::IdString, unsigned int, RTLIL::sort_by_id_str> local_num_cells_by_type;
|
||||
std::map<RTLIL::IdString, double, RTLIL::sort_by_id_str> local_area_cells_by_type;
|
||||
std::map<RTLIL::IdString, double, RTLIL::sort_by_id_str> local_seq_area_cells_by_type;
|
||||
std::map<TwineRef, unsigned int, RTLIL::sort_by_id_str> local_num_cells_by_type;
|
||||
std::map<TwineRef, double, RTLIL::sort_by_id_str> local_area_cells_by_type;
|
||||
std::map<TwineRef, double, RTLIL::sort_by_id_str> local_seq_area_cells_by_type;
|
||||
string tech;
|
||||
|
||||
std::map<RTLIL::IdString, unsigned int, RTLIL::sort_by_id_str> num_cells_by_type;
|
||||
std::map<RTLIL::IdString, double, RTLIL::sort_by_id_str> area_cells_by_type;
|
||||
std::map<RTLIL::IdString, double, RTLIL::sort_by_id_str> seq_area_cells_by_type;
|
||||
std::set<RTLIL::IdString> unknown_cell_area;
|
||||
std::map<TwineRef, unsigned int, RTLIL::sort_by_id_str> num_cells_by_type;
|
||||
std::map<TwineRef, double, RTLIL::sort_by_id_str> area_cells_by_type;
|
||||
std::map<TwineRef, double, RTLIL::sort_by_id_str> seq_area_cells_by_type;
|
||||
std::set<TwineRef> unknown_cell_area;
|
||||
|
||||
statdata_t operator+(const statdata_t &other) const
|
||||
{
|
||||
|
|
@ -141,7 +141,7 @@ struct statdata_t {
|
|||
}
|
||||
}
|
||||
|
||||
statdata_t(RTLIL::Design *design, const RTLIL::Module *mod, bool width_mode, dict<IdString, cell_area_t> &cell_area, string techname)
|
||||
statdata_t(RTLIL::Design *design, const RTLIL::Module *mod, bool width_mode, dict<TwineRef, cell_area_t> &cell_area, string techname)
|
||||
{
|
||||
tech = techname;
|
||||
|
||||
|
|
@ -183,35 +183,35 @@ struct statdata_t {
|
|||
local_num_memory_bits += it.second->width * it.second->size;
|
||||
}
|
||||
for (auto cell : mod->selected_cells()) {
|
||||
RTLIL::IdString cell_type = cell->type;
|
||||
TwineRef cell_type = cell->type_impl;
|
||||
if (width_mode) {
|
||||
if (cell_type.in(ID($not), ID($pos), ID($neg), ID($logic_not), ID($logic_and), ID($logic_or), ID($reduce_and),
|
||||
ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($lut), ID($and), ID($or),
|
||||
ID($xor), ID($xnor), ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx), ID($lt),
|
||||
ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt), ID($add), ID($sub), ID($mul),
|
||||
ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow), ID($alu))) {
|
||||
if (cell_type.in(TW($not), TW($pos), TW($neg), TW($logic_not), TW($logic_and), TW($logic_or), TW($reduce_and),
|
||||
TW($reduce_or), TW($reduce_xor), TW($reduce_xnor), TW($reduce_bool), TW($lut), TW($and), TW($or),
|
||||
TW($xor), TW($xnor), TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx), TW($lt),
|
||||
TW($le), TW($eq), TW($ne), TW($eqx), TW($nex), TW($ge), TW($gt), TW($add), TW($sub), TW($mul),
|
||||
TW($div), TW($mod), TW($divfloor), TW($modfloor), TW($pow), TW($alu))) {
|
||||
int width_a = cell->hasPort(TW::A) ? GetSize(cell->getPort(TW::A)) : 0;
|
||||
int width_b = cell->hasPort(TW::B) ? GetSize(cell->getPort(TW::B)) : 0;
|
||||
int width_y = cell->hasPort(TW::Y) ? GetSize(cell->getPort(TW::Y)) : 0;
|
||||
cell_type = stringf("%s_%d", cell_type, max<int>({width_a, width_b, width_y}));
|
||||
} else if (cell_type.in(ID($mux)))
|
||||
cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(TW::Y)));
|
||||
else if (cell_type.in(ID($bmux), ID($pmux)))
|
||||
cell_type = design->twines.add(Twine{stringf("%s_%d", cell_type, max<int>({width_a, width_b, width_y}))});
|
||||
} else if (cell_type.in(TW($mux)))
|
||||
cell_type = design->twines.add(Twine{stringf("%s_%d", cell_type, GetSize(cell->getPort(TW::Y)))});
|
||||
else if (cell_type.in(TW($bmux), TW($pmux)))
|
||||
cell_type =
|
||||
stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(TW::Y)), GetSize(cell->getPort(TW::S)));
|
||||
else if (cell_type == ID($demux))
|
||||
design->twines.add(Twine{stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(TW::Y)), GetSize(cell->getPort(TW::S)))});
|
||||
else if (cell_type == TW($demux))
|
||||
cell_type =
|
||||
stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::S)));
|
||||
else if (cell_type.in(ID($sr), ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe),
|
||||
ID($sdff), ID($sdffe), ID($sdffce), ID($aldff), ID($aldffe), ID($dlatch), ID($adlatch),
|
||||
ID($dlatchsr)))
|
||||
cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(TW::Q)));
|
||||
design->twines.add(Twine{stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::S)))});
|
||||
else if (cell_type.in(TW($sr), TW($ff), TW($dff), TW($dffe), TW($dffsr), TW($dffsre), TW($adff), TW($adffe),
|
||||
TW($sdff), TW($sdffe), TW($sdffce), TW($aldff), TW($aldffe), TW($dlatch), TW($adlatch),
|
||||
TW($dlatchsr)))
|
||||
cell_type = design->twines.add(Twine{stringf("%s_%d", cell_type, GetSize(cell->getPort(TW::Q)))});
|
||||
}
|
||||
|
||||
if (!cell_area.empty()) {
|
||||
// check if cell_area provides a area calculator
|
||||
if (cell_area.count(cell->type)) {
|
||||
cell_area_t cell_data = cell_area.at(cell->type);
|
||||
if (cell_area.count(cell->type_impl)) {
|
||||
cell_area_t cell_data = cell_area.at(cell->type_impl);
|
||||
if (cell_data.single_parameter_area.size() > 0) {
|
||||
// assume that we just take the max of the A,B,Y ports
|
||||
|
||||
|
|
@ -337,18 +337,16 @@ struct statdata_t {
|
|||
num_processes++;
|
||||
local_num_processes++;
|
||||
}
|
||||
RTLIL::IdString cell_name = mod->name;
|
||||
auto s = cell_name.str();
|
||||
}
|
||||
|
||||
unsigned int estimate_xilinx_lc()
|
||||
{
|
||||
unsigned int lut6_cnt = num_cells_by_type[ID(LUT6)];
|
||||
unsigned int lut5_cnt = num_cells_by_type[ID(LUT5)];
|
||||
unsigned int lut4_cnt = num_cells_by_type[ID(LUT4)];
|
||||
unsigned int lut3_cnt = num_cells_by_type[ID(LUT3)];
|
||||
unsigned int lut2_cnt = num_cells_by_type[ID(LUT2)];
|
||||
unsigned int lut1_cnt = num_cells_by_type[ID(LUT1)];
|
||||
unsigned int lut6_cnt = num_cells_by_type[TW::LUT6];
|
||||
unsigned int lut5_cnt = num_cells_by_type[TW::LUT5];
|
||||
unsigned int lut4_cnt = num_cells_by_type[TW::LUT4];
|
||||
unsigned int lut3_cnt = num_cells_by_type[TW::LUT3];
|
||||
unsigned int lut2_cnt = num_cells_by_type[TW::LUT2];
|
||||
unsigned int lut1_cnt = num_cells_by_type[TW::LUT1];
|
||||
unsigned int lc_cnt = 0;
|
||||
|
||||
lc_cnt += lut6_cnt;
|
||||
|
|
@ -505,7 +503,7 @@ struct statdata_t {
|
|||
}
|
||||
}
|
||||
|
||||
void log_data(RTLIL::IdString mod_name, bool top_mod, bool print_area = true, bool print_hierarchical = true, bool print_global_only = false)
|
||||
void log_data(const TwinePool& twines, TwineRef mod_name, bool top_mod, bool print_area = true, bool print_hierarchical = true, bool print_global_only = false)
|
||||
{
|
||||
|
||||
print_log_header(print_area, print_hierarchical, print_global_only);
|
||||
|
|
@ -523,7 +521,7 @@ struct statdata_t {
|
|||
print_log_line("cells", local_num_cells, local_area, num_cells, area, 0, print_area, print_hierarchical, print_global_only);
|
||||
for (auto &it : num_cells_by_type)
|
||||
if (it.second) {
|
||||
auto name = string(it.first.unescape());
|
||||
auto name = twines.unescaped_str(it.first);
|
||||
print_log_line(name, local_num_cells_by_type.count(it.first) ? local_num_cells_by_type.at(it.first) : 0,
|
||||
local_area_cells_by_type.count(it.first) ? local_area_cells_by_type.at(it.first) : 0, it.second,
|
||||
area_cells_by_type.at(it.first), 1, print_area, print_hierarchical, print_global_only);
|
||||
|
|
@ -533,7 +531,7 @@ struct statdata_t {
|
|||
print_global_only);
|
||||
for (auto &it : num_submodules_by_type)
|
||||
if (it.second)
|
||||
print_log_line(string(it.first.unescape()), it.second, 0, it.second,
|
||||
print_log_line(twines.unescaped_str(it.first), it.second, 0, it.second,
|
||||
submodules_area_by_type.count(it.first) ? submodules_area_by_type.at(it.first) : 0, 1,
|
||||
print_area, print_hierarchical, print_global_only);
|
||||
}
|
||||
|
|
@ -582,7 +580,7 @@ struct statdata_t {
|
|||
count_local, area_local);
|
||||
}
|
||||
|
||||
void log_data_json(const char *mod_name, bool first_module, bool hierarchical = false, bool global_only = false)
|
||||
void log_data_json(const TwinePool& twines, const char *mod_name, bool first_module, bool hierarchical = false, bool global_only = false)
|
||||
{
|
||||
if (!first_module)
|
||||
log(",\n");
|
||||
|
|
@ -607,7 +605,7 @@ struct statdata_t {
|
|||
if (it.second) {
|
||||
if (!first_line)
|
||||
log(",\n");
|
||||
log(" %s: %s", json11::Json(it.first.unescape()).dump(),
|
||||
log(" %s: %s", json11::Json(twines.unescaped_str(it.first)).dump(),
|
||||
json_line(local_num_cells_by_type.count(it.first) ? local_num_cells_by_type.at(it.first) : 0,
|
||||
local_area_cells_by_type.count(it.first) ? local_area_cells_by_type.at(it.first) : 0, it.second,
|
||||
area_cells_by_type.at(it.first))
|
||||
|
|
@ -621,7 +619,7 @@ struct statdata_t {
|
|||
if (it.second) {
|
||||
if (!first_line)
|
||||
log(",\n");
|
||||
log(" %s: %s", json11::Json(it.first.unescape()).dump(),
|
||||
log(" %s: %s", json11::Json(twines.unescaped_str(it.first)).dump(),
|
||||
json_line(0, 0, it.second,
|
||||
submodules_area_by_type.count(it.first) ? submodules_area_by_type.at(it.first) : 0)
|
||||
.c_str());
|
||||
|
|
@ -662,14 +660,14 @@ struct statdata_t {
|
|||
if (it.second) {
|
||||
if (!first_line)
|
||||
log(",\n");
|
||||
log(" %s: %u", json11::Json(it.first.unescape()).dump(), it.second);
|
||||
log(" %s: %u", json11::Json(twines.unescaped_str(it.first)).dump(), it.second);
|
||||
first_line = false;
|
||||
}
|
||||
for (auto &it : num_submodules_by_type)
|
||||
if (it.second) {
|
||||
if (!first_line)
|
||||
log(",\n");
|
||||
log(" %s: %u", json11::Json(it.first.unescape()).dump(), it.second);
|
||||
log(" %s: %u", json11::Json(twines.unescaped_str(it.first)).dump(), it.second);
|
||||
first_line = false;
|
||||
}
|
||||
log("\n");
|
||||
|
|
@ -697,14 +695,14 @@ struct statdata_t {
|
|||
if (it.second) {
|
||||
if (!first_line)
|
||||
log(",\n");
|
||||
log(" %s: %u", json11::Json(it.first.unescape()).dump(), it.second);
|
||||
log(" %s: %u", json11::Json(twines.unescaped_str(it.first)).dump(), it.second);
|
||||
first_line = false;
|
||||
}
|
||||
for (auto &it : num_submodules_by_type)
|
||||
if (it.second) {
|
||||
if (!first_line)
|
||||
log(",\n");
|
||||
log(" %s: %u", json11::Json(it.first.unescape()).dump(), it.second);
|
||||
log(" %s: %u", json11::Json(twines.unescaped_str(it.first)).dump(), it.second);
|
||||
first_line = false;
|
||||
}
|
||||
log("\n");
|
||||
|
|
@ -726,7 +724,7 @@ struct statdata_t {
|
|||
}
|
||||
};
|
||||
|
||||
statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTLIL::IdString mod, int level, bool quiet = false, bool has_area = true,
|
||||
statdata_t hierarchy_worker(const TwinePool& twines, std::map<TwineRef, statdata_t> &mod_stat, TwineRef mod, int level, bool quiet = false, bool has_area = true,
|
||||
bool hierarchy_mode = true)
|
||||
{
|
||||
statdata_t mod_data = mod_stat.at(mod);
|
||||
|
|
@ -734,60 +732,60 @@ statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTL
|
|||
for (auto &it : mod_data.num_submodules_by_type) {
|
||||
if (mod_stat.count(it.first) > 0) {
|
||||
if (!quiet)
|
||||
mod_data.print_log_line(string(it.first.unescape()), mod_stat.at(it.first).local_num_cells,
|
||||
mod_data.print_log_line(twines.unescaped_str(it.first), mod_stat.at(it.first).local_num_cells,
|
||||
mod_stat.at(it.first).local_area, mod_stat.at(it.first).num_cells, mod_stat.at(it.first).area,
|
||||
level, has_area, hierarchy_mode);
|
||||
hierarchy_worker(mod_stat, it.first, level + 1, quiet, has_area, hierarchy_mode) * it.second;
|
||||
hierarchy_worker(twines, mod_stat, it.first, level + 1, quiet, has_area, hierarchy_mode) * it.second;
|
||||
}
|
||||
}
|
||||
|
||||
return mod_data;
|
||||
}
|
||||
|
||||
statdata_t hierarchy_builder(RTLIL::Design *design, const RTLIL::Module *top_mod, std::map<RTLIL::IdString, statdata_t> &mod_stat,
|
||||
bool width_mode, dict<IdString, cell_area_t> &cell_area, string techname)
|
||||
statdata_t hierarchy_builder(RTLIL::Design *design, const RTLIL::Module *top_mod, std::map<TwineRef, statdata_t> &mod_stat,
|
||||
bool width_mode, dict<TwineRef, cell_area_t> &cell_area, string techname)
|
||||
{
|
||||
if (top_mod == nullptr)
|
||||
top_mod = design->top_module();
|
||||
statdata_t mod_data(design, top_mod, width_mode, cell_area, techname);
|
||||
for (auto cell : top_mod->selected_cells()) {
|
||||
if (cell_area.count(cell->type) == 0) {
|
||||
if (design->has(cell->type)) {
|
||||
if (cell_area.count(cell->type_impl) == 0) {
|
||||
if (design->has(cell->type_impl)) {
|
||||
if (!(design->module(cell->type)->attributes.count(ID::blackbox))) {
|
||||
// deal with modules
|
||||
mod_data.add(
|
||||
hierarchy_builder(design, design->module(cell->type), mod_stat, width_mode, cell_area, techname));
|
||||
mod_data.num_submodules_by_type[cell->type]++;
|
||||
mod_data.submodules_area_by_type[cell->type] += mod_stat.at(cell->type).area;
|
||||
mod_data.submodule_area += mod_stat.at(cell->type).area;
|
||||
mod_data.num_submodules_by_type[cell->type_impl]++;
|
||||
mod_data.submodules_area_by_type[cell->type_impl] += mod_stat.at(cell->type_impl).area;
|
||||
mod_data.submodule_area += mod_stat.at(cell->type_impl).area;
|
||||
mod_data.num_submodules++;
|
||||
mod_data.unknown_cell_area.erase(cell->type);
|
||||
mod_data.unknown_cell_area.erase(cell->type_impl);
|
||||
mod_data.num_cells -=
|
||||
(mod_data.num_cells_by_type.count(cell->type) != 0) ? mod_data.num_cells_by_type.at(cell->type) : 0;
|
||||
mod_data.num_cells_by_type.erase(cell->type);
|
||||
mod_data.local_num_cells -= (mod_data.local_num_cells_by_type.count(cell->type) != 0)
|
||||
? mod_data.local_num_cells_by_type.at(cell->type)
|
||||
(mod_data.num_cells_by_type.count(cell->type_impl) != 0) ? mod_data.num_cells_by_type.at(cell->type_impl) : 0;
|
||||
mod_data.num_cells_by_type.erase(cell->type_impl);
|
||||
mod_data.local_num_cells -= (mod_data.local_num_cells_by_type.count(cell->type_impl) != 0)
|
||||
? mod_data.local_num_cells_by_type.at(cell->type_impl)
|
||||
: 0;
|
||||
mod_data.local_num_cells_by_type.erase(cell->type);
|
||||
mod_data.local_area_cells_by_type.erase(cell->type);
|
||||
mod_data.local_num_cells_by_type.erase(cell->type_impl);
|
||||
mod_data.local_area_cells_by_type.erase(cell->type_impl);
|
||||
} else {
|
||||
// deal with blackbox cells
|
||||
if (design->module(cell->type)->attributes.count(ID::area) &&
|
||||
design->module(cell->type)->attributes.at(ID::area).size() == 0) {
|
||||
mod_data.num_submodules_by_type[cell->type]++;
|
||||
mod_data.num_submodules_by_type[cell->type_impl]++;
|
||||
mod_data.num_submodules++;
|
||||
mod_data.submodules_area_by_type[cell->type] +=
|
||||
double(design->module(cell->type)->attributes.at(ID::area).as_int());
|
||||
mod_data.area += double(design->module(cell->type)->attributes.at(ID::area).as_int());
|
||||
mod_data.unknown_cell_area.erase(cell->type);
|
||||
mod_data.submodules_area_by_type[cell->type_impl] +=
|
||||
double(design->module(cell->type_impl)->attributes.at(ID::area).as_int());
|
||||
mod_data.area += double(design->module(cell->type_impl)->attributes.at(ID::area).as_int());
|
||||
mod_data.unknown_cell_area.erase(cell->type_impl);
|
||||
mod_data.num_cells -=
|
||||
(mod_data.num_cells_by_type.count(cell->type) != 0) ? mod_data.num_cells_by_type.at(cell->type) : 0;
|
||||
mod_data.num_cells_by_type.erase(cell->type);
|
||||
mod_data.local_num_cells -= (mod_data.local_num_cells_by_type.count(cell->type) != 0)
|
||||
? mod_data.local_num_cells_by_type.at(cell->type)
|
||||
(mod_data.num_cells_by_type.count(cell->type_impl) != 0) ? mod_data.num_cells_by_type.at(cell->type_impl) : 0;
|
||||
mod_data.num_cells_by_type.erase(cell->type_impl);
|
||||
mod_data.local_num_cells -= (mod_data.local_num_cells_by_type.count(cell->type_impl) != 0)
|
||||
? mod_data.local_num_cells_by_type.at(cell->type_impl)
|
||||
: 0;
|
||||
mod_data.local_num_cells_by_type.erase(cell->type);
|
||||
mod_data.local_area_cells_by_type.erase(cell->type);
|
||||
mod_data.local_num_cells_by_type.erase(cell->type_impl);
|
||||
mod_data.local_area_cells_by_type.erase(cell->type_impl);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -797,7 +795,7 @@ statdata_t hierarchy_builder(RTLIL::Design *design, const RTLIL::Module *top_mod
|
|||
return mod_data;
|
||||
}
|
||||
|
||||
void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_area, string liberty_file)
|
||||
void read_liberty_cellarea(TwinePool& twines, dict<TwineRef, cell_area_t> &cell_area, string liberty_file)
|
||||
{
|
||||
std::istream *f = uncompressed(liberty_file.c_str());
|
||||
yosys_input_files.insert(liberty_file);
|
||||
|
|
@ -874,7 +872,8 @@ void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_area, string libert
|
|||
|
||||
if (ar != nullptr && !ar->value.empty()) {
|
||||
string prefix = cell->args[0].substr(0, 1) == "$" ? "" : "\\";
|
||||
cell_area[prefix + cell->args[0]] = {atof(ar->value.c_str()), is_flip_flop, single_parameter_area, double_parameter_area,
|
||||
TwineRef t = twines.add(Twine{prefix + cell->args[0]});
|
||||
cell_area[t] = {atof(ar->value.c_str()), is_flip_flop, single_parameter_area, double_parameter_area,
|
||||
port_names};
|
||||
}
|
||||
}
|
||||
|
|
@ -927,8 +926,8 @@ struct StatPass : public Pass {
|
|||
{
|
||||
bool width_mode = false, json_mode = false, hierarchy_mode = false;
|
||||
RTLIL::Module *top_mod = nullptr;
|
||||
std::map<RTLIL::IdString, statdata_t> mod_stat;
|
||||
dict<IdString, cell_area_t> cell_area;
|
||||
std::map<TwineRef, statdata_t> mod_stat;
|
||||
dict<TwineRef, cell_area_t> cell_area;
|
||||
string techname;
|
||||
|
||||
size_t argidx;
|
||||
|
|
@ -940,7 +939,7 @@ struct StatPass : public Pass {
|
|||
if (args[argidx] == "-liberty" && argidx + 1 < args.size()) {
|
||||
string liberty_file = args[++argidx];
|
||||
rewrite_filename(liberty_file);
|
||||
read_liberty_cellarea(cell_area, liberty_file);
|
||||
read_liberty_cellarea(design->twines, cell_area, liberty_file);
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-tech" && argidx + 1 < args.size()) {
|
||||
|
|
@ -1005,13 +1004,13 @@ struct StatPass : public Pass {
|
|||
top_mod = mod;
|
||||
statdata_t data = mod_stat.at(mod->name);
|
||||
if (json_mode) {
|
||||
data.log_data_json(mod->name.c_str(), first_module, hierarchy_mode);
|
||||
data.log_data_json(design->twines, mod->name.c_str(), first_module, hierarchy_mode);
|
||||
first_module = false;
|
||||
} else {
|
||||
log("\n");
|
||||
log("=== %s%s ===\n", mod->name.unescape(), mod->is_selected_whole() ? "" : " (partially selected)");
|
||||
log("=== %s%s ===\n", design->twines.unescaped_str(mod->name), mod->is_selected_whole() ? "" : " (partially selected)");
|
||||
log("\n");
|
||||
data.log_data(mod->name, false, has_area, hierarchy_mode);
|
||||
data.log_data(design->twines, mod->name, false, has_area, hierarchy_mode);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1031,13 +1030,13 @@ struct StatPass : public Pass {
|
|||
mod_stat[top_mod->name].area, 0, has_area, hierarchy_mode, true);
|
||||
}
|
||||
|
||||
statdata_t data = hierarchy_worker(mod_stat, top_mod->name, 0, /*quiet=*/json_mode, has_area, hierarchy_mode);
|
||||
statdata_t data = hierarchy_worker(design->twines, mod_stat, top_mod->name, 0, /*quiet=*/json_mode, has_area, hierarchy_mode);
|
||||
|
||||
if (json_mode)
|
||||
data.log_data_json("design", true, hierarchy_mode, true);
|
||||
data.log_data_json(design->twines, "design", true, hierarchy_mode, true);
|
||||
else if (GetSize(mod_stat) > 1) {
|
||||
log("\n");
|
||||
data.log_data(top_mod->name, true, has_area, hierarchy_mode, true);
|
||||
data.log_data(design->twines, top_mod->name, true, has_area, hierarchy_mode, true);
|
||||
}
|
||||
|
||||
design->scratchpad_set_int("stat.num_wires", data.num_wires);
|
||||
|
|
|
|||
|
|
@ -17,12 +17,12 @@ struct TestPatchPass : public Pass {
|
|||
for (auto module : design->selected_modules()) {
|
||||
SigMap sigmap(module);
|
||||
for (auto cell : module->selected_cells()) {
|
||||
if (cell->type == ID($add)) {
|
||||
if (cell->type == TW($add)) {
|
||||
Cell* add = cell;
|
||||
log_assert(add->getPort(TW::B).is_wire());
|
||||
log_assert(add->getPort(TW::B).known_driver());
|
||||
auto neg = add->getPort(TW::B)[0].wire->driverCell();
|
||||
log_assert(neg->type == ID($not));
|
||||
log_assert(neg->type == TW($not));
|
||||
RTLIL::Patch patcher(module, nullptr);
|
||||
int width = cell->getPort(TW::A).size();
|
||||
auto sub = patcher.addSub(NEW_TWINE,
|
||||
|
|
|
|||
|
|
@ -66,8 +66,8 @@ struct EstimateSta {
|
|||
// and to account for the AIG model not being balanced
|
||||
int cell_type_factor(IdString type)
|
||||
{
|
||||
if (type.in(ID($gt), ID($ge), ID($lt), ID($le), ID($add), ID($sub),
|
||||
ID($logic_not), ID($reduce_and), ID($reduce_or), ID($eq)))
|
||||
if (type.in(TW($gt), TW($ge), TW($lt), TW($le), TW($add), TW($sub),
|
||||
TW($logic_not), TW($reduce_and), TW($reduce_or), TW($eq)))
|
||||
return 1;
|
||||
else
|
||||
return 2;
|
||||
|
|
@ -97,7 +97,7 @@ struct EstimateSta {
|
|||
FfData ff(nullptr, cell);
|
||||
if (!ff.has_clk) {
|
||||
log_warning("Ignoring unsupported storage element '%s' (%s)\n",
|
||||
cell, cell->type.unescape());
|
||||
cell, cell->type.unescaped());
|
||||
continue;
|
||||
}
|
||||
if (!clk || ff.sig_clk.as_bit() != *clk)
|
||||
|
|
@ -112,7 +112,7 @@ struct EstimateSta {
|
|||
} else if (cell->is_mem_cell()) {
|
||||
// memories handled separately
|
||||
continue;
|
||||
} else if (cell->type == ID($scopeinfo)) {
|
||||
} else if (cell->type == TW($scopeinfo)) {
|
||||
continue;
|
||||
} else {
|
||||
// find or build AIG model of combinational cell
|
||||
|
|
@ -121,7 +121,7 @@ struct EstimateSta {
|
|||
aigs.emplace(fingerprint, Aig(cell));
|
||||
if (aigs.at(fingerprint).name.empty()) {
|
||||
log_error("Unsupported cell '%s' in module '%s'",
|
||||
cell->type.unescape(), m);
|
||||
cell->type.unescaped(), m);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -342,7 +342,7 @@ struct EstimateSta {
|
|||
std::string src_attr = cell->get_src_attribute();
|
||||
cell_src = stringf(" source: %s", src_attr);
|
||||
}
|
||||
log(" cell %s (%s)%s\n", cell, cell->type.unescape(), cell_src);
|
||||
log(" cell %s (%s)%s\n", cell, cell->type.unescaped(), cell_src);
|
||||
printed.insert(cell);
|
||||
}
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -83,13 +83,13 @@ struct TorderPass : public Pass {
|
|||
for (auto cell : module->selected_cells())
|
||||
for (auto conn : cell->connections())
|
||||
{
|
||||
if (stop_db.count(cell->type) && stop_db.at(cell->type).count(conn.first))
|
||||
if (stop_db.count(RTLIL::IdString(cell->type)) && stop_db.at(RTLIL::IdString(cell->type)).count(RTLIL::IdString(design->twines.str(conn.first))))
|
||||
continue;
|
||||
|
||||
if (!noautostop && yosys_celltypes.cell_known(cell->type)) {
|
||||
if (!noautostop && yosys_celltypes.cell_known(cell->type.ref())) {
|
||||
if (conn.first.in(ID::Q, ID::CTRL_OUT, ID::RD_DATA))
|
||||
continue;
|
||||
if (cell->type.in(ID($memrd), ID($memrd_v2)) && conn.first == ID::DATA)
|
||||
if (cell->type.in(TW($memrd), TW($memrd_v2)) && conn.first == ID::DATA)
|
||||
continue;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ struct TraceMonitor : public RTLIL::Monitor
|
|||
|
||||
void notify_connect(RTLIL::Cell *cell, TwineRef port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
|
||||
{
|
||||
log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", cell->module, cell, port.unescape(), log_signal(sig), log_signal(old_sig));
|
||||
log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", cell->module, cell, cell->module->design->twines.unescaped_str(port).c_str(), log_signal(sig), log_signal(old_sig));
|
||||
}
|
||||
|
||||
void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) override
|
||||
|
|
|
|||
|
|
@ -309,12 +309,12 @@ struct Graph {
|
|||
{
|
||||
GraphNode *g = nullptr;
|
||||
|
||||
if (!grp.second.selected_module(module->name))
|
||||
if (!grp.second.selected_module(module->meta_->name))
|
||||
continue;
|
||||
|
||||
for (auto wire : module->wires()) {
|
||||
if (!wire->name.isPublic()) continue;
|
||||
if (!grp.second.selected_member(module->name, wire->name)) continue;
|
||||
if (!grp.second.selected_member(module->meta_->name, wire->name.ref())) continue;
|
||||
for (auto bit : sigmap(wire)) {
|
||||
auto it = wire_nodes.find(bit);
|
||||
if (it == wire_nodes.end())
|
||||
|
|
@ -708,8 +708,8 @@ struct VizWorker
|
|||
c->attributes.erase(vg_id);
|
||||
for (auto g : graph.nodes) {
|
||||
for (auto name : g->names()) {
|
||||
auto w = module->wire(name);
|
||||
auto c = module->cell(name);
|
||||
auto w = module->wire(module->design->twines.lookup(name.str()));
|
||||
auto c = module->cell(module->design->twines.lookup(name.str()));
|
||||
if (w) w->attributes[vg_id] = g->index;
|
||||
if (c) c->attributes[vg_id] = g->index;
|
||||
}
|
||||
|
|
@ -718,7 +718,7 @@ struct VizWorker
|
|||
|
||||
void write_dot(FILE *f)
|
||||
{
|
||||
fprintf(f, "digraph \"%s\" {\n", module->name.unescape().c_str());
|
||||
fprintf(f, "digraph \"%s\" {\n", design->twines.unescaped_str(module->name).c_str());
|
||||
fprintf(f, " rankdir = LR;\n");
|
||||
|
||||
dict<GraphNode*, std::vector<std::vector<std::string>>> extra_lines;
|
||||
|
|
@ -782,7 +782,7 @@ struct VizWorker
|
|||
g->names().sort();
|
||||
std::string label; // = stringf("vg=%d\\n", g->index);
|
||||
for (auto n : g->names())
|
||||
label = label + (label.empty() ? "" : "\\n") + n.unescape();
|
||||
label = label + (label.empty() ? "" : "\\n") + design->twines.unescaped_str(n);
|
||||
fprintf(f, "\tn%d [shape=rectangle,label=\"%s\"];\n", g->index, label.c_str());
|
||||
} else {
|
||||
std::string label = stringf("vg=%d | %d cells", g->index, GetSize(g->names()));
|
||||
|
|
|
|||
|
|
@ -208,13 +208,13 @@ struct WrapcellPass : Pass {
|
|||
Module *subm;
|
||||
Cell *subcell;
|
||||
|
||||
if (!ct.cell_known(cell->type))
|
||||
if (!ct.cell_known(cell->type_impl))
|
||||
log_error("Non-internal cell type '%s' on cell '%s' in module '%s' unsupported\n",
|
||||
cell->type.unescape(), cell, module);
|
||||
cell->type.unescaped(), cell, module);
|
||||
|
||||
std::vector<std::pair<IdString, int>> unused_outputs, used_outputs;
|
||||
for (auto conn : cell->connections()) {
|
||||
if (ct.cell_output(cell->type, conn.first))
|
||||
if (ct.cell_output(cell->type_impl, conn.first))
|
||||
for (int i = 0; i < conn.second.size(); i++) {
|
||||
if (tracking_unused && unused.check(conn.second[i]))
|
||||
unused_outputs.emplace_back(conn.first, i);
|
||||
|
|
@ -227,7 +227,7 @@ struct WrapcellPass : Pass {
|
|||
if (!unused_outputs.empty()) {
|
||||
context.unused_outputs += "_unused";
|
||||
for (auto chunk : collect_chunks(unused_outputs))
|
||||
context.unused_outputs += "_" + chunk.format(cell).unescape();
|
||||
context.unused_outputs += "_" + design->twines.unescaped_str(chunk.format(cell));
|
||||
}
|
||||
|
||||
std::optional<std::string> unescaped_name = format_with_params(name_fmt, cell->parameters, context);
|
||||
|
|
@ -242,7 +242,7 @@ struct WrapcellPass : Pass {
|
|||
subm = d->addModule(name);
|
||||
subcell = subm->addCell("$1", cell->type);
|
||||
for (auto conn : cell->connections()) {
|
||||
if (ct.cell_output(cell->type, conn.first)) {
|
||||
if (ct.cell_output(cell->type_impl, conn.first)) {
|
||||
// Insert marker bits as placehodlers which need to be replaced
|
||||
subcell->setPort(conn.first, SigSpec(RTLIL::Sm, conn.second.size()));
|
||||
} else {
|
||||
|
|
@ -286,7 +286,7 @@ struct WrapcellPass : Pass {
|
|||
dict<IdString, SigSpec> new_connections;
|
||||
|
||||
for (auto conn : cell->connections())
|
||||
if (!ct.cell_output(cell->type, conn.first))
|
||||
if (!ct.cell_output(cell->type_impl, conn.first))
|
||||
new_connections[conn.first] = conn.second;
|
||||
|
||||
for (auto chunk : collect_chunks(used_outputs))
|
||||
|
|
|
|||
|
|
@ -294,18 +294,18 @@ struct XpropWorker
|
|||
}
|
||||
|
||||
void mark_maybe_x(Cell *cell) {
|
||||
if (cell->type.in(ID($bweqx), ID($eqx), ID($nex), ID($initstate), ID($assert), ID($assume), ID($cover), ID($anyseq), ID($anyconst)))
|
||||
if (cell->type.in(TW($bweqx), TW($eqx), TW($nex), TW($initstate), TW($assert), TW($assume), TW($cover), TW($anyseq), TW($anyconst)))
|
||||
return;
|
||||
|
||||
if (cell->type.in(ID($pmux))) {
|
||||
if (cell->type.in(TW($pmux))) {
|
||||
mark_outputs_maybe_x(cell);
|
||||
return;
|
||||
}
|
||||
|
||||
if (cell->is_builtin_ff() || cell->type == ID($anyinit)) {
|
||||
if (cell->is_builtin_ff() || cell->type == TW($anyinit)) {
|
||||
FfData ff(&initvals, cell);
|
||||
|
||||
if (cell->type != ID($anyinit))
|
||||
if (cell->type != TW($anyinit))
|
||||
for (int i = 0; i < ff.width; i++)
|
||||
if (ff.val_init[i] == State::Sx)
|
||||
mark_maybe_x(ff.sig_q[i]);
|
||||
|
|
@ -318,7 +318,7 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type == ID($not)) {
|
||||
if (cell->type == TW($not)) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto sig_a = cell->getPort(TW::A); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
|
||||
for (int i = 0; i < GetSize(sig_y); i++)
|
||||
|
|
@ -327,7 +327,7 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
|
||||
if (cell->type.in(TW($and), TW($or), TW($xor), TW($xnor))) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto sig_a = cell->getPort(TW::A); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
|
||||
auto sig_b = cell->getPort(TW::B); sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
|
||||
|
|
@ -337,7 +337,7 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($bwmux))) {
|
||||
if (cell->type.in(TW($bwmux))) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto &sig_a = cell->getPort(TW::A);
|
||||
auto &sig_b = cell->getPort(TW::B);
|
||||
|
|
@ -348,7 +348,7 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($_MUX_), ID($mux), ID($bmux))) {
|
||||
if (cell->type.in(TW($_MUX_), TW($mux), TW($bmux))) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto &sig_a = cell->getPort(TW::A);
|
||||
auto &sig_b = cell->getPort(TW::B);
|
||||
|
|
@ -372,7 +372,7 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($demux))) {
|
||||
if (cell->type.in(TW($demux))) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto &sig_a = cell->getPort(TW::A);
|
||||
auto &sig_s = cell->getPort(TW::S);
|
||||
|
|
@ -387,7 +387,7 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift))) {
|
||||
if (cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift))) {
|
||||
auto &sig_b = cell->getPort(TW::B);
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
|
||||
|
|
@ -407,7 +407,7 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($shiftx))) {
|
||||
if (cell->type.in(TW($shiftx))) {
|
||||
auto &sig_b = cell->getPort(TW::B);
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
|
||||
|
|
@ -438,24 +438,24 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($add), ID($sub), ID($mul), ID($neg))) {
|
||||
if (cell->type.in(TW($add), TW($sub), TW($mul), TW($neg))) {
|
||||
if (inputs_maybe_x(cell))
|
||||
mark_outputs_maybe_x(cell);
|
||||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
|
||||
if (cell->type.in(TW($div), TW($mod), TW($divfloor), TW($modfloor))) {
|
||||
mark_outputs_maybe_x(cell);
|
||||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(
|
||||
ID($le), ID($lt), ID($ge), ID($gt),
|
||||
ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor),
|
||||
ID($reduce_bool), ID($logic_not), ID($logic_or), ID($logic_and),
|
||||
ID($eq), ID($ne),
|
||||
TW($le), TW($lt), TW($ge), TW($gt),
|
||||
TW($reduce_and), TW($reduce_or), TW($reduce_xor), TW($reduce_xnor),
|
||||
TW($reduce_bool), TW($logic_not), TW($logic_or), TW($logic_and),
|
||||
TW($eq), TW($ne),
|
||||
|
||||
ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_ANDNOT_), ID($_OR_), ID($_NOR_), ID($_ORNOT_), ID($_XOR_), ID($_XNOR_)
|
||||
TW($_NOT_), TW($_AND_), TW($_NAND_), TW($_ANDNOT_), TW($_OR_), TW($_NOR_), TW($_ORNOT_), TW($_XOR_), TW($_XNOR_)
|
||||
)) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
if (inputs_maybe_x(cell))
|
||||
|
|
@ -463,11 +463,11 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($scopeinfo))) {
|
||||
if (cell->type.in(TW($scopeinfo))) {
|
||||
return;
|
||||
}
|
||||
|
||||
log_warning("Unhandled cell %s (%s) during maybe-x marking\n", cell, cell->type.unescape());
|
||||
log_warning("Unhandled cell %s (%s) during maybe-x marking\n", cell, cell->type.unescaped());
|
||||
mark_outputs_maybe_x(cell);
|
||||
}
|
||||
|
||||
|
|
@ -481,7 +481,7 @@ struct XpropWorker
|
|||
{
|
||||
if (!ports_maybe_x(cell)) {
|
||||
|
||||
if (cell->type == ID($bweq)) {
|
||||
if (cell->type == TW($bweq)) {
|
||||
auto sig_y = cell->getPort(TW::Y);
|
||||
auto sig_a = cell->getPort(TW::A);
|
||||
auto sig_b = cell->getPort(TW::B);
|
||||
|
|
@ -492,7 +492,7 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($nex), ID($eqx))) {
|
||||
if (cell->type.in(TW($nex), TW($eqx))) {
|
||||
auto sig_y = cell->getPort(TW::Y);
|
||||
auto sig_a = cell->getPort(TW::A);
|
||||
auto sig_b = cell->getPort(TW::B);
|
||||
|
|
@ -500,7 +500,7 @@ struct XpropWorker
|
|||
RTLIL::IdString name(cell->name);
|
||||
auto type = cell->type;
|
||||
module->remove(cell);
|
||||
if (type == ID($eqx))
|
||||
if (type == TW($eqx))
|
||||
module->addEq(name, sig_a, sig_b, sig_y);
|
||||
else
|
||||
module->addNe(name, sig_a, sig_b, sig_y);
|
||||
|
|
@ -510,10 +510,10 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($not), ID($_NOT_))) {
|
||||
if (cell->type.in(TW($not), TW($_NOT_))) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto sig_a = cell->getPort(TW::A);
|
||||
if (cell->type == ID($not))
|
||||
if (cell->type == TW($not))
|
||||
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
|
||||
|
||||
auto enc_a = encoded(sig_a);
|
||||
|
|
@ -527,11 +527,11 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($and), ID($or), ID($_AND_), ID($_OR_), ID($_NAND_), ID($_NOR_), ID($_ANDNOT_), ID($_ORNOT_))) {
|
||||
if (cell->type.in(TW($and), TW($or), TW($_AND_), TW($_OR_), TW($_NAND_), TW($_NOR_), TW($_ANDNOT_), TW($_ORNOT_))) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto sig_a = cell->getPort(TW::A);
|
||||
auto sig_b = cell->getPort(TW::B);
|
||||
if (cell->type.in(ID($and), ID($or))) {
|
||||
if (cell->type.in(TW($and), TW($or))) {
|
||||
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
|
||||
sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
|
||||
}
|
||||
|
|
@ -540,11 +540,11 @@ struct XpropWorker
|
|||
auto enc_b = encoded(sig_b);
|
||||
auto enc_y = encoded(sig_y, true);
|
||||
|
||||
if (cell->type.in(ID($or), ID($_OR_), ID($_NOR_), ID($_ORNOT_)))
|
||||
if (cell->type.in(TW($or), TW($_OR_), TW($_NOR_), TW($_ORNOT_)))
|
||||
enc_a.invert(), enc_b.invert(), enc_y.invert();
|
||||
if (cell->type.in(ID($_NAND_), ID($_NOR_)))
|
||||
if (cell->type.in(TW($_NAND_), TW($_NOR_)))
|
||||
enc_y.invert();
|
||||
if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
|
||||
if (cell->type.in(TW($_ANDNOT_), TW($_ORNOT_)))
|
||||
enc_b.invert();
|
||||
|
||||
enc_y.connect_0(module->Or(NEW_TWINE, enc_a.is_0, enc_b.is_0));
|
||||
|
|
@ -554,7 +554,7 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($logic_not))) {
|
||||
if (cell->type.in(TW($reduce_and), TW($reduce_or), TW($reduce_bool), TW($logic_not))) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto &sig_a = cell->getPort(TW::A);
|
||||
|
||||
|
|
@ -563,9 +563,9 @@ struct XpropWorker
|
|||
|
||||
enc_y.connect_as_bool();
|
||||
|
||||
if (cell->type.in(ID($reduce_or), ID($reduce_bool)))
|
||||
if (cell->type.in(TW($reduce_or), TW($reduce_bool)))
|
||||
enc_a.invert(), enc_y.invert();
|
||||
if (cell->type == ID($logic_not))
|
||||
if (cell->type == TW($logic_not))
|
||||
enc_a.invert();
|
||||
|
||||
enc_y.connect_0(module->ReduceOr(NEW_TWINE, enc_a.is_0));
|
||||
|
|
@ -576,7 +576,7 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
|
||||
if (cell->type.in(TW($reduce_xor), TW($reduce_xnor))) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto &sig_a = cell->getPort(TW::A);
|
||||
|
||||
|
|
@ -584,7 +584,7 @@ struct XpropWorker
|
|||
auto enc_y = encoded(sig_y, true);
|
||||
|
||||
enc_y.connect_as_bool();
|
||||
if (cell->type == ID($reduce_xnor))
|
||||
if (cell->type == TW($reduce_xnor))
|
||||
enc_y.invert();
|
||||
|
||||
|
||||
|
|
@ -596,7 +596,7 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($logic_and), ID($logic_or))) {
|
||||
if (cell->type.in(TW($logic_and), TW($logic_or))) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto &sig_a = cell->getPort(TW::A);
|
||||
auto &sig_b = cell->getPort(TW::B);
|
||||
|
|
@ -612,7 +612,7 @@ struct XpropWorker
|
|||
auto b_is_1 = module->ReduceOr(NEW_TWINE, enc_b.is_1);
|
||||
auto b_is_0 = module->ReduceAnd(NEW_TWINE, enc_b.is_0);
|
||||
|
||||
if (cell->type == ID($logic_or))
|
||||
if (cell->type == TW($logic_or))
|
||||
enc_y.invert(), std::swap(a_is_0, a_is_1), std::swap(b_is_0, b_is_1);
|
||||
|
||||
enc_y.connect_0(module->Or(NEW_TWINE, a_is_0, b_is_0));
|
||||
|
|
@ -622,11 +622,11 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($xor), ID($xnor), ID($_XOR_), ID($_XNOR_))) {
|
||||
if (cell->type.in(TW($xor), TW($xnor), TW($_XOR_), TW($_XNOR_))) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto sig_a = cell->getPort(TW::A);
|
||||
auto sig_b = cell->getPort(TW::B);
|
||||
if (cell->type.in(ID($xor), ID($xnor))) {
|
||||
if (cell->type.in(TW($xor), TW($xnor))) {
|
||||
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
|
||||
sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
|
||||
}
|
||||
|
|
@ -635,7 +635,7 @@ struct XpropWorker
|
|||
auto enc_b = encoded(sig_b);
|
||||
auto enc_y = encoded(sig_y, true);
|
||||
|
||||
if (cell->type.in(ID($xnor), ID($_XNOR_)))
|
||||
if (cell->type.in(TW($xnor), TW($_XNOR_)))
|
||||
enc_y.invert();
|
||||
|
||||
enc_y.connect_x(module->Or(NEW_TWINE, enc_a.is_x, enc_b.is_x));
|
||||
|
|
@ -645,7 +645,7 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($eq), ID($ne))) {
|
||||
if (cell->type.in(TW($eq), TW($ne))) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto sig_a = cell->getPort(TW::A);
|
||||
auto sig_b = cell->getPort(TW::B);
|
||||
|
|
@ -658,7 +658,7 @@ struct XpropWorker
|
|||
auto enc_y = encoded(sig_y, true);
|
||||
enc_y.connect_as_bool();
|
||||
|
||||
if (cell->type == ID($ne))
|
||||
if (cell->type == TW($ne))
|
||||
enc_y.invert();
|
||||
|
||||
auto delta = module->Xor(NEW_TWINE, enc_a.is_1, enc_b.is_1);
|
||||
|
|
@ -671,7 +671,7 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($eqx), ID($nex))) {
|
||||
if (cell->type.in(TW($eqx), TW($nex))) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto sig_a = cell->getPort(TW::A);
|
||||
auto sig_b = cell->getPort(TW::B);
|
||||
|
|
@ -687,7 +687,7 @@ struct XpropWorker
|
|||
|
||||
auto eq = module->ReduceAnd(NEW_TWINE, {delta_0, delta_1});
|
||||
|
||||
auto res = cell->type == ID($nex) ? module->Not(NEW_TWINE, eq) : eq;
|
||||
auto res = cell->type == TW($nex) ? module->Not(NEW_TWINE, eq) : eq;
|
||||
|
||||
module->connect(sig_y[0], res);
|
||||
if (GetSize(sig_y) > 1)
|
||||
|
|
@ -696,7 +696,7 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($bweqx))) {
|
||||
if (cell->type.in(TW($bweqx))) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto &sig_a = cell->getPort(TW::A);
|
||||
auto &sig_b = cell->getPort(TW::B);
|
||||
|
|
@ -711,13 +711,13 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($_MUX_), ID($mux), ID($bwmux))) {
|
||||
if (cell->type.in(TW($_MUX_), TW($mux), TW($bwmux))) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto &sig_a = cell->getPort(TW::A);
|
||||
auto &sig_b = cell->getPort(TW::B);
|
||||
auto sig_s = cell->getPort(TW::S);
|
||||
|
||||
if (cell->type == ID($mux))
|
||||
if (cell->type == TW($mux))
|
||||
sig_s = SigSpec(sig_s[0], GetSize(sig_y));
|
||||
|
||||
auto enc_a = encoded(sig_a);
|
||||
|
|
@ -736,7 +736,7 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($pmux))) {
|
||||
if (cell->type.in(TW($pmux))) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto &sig_a = cell->getPort(TW::A);
|
||||
auto &sig_b = cell->getPort(TW::B);
|
||||
|
|
@ -771,7 +771,7 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) {
|
||||
if (cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx))) {
|
||||
auto &sig_y = cell->getPort(TW::Y);
|
||||
auto &sig_a = cell->getPort(TW::A);
|
||||
auto &sig_b = cell->getPort(TW::B);
|
||||
|
|
@ -787,9 +787,9 @@ struct XpropWorker
|
|||
SigSpec y_1 = module->addWire(NEW_TWINE, GetSize(sig_y));
|
||||
SigSpec y_x = module->addWire(NEW_TWINE, GetSize(sig_y));
|
||||
|
||||
auto encoded_type = cell->type == ID($shiftx) ? ID($shift) : cell->type;
|
||||
auto encoded_type = cell->type == TW($shiftx) ? TW($shift) : cell->type;
|
||||
|
||||
if (cell->type == ID($shiftx)) {
|
||||
if (cell->type == TW($shiftx)) {
|
||||
std::swap(enc_a.is_0, enc_a.is_x);
|
||||
}
|
||||
|
||||
|
|
@ -813,7 +813,7 @@ struct XpropWorker
|
|||
|
||||
SigSpec y_0 = module->Not(NEW_TWINE, y_not_0);
|
||||
|
||||
if (cell->type == ID($shiftx))
|
||||
if (cell->type == TW($shiftx))
|
||||
std::swap(y_0, y_x);
|
||||
|
||||
enc_y.connect_0(module->And(NEW_TWINE, y_0, SigSpec(not_all_x, GetSize(sig_y))));
|
||||
|
|
@ -824,7 +824,7 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($ff))) {
|
||||
if (cell->type.in(TW($ff))) {
|
||||
auto &sig_d = cell->getPort(TW::D);
|
||||
auto &sig_q = cell->getPort(TW::Q);
|
||||
|
||||
|
|
@ -857,12 +857,12 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->is_builtin_ff() || cell->type == ID($anyinit)) {
|
||||
if (cell->is_builtin_ff() || cell->type == TW($anyinit)) {
|
||||
FfData ff(&initvals, cell);
|
||||
|
||||
if ((ff.has_clk || ff.has_gclk) && !ff.has_ce && !ff.has_aload && !ff.has_srst && !ff.has_arst && !ff.has_sr) {
|
||||
if (ff.has_clk && maybe_x(ff.sig_clk)) {
|
||||
log_warning("Only non-x CLK inputs are currently supported for %s (%s)\n", cell, cell->type.unescape());
|
||||
log_warning("Only non-x CLK inputs are currently supported for %s (%s)\n", cell, cell->type.unescaped());
|
||||
} else {
|
||||
auto init_q = ff.val_init;
|
||||
auto init_q_is_1 = init_q;
|
||||
|
|
@ -907,15 +907,15 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
} else {
|
||||
log_warning("Unhandled FF-cell %s (%s), consider running clk2fflogic, async2sync and/or dffunmap\n", cell, cell->type.unescape());
|
||||
log_warning("Unhandled FF-cell %s (%s), consider running clk2fflogic, async2sync and/or dffunmap\n", cell, cell->type.unescaped());
|
||||
}
|
||||
}
|
||||
|
||||
// Celltypes where any input x bit makes the whole output x
|
||||
if (cell->type.in(
|
||||
ID($neg),
|
||||
ID($le), ID($lt), ID($ge), ID($gt),
|
||||
ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor)
|
||||
TW($neg),
|
||||
TW($le), TW($lt), TW($ge), TW($gt),
|
||||
TW($add), TW($sub), TW($mul), TW($div), TW($mod), TW($divfloor), TW($modfloor)
|
||||
)) {
|
||||
|
||||
SigSpec inbits_x;
|
||||
|
|
@ -927,7 +927,7 @@ struct XpropWorker
|
|||
}
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
|
||||
if (cell->type.in(TW($div), TW($mod), TW($divfloor), TW($modfloor))) {
|
||||
auto sig_b = cell->getPort(TW::B);
|
||||
auto invalid = module->LogicNot(NEW_TWINE, sig_b);
|
||||
inbits_x.append(invalid);
|
||||
|
|
@ -937,7 +937,7 @@ struct XpropWorker
|
|||
|
||||
SigBit outbits_x = (GetSize(inbits_x) == 1 ? inbits_x : module->ReduceOr(NEW_TWINE, inbits_x));
|
||||
|
||||
bool bool_out = cell->type.in(ID($le), ID($lt), ID($ge), ID($gt));
|
||||
bool bool_out = cell->type.in(TW($le), TW($lt), TW($ge), TW($gt));
|
||||
|
||||
for (auto &conn : cell->connections()) {
|
||||
if (cell->output(conn.first)) {
|
||||
|
|
@ -958,15 +958,15 @@ struct XpropWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type == ID($bmux)) // TODO might want to support bmux natively anyway
|
||||
if (cell->type == TW($bmux)) // TODO might want to support bmux natively anyway
|
||||
log("Running 'bmuxmap' preserves x-propagation and can be run before 'xprop'.\n");
|
||||
if (cell->type == ID($demux)) // TODO might want to support demux natively anyway
|
||||
if (cell->type == TW($demux)) // TODO might want to support demux natively anyway
|
||||
log("Running 'demuxmap' preserves x-propagation and can be run before 'xprop'.\n");
|
||||
|
||||
if (options.required)
|
||||
log_error("Unhandled cell %s (%s)\n", cell, cell->type.unescape());
|
||||
log_error("Unhandled cell %s (%s)\n", cell, cell->type.unescaped());
|
||||
else
|
||||
log_warning("Unhandled cell %s (%s)\n", cell, cell->type.unescape());
|
||||
log_warning("Unhandled cell %s (%s)\n", cell, cell->type.unescaped());
|
||||
}
|
||||
|
||||
void split_ports()
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ struct EquivInductWorker : public EquivWorker<>
|
|||
if (!satgen.importCell(cell, step)) {
|
||||
report_missing_model(cfg.ignore_unknown_cells, cell);
|
||||
}
|
||||
if (cell->type == ID($equiv)) {
|
||||
if (cell->type == TW($equiv)) {
|
||||
SigBit bit_a = sigmap(cell->getPort(TW::A)).as_bit();
|
||||
SigBit bit_b = sigmap(cell->getPort(TW::B)).as_bit();
|
||||
if (bit_a != bit_b) {
|
||||
|
|
@ -88,14 +88,14 @@ struct EquivInductWorker : public EquivWorker<>
|
|||
|
||||
if (satgen.model_undef) {
|
||||
for (auto cell : cells)
|
||||
if (yosys_celltypes.cell_known(cell->type))
|
||||
if (yosys_celltypes.cell_known(cell->type_impl))
|
||||
for (auto &conn : cell->connections())
|
||||
if (yosys_celltypes.cell_input(cell->type, conn.first))
|
||||
if (yosys_celltypes.cell_input(cell->type_impl, conn.first))
|
||||
undriven_signals.add(sigmap(conn.second));
|
||||
for (auto cell : cells)
|
||||
if (yosys_celltypes.cell_known(cell->type))
|
||||
if (yosys_celltypes.cell_known(cell->type_impl))
|
||||
for (auto &conn : cell->connections())
|
||||
if (yosys_celltypes.cell_output(cell->type, conn.first))
|
||||
if (yosys_celltypes.cell_output(cell->type_impl, conn.first))
|
||||
undriven_signals.del(sigmap(conn.second));
|
||||
}
|
||||
|
||||
|
|
@ -211,7 +211,7 @@ struct EquivInductPass : public Pass {
|
|||
vector<Cell*> assume_cells;
|
||||
|
||||
for (auto cell : module->selected_cells())
|
||||
if (cell->type == ID($equiv)) {
|
||||
if (cell->type == TW($equiv)) {
|
||||
if (cell->getPort(TW::A) != cell->getPort(TW::B))
|
||||
unproven_equiv_cells.insert(cell);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -115,7 +115,7 @@ struct EquivMakeWorker
|
|||
if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
|
||||
cell_names.insert(it->name);
|
||||
gold_clone->rename(it, gold_clone->design->twines.add(Twine{it->name.str() + "_gold"}));
|
||||
if (it->type.in(ID($input_port), ID($output_port), ID($public)))
|
||||
if (it->type.in(TW($input_port), TW($output_port), TW($public)))
|
||||
gold_clone->remove(it);
|
||||
}
|
||||
|
||||
|
|
@ -129,7 +129,7 @@ struct EquivMakeWorker
|
|||
if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
|
||||
cell_names.insert(it->name);
|
||||
gate_clone->rename(it, gate_clone->design->twines.add(Twine{it->name.str() + "_gate"}));
|
||||
if (it->type.in(ID($input_port), ID($output_port), ID($public)))
|
||||
if (it->type.in(TW($input_port), TW($output_port), TW($public)))
|
||||
gate_clone->remove(it);
|
||||
}
|
||||
|
||||
|
|
@ -164,7 +164,7 @@ struct EquivMakeWorker
|
|||
|
||||
if (encdata.count(id))
|
||||
{
|
||||
log("Creating encoder/decoder for signal %s.\n", id.unescape());
|
||||
log("Creating encoder/decoder for signal %s.\n", design->twines.unescaped_str(id));
|
||||
|
||||
Wire *dec_wire = equiv_mod->addWire(Twine{id.str() + "_decoded"}, gold_wire->width);
|
||||
Wire *enc_wire = equiv_mod->addWire(Twine{id.str() + "_encoded"}, gate_wire->width);
|
||||
|
|
@ -239,7 +239,7 @@ struct EquivMakeWorker
|
|||
|
||||
log("Presumably equivalent wires: %s (%s), %s (%s) -> %s\n",
|
||||
gold_wire, log_signal(assign_map(gold_wire)),
|
||||
gate_wire, log_signal(assign_map(gate_wire)), id.unescape());
|
||||
gate_wire, log_signal(assign_map(gate_wire)), design->twines.unescaped_str(id));
|
||||
|
||||
if (gold_wire->port_output || gate_wire->port_output)
|
||||
{
|
||||
|
|
@ -310,7 +310,7 @@ struct EquivMakeWorker
|
|||
|
||||
for (auto c : cells_list)
|
||||
for (auto &conn : c->connections())
|
||||
if (!ct.cell_output(c->type, conn.first)) {
|
||||
if (!ct.cell_output(c->type_impl, conn.first)) {
|
||||
SigSpec old_sig = assign_map(conn.second);
|
||||
SigSpec new_sig = rd_signal_map(old_sig);
|
||||
for (int i = 0; i < GetSize(old_sig); i++)
|
||||
|
|
@ -318,7 +318,7 @@ struct EquivMakeWorker
|
|||
new_sig[i] = old_sig[i];
|
||||
if (old_sig != new_sig) {
|
||||
log("Changing input %s of cell %s (%s): %s -> %s\n",
|
||||
equiv_mod->design->twines.str(conn.first).c_str(), c, c->type.unescape(),
|
||||
equiv_mod->design->twines.str(conn.first).c_str(), c, design->twines.unescaped_str(c->type),
|
||||
log_signal(old_sig), log_signal(new_sig));
|
||||
c->setPort(conn.first, new_sig);
|
||||
}
|
||||
|
|
@ -339,7 +339,7 @@ struct EquivMakeWorker
|
|||
Cell *gold_cell = equiv_mod->cell(gold_id);
|
||||
Cell *gate_cell = equiv_mod->cell(gate_id);
|
||||
|
||||
if (gold_cell == nullptr || gate_cell == nullptr || gold_cell->type != gate_cell->type || !ct.cell_known(gold_cell->type) ||
|
||||
if (gold_cell == nullptr || gate_cell == nullptr || gold_cell->type != gate_cell->type || !ct.cell_known(gold_cell->type_impl) ||
|
||||
gold_cell->parameters != gate_cell->parameters || GetSize(gold_cell->connections()) != GetSize(gate_cell->connections()))
|
||||
try_next_cell_name:
|
||||
continue;
|
||||
|
|
@ -349,14 +349,14 @@ struct EquivMakeWorker
|
|||
goto try_next_cell_name;
|
||||
|
||||
log("Presumably equivalent cells: %s %s (%s) -> %s\n",
|
||||
gold_cell, gate_cell, gold_cell->type.unescape(), id.unescape());
|
||||
gold_cell, gate_cell, design->twines.unescaped_str(gold_cell->type), design->twines.unescaped_str(id));
|
||||
|
||||
for (auto gold_conn : gold_cell->connections())
|
||||
{
|
||||
SigSpec gold_sig = assign_map(gold_conn.second);
|
||||
SigSpec gate_sig = assign_map(gate_cell->getPort(gold_conn.first));
|
||||
|
||||
if (ct.cell_output(gold_cell->type, gold_conn.first)) {
|
||||
if (ct.cell_output(gold_cell->type_impl, gold_conn.first)) {
|
||||
equiv_mod->connect(gate_sig, gold_sig);
|
||||
continue;
|
||||
}
|
||||
|
|
@ -403,7 +403,7 @@ struct EquivMakeWorker
|
|||
|
||||
for (auto cell : equiv_mod->cells()) {
|
||||
for (auto &conn : cell->connections())
|
||||
if (!ct.cell_known(cell->type) || ct.cell_output(cell->type, conn.first))
|
||||
if (!ct.cell_known(cell->type_impl) || ct.cell_output(cell->type_impl, conn.first))
|
||||
for (auto bit : assign_map(conn.second))
|
||||
undriven_bits.erase(bit);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ struct EquivMarkWorker
|
|||
{
|
||||
for (auto cell : module->cells())
|
||||
{
|
||||
if (cell->type == ID($equiv))
|
||||
if (cell->type == TW($equiv))
|
||||
equiv_cells.insert(cell->meta_->name);
|
||||
|
||||
for (auto &port : cell->connections())
|
||||
|
|
@ -139,7 +139,7 @@ struct EquivMarkWorker
|
|||
|
||||
for (auto cell : module->cells())
|
||||
{
|
||||
if (cell_regions.count(cell->meta_->name) || cell->type != ID($equiv))
|
||||
if (cell_regions.count(cell->meta_->name) || cell->type != TW($equiv))
|
||||
continue;
|
||||
|
||||
SigSpec sig_a = sigmap(cell->getPort(TW::A));
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ struct EquivMiterWorker
|
|||
if (cone.count(c))
|
||||
return;
|
||||
|
||||
if (c->type == ID($equiv) && !seed_cells.count(c)) {
|
||||
if (c->type == TW($equiv) && !seed_cells.count(c)) {
|
||||
leaves.insert(c);
|
||||
return;
|
||||
}
|
||||
|
|
@ -55,9 +55,9 @@ struct EquivMiterWorker
|
|||
cone.insert(c);
|
||||
|
||||
for (auto &conn : c->connections()) {
|
||||
if (!ct.cell_input(c->type, conn.first))
|
||||
if (!ct.cell_input(c->type_impl, conn.first))
|
||||
continue;
|
||||
if (c->type == ID($equiv) && (conn.first == TW::A) != gold_mode)
|
||||
if (c->type == TW($equiv) && (conn.first == TW::A) != gold_mode)
|
||||
continue;
|
||||
for (auto bit : sigmap(conn.second))
|
||||
if (bit_to_driver.count(bit))
|
||||
|
|
@ -73,7 +73,7 @@ struct EquivMiterWorker
|
|||
|
||||
for (auto c : source_module->cells())
|
||||
for (auto &conn : c->connections())
|
||||
if (ct.cell_output(c->type, conn.first))
|
||||
if (ct.cell_output(c->type_impl, conn.first))
|
||||
for (auto bit : sigmap(conn.second))
|
||||
if (bit.wire)
|
||||
bit_to_driver[bit] = c;
|
||||
|
|
@ -81,7 +81,7 @@ struct EquivMiterWorker
|
|||
// find seed cells
|
||||
|
||||
for (auto c : source_module->selected_cells())
|
||||
if (c->type == ID($equiv)) {
|
||||
if (c->type == TW($equiv)) {
|
||||
log("Seed $equiv cell: %s\n", c);
|
||||
seed_cells.insert(c);
|
||||
}
|
||||
|
|
@ -143,7 +143,7 @@ struct EquivMiterWorker
|
|||
for (auto w : miter_wires)
|
||||
miter_module->addWire(Twine{w->name.str()}, w->width);
|
||||
for (auto c : miter_cells) {
|
||||
if (c->type.in(ID($input_port), ID($output_port), ID($public)))
|
||||
if (c->type.in(TW($input_port), TW($output_port), TW($public)))
|
||||
continue;
|
||||
auto mc = miter_module->addCell(Twine{c->name.str()}, c);
|
||||
for (auto &conn : mc->connections())
|
||||
|
|
@ -175,11 +175,11 @@ struct EquivMiterWorker
|
|||
|
||||
for (auto c : miter_module->cells())
|
||||
for (auto &conn : c->connections()) {
|
||||
if (ct.cell_input(c->type, conn.first))
|
||||
if (ct.cell_input(c->type_impl, conn.first))
|
||||
for (auto bit : conn.second)
|
||||
if (bit.wire)
|
||||
used_bits.insert(bit);
|
||||
if (ct.cell_output(c->type, conn.first))
|
||||
if (ct.cell_output(c->type_impl, conn.first))
|
||||
for (auto bit : conn.second)
|
||||
if (bit.wire)
|
||||
driven_bits.insert(bit);
|
||||
|
|
@ -214,7 +214,7 @@ struct EquivMiterWorker
|
|||
vector<Cell*> equiv_cells;
|
||||
|
||||
for (auto c : miter_module->cells())
|
||||
if (c->type == ID($equiv) && c->getPort(TW::A) != c->getPort(TW::B))
|
||||
if (c->type == TW($equiv) && c->getPort(TW::A) != c->getPort(TW::B))
|
||||
equiv_cells.push_back(c);
|
||||
|
||||
for (auto c : equiv_cells)
|
||||
|
|
@ -324,7 +324,7 @@ struct EquivMiterPass : public Pass {
|
|||
design->sigNormalize(false);
|
||||
|
||||
if (design->module(design->twines.lookup(worker.miter_name.str())))
|
||||
log_cmd_error("Miter module %s already exists.\n", worker.miter_name.unescape());
|
||||
log_cmd_error("Miter module %s already exists.\n", design->twines.unescaped_str(worker.miter_name));
|
||||
|
||||
worker.source_module = nullptr;
|
||||
for (auto m : design->selected_modules()) {
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ struct EquivPurgeWorker
|
|||
Wire *wire = sig.as_wire();
|
||||
if (wire->name.isPublic()) {
|
||||
if (!wire->port_output) {
|
||||
log(" Module output: %s (%s)\n", log_signal(wire), cellname.unescape());
|
||||
log(" Module output: %s (%s)\n", log_signal(wire), design->twines.unescaped_str(cellname));
|
||||
wire->port_output = true;
|
||||
}
|
||||
return wire;
|
||||
|
|
@ -53,7 +53,7 @@ struct EquivPurgeWorker
|
|||
Wire *wire = module->addWire(Twine{name}, GetSize(sig));
|
||||
wire->port_output = true;
|
||||
module->connect(wire, sig);
|
||||
log(" Module output: %s (%s)\n", log_signal(wire), cellname.unescape());
|
||||
log(" Module output: %s (%s)\n", log_signal(wire), design->twines.unescaped_str(cellname));
|
||||
return wire;
|
||||
}
|
||||
}
|
||||
|
|
@ -102,7 +102,7 @@ struct EquivPurgeWorker
|
|||
|
||||
for (auto cell : module->cells())
|
||||
{
|
||||
if (cell->type != ID($equiv)) {
|
||||
if (cell->type != TW($equiv)) {
|
||||
for (auto &port : cell->connections()) {
|
||||
if (cell->input(port.first))
|
||||
for (auto bit : sigmap(port.second))
|
||||
|
|
@ -167,7 +167,7 @@ struct EquivPurgeWorker
|
|||
rewrite_sigmap.add(chunk, make_input(chunk));
|
||||
|
||||
for (auto cell : module->cells())
|
||||
if (cell->type == ID($equiv))
|
||||
if (cell->type == TW($equiv))
|
||||
cell->setPort(TW::Y, rewrite_sigmap(sigmap(cell->getPort(TW::Y))));
|
||||
|
||||
module->fixup_ports();
|
||||
|
|
|
|||
|
|
@ -68,7 +68,7 @@ struct EquivRemovePass : public Pass {
|
|||
for (auto module : design->selected_modules())
|
||||
{
|
||||
for (auto cell : module->selected_cells())
|
||||
if (cell->type == ID($equiv) && (mode_gold || mode_gate || cell->getPort(TW::A) == cell->getPort(TW::B))) {
|
||||
if (cell->type == TW($equiv) && (mode_gold || mode_gate || cell->getPort(TW::A) == cell->getPort(TW::B))) {
|
||||
log("Removing $equiv cell %s.%s (%s).\n", module, cell, log_signal(cell->getPort(TW::Y)));
|
||||
module->connect(cell->getPort(TW::Y), mode_gate ? cell->getPort(TW::B) : cell->getPort(TW::A));
|
||||
module->remove(cell);
|
||||
|
|
|
|||
|
|
@ -111,7 +111,7 @@ struct EquivSimpleWorker : public EquivWorker<EquivSimpleConfig>
|
|||
return true;
|
||||
|
||||
for (auto &conn : cell->connections())
|
||||
if (yosys_celltypes.cell_input(cell->type, conn.first))
|
||||
if (yosys_celltypes.cell_input(cell->type_impl, conn.first))
|
||||
for (auto bit : model.sigmap(conn.second)) {
|
||||
if (cell->is_builtin_ff()) {
|
||||
if (conn.first != TW::CLK && conn.first != TW::C)
|
||||
|
|
@ -461,14 +461,14 @@ struct EquivSimplePass : public Pass {
|
|||
int unproven_cells_counter = 0;
|
||||
|
||||
for (auto cell : module->selected_cells()) {
|
||||
if (cell->type == ID($equiv) && cell->getPort(TW::A) != cell->getPort(TW::B)) {
|
||||
if (cell->type == TW($equiv) && cell->getPort(TW::A) != cell->getPort(TW::B)) {
|
||||
auto bit = sigmap(cell->getPort(TW::Y).as_bit());
|
||||
auto bit_group = bit;
|
||||
if (cfg.group && bit_group.wire)
|
||||
bit_group.offset = 0;
|
||||
unproven_equiv_cells[bit_group][bit] = cell;
|
||||
unproven_cells_counter++;
|
||||
} else if (cell->type == ID($assume)) {
|
||||
} else if (cell->type == TW($assume)) {
|
||||
assumes.push_back(cell);
|
||||
}
|
||||
}
|
||||
|
|
@ -480,10 +480,10 @@ struct EquivSimplePass : public Pass {
|
|||
unproven_cells_counter, GetSize(unproven_equiv_cells), module);
|
||||
|
||||
for (auto cell : module->cells()) {
|
||||
if (!ct.cell_known(cell->type))
|
||||
if (!ct.cell_known(cell->type_impl))
|
||||
continue;
|
||||
for (auto &conn : cell->connections())
|
||||
if (yosys_celltypes.cell_output(cell->type, conn.first))
|
||||
if (yosys_celltypes.cell_output(cell->type_impl, conn.first))
|
||||
for (auto bit : sigmap(conn.second))
|
||||
bit2driver[bit] = cell;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -59,7 +59,7 @@ struct EquivStatusPass : public Pass {
|
|||
int proven_equiv_cells = 0;
|
||||
|
||||
for (auto cell : module->selected_cells())
|
||||
if (cell->type == ID($equiv)) {
|
||||
if (cell->type == TW($equiv)) {
|
||||
if (cell->getPort(TW::A) != cell->getPort(TW::B))
|
||||
unproven_equiv_cells.push_back(cell);
|
||||
else
|
||||
|
|
|
|||
|
|
@ -124,7 +124,7 @@ struct EquivStructWorker
|
|||
pool<TwineRef> cells;
|
||||
|
||||
for (auto cell : module->selected_cells())
|
||||
if (cell->type == ID($equiv)) {
|
||||
if (cell->type == TW($equiv)) {
|
||||
SigBit sig_a = sigmap(cell->getPort(TW::A).as_bit());
|
||||
SigBit sig_b = sigmap(cell->getPort(TW::B).as_bit());
|
||||
equiv_bits.add(sig_b, sig_a);
|
||||
|
|
@ -137,7 +137,7 @@ struct EquivStructWorker
|
|||
}
|
||||
|
||||
for (auto cell : module->selected_cells())
|
||||
if (cell->type == ID($equiv)) {
|
||||
if (cell->type == TW($equiv)) {
|
||||
SigBit sig_a = sigmap(cell->getPort(TW::A).as_bit());
|
||||
SigBit sig_b = sigmap(cell->getPort(TW::B).as_bit());
|
||||
SigBit sig_y = sigmap(cell->getPort(TW::Y).as_bit());
|
||||
|
|
@ -264,7 +264,7 @@ struct EquivStructWorker
|
|||
run_strategy:
|
||||
int total_group_size = GetSize(gold_cells) + GetSize(gate_cells) + GetSize(other_cells);
|
||||
log(" %s merging %d %s cells (from group of %d) using strategy %s:\n", phase ? "Bwd" : "Fwd",
|
||||
2*GetSize(cell_pairs), cells_type.unescape(), total_group_size, strategy);
|
||||
2*GetSize(cell_pairs), design->twines.unescaped_str(cells_type), total_group_size, strategy);
|
||||
for (auto it : cell_pairs) {
|
||||
log(" Merging cells %s and %s.\n", it.first, it.second);
|
||||
merge_cell_pair(it.first, it.second);
|
||||
|
|
@ -314,7 +314,7 @@ struct EquivStructPass : public Pass {
|
|||
}
|
||||
void execute(std::vector<std::string> args, Design *design) override
|
||||
{
|
||||
pool<IdString> fwonly_cells({ ID($equiv) });
|
||||
pool<IdString> fwonly_cells({ TW($equiv) });
|
||||
bool mode_icells = false;
|
||||
bool mode_fwd = false;
|
||||
int max_iter = -1;
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@ ret_false:
|
|||
sig2driver.find(sig, cellport_list);
|
||||
for (auto &cellport : cellport_list)
|
||||
{
|
||||
if ((cellport.first->type != ID($mux) && cellport.first->type != ID($pmux)) || cellport.second != TW::Y) {
|
||||
if ((cellport.first->type != TW($mux) && cellport.first->type != TW($pmux)) || cellport.second != TW::Y) {
|
||||
goto ret_false;
|
||||
}
|
||||
|
||||
|
|
@ -99,9 +99,9 @@ static bool check_state_users(RTLIL::SigSpec sig)
|
|||
RTLIL::Cell *cell = cellport.first;
|
||||
if (muxtree_cells.count(cell) > 0)
|
||||
continue;
|
||||
if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
|
||||
if (cell->type.in(TW($input_port), TW($output_port), TW($public)))
|
||||
continue;
|
||||
if (cell->type == ID($logic_not) && assign_map(cell->getPort(TW::A)) == sig)
|
||||
if (cell->type == TW($logic_not) && assign_map(cell->getPort(TW::A)) == sig)
|
||||
continue;
|
||||
if (cellport.second != TW::A && cellport.second != TW::B)
|
||||
return false;
|
||||
|
|
@ -145,7 +145,7 @@ static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false)
|
|||
|
||||
for (auto &cellport : cellport_list)
|
||||
{
|
||||
if ((cellport.first->type != ID($dff) && cellport.first->type != ID($adff)) || cellport.second != TW::Q)
|
||||
if ((cellport.first->type != TW($dff) && cellport.first->type != TW($adff)) || cellport.second != TW::Q)
|
||||
continue;
|
||||
|
||||
muxtree_cells.clear();
|
||||
|
|
@ -175,10 +175,10 @@ static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false)
|
|||
RTLIL::Cell *cell = cellport.first;
|
||||
bool set_output = false, clr_output = false;
|
||||
|
||||
if (cell->type.in(ID($ne), ID($reduce_or), ID($reduce_bool)))
|
||||
if (cell->type.in(TW($ne), TW($reduce_or), TW($reduce_bool)))
|
||||
set_output = true;
|
||||
|
||||
if (cell->type.in(ID($eq), ID($logic_not), ID($reduce_and)))
|
||||
if (cell->type.in(TW($eq), TW($logic_not), TW($reduce_and)))
|
||||
clr_output = true;
|
||||
|
||||
if (set_output || clr_output) {
|
||||
|
|
@ -202,7 +202,7 @@ static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false)
|
|||
|
||||
SigSpec sig_y = sig_d, sig_undef;
|
||||
if (!ignore_self_reset) {
|
||||
if (cellport.first->type == ID($adff)) {
|
||||
if (cellport.first->type == TW($adff)) {
|
||||
SigSpec sig_arst = assign_map(cellport.first->getPort(TW::ARST));
|
||||
if (ce.eval(sig_arst, sig_undef))
|
||||
is_self_resetting = true;
|
||||
|
|
@ -328,12 +328,12 @@ struct FsmDetectPass : public Pass {
|
|||
sig_at_port.clear();
|
||||
for (auto cell : module->cells())
|
||||
for (auto &conn_it : cell->connections()) {
|
||||
if (ct.cell_output(cell->type, conn_it.first) || !ct.cell_known(cell->type)) {
|
||||
if (ct.cell_output(cell->type_impl, conn_it.first) || !ct.cell_known(cell->type_impl)) {
|
||||
RTLIL::SigSpec sig = conn_it.second;
|
||||
assign_map.apply(sig);
|
||||
sig2driver.insert(sig, sig2driver_entry_t(cell, conn_it.first));
|
||||
}
|
||||
if (!ct.cell_known(cell->type) || ct.cell_input(cell->type, conn_it.first)) {
|
||||
if (!ct.cell_known(cell->type_impl) || ct.cell_input(cell->type_impl, conn_it.first)) {
|
||||
RTLIL::SigSpec sig = conn_it.second;
|
||||
assign_map.apply(sig);
|
||||
sig2user.insert(sig, sig2driver_entry_t(cell, conn_it.first));
|
||||
|
|
|
|||
|
|
@ -47,10 +47,10 @@ struct FsmExpand
|
|||
|
||||
bool is_cell_merge_candidate(RTLIL::Cell *cell)
|
||||
{
|
||||
if (full_mode || cell->type == ID($_MUX_))
|
||||
if (full_mode || cell->type == TW($_MUX_))
|
||||
return true;
|
||||
|
||||
if (cell->type.in(ID($mux), ID($pmux)))
|
||||
if (cell->type.in(TW($mux), TW($pmux)))
|
||||
if (cell->getPort(TW::A).size() < 2)
|
||||
return true;
|
||||
|
||||
|
|
@ -147,7 +147,7 @@ struct FsmExpand
|
|||
RTLIL::SigSpec input_sig, output_sig;
|
||||
|
||||
for (auto &p : cell->connections())
|
||||
if (ct.cell_output(cell->type, p.first))
|
||||
if (ct.cell_output(cell->type_impl, p.first))
|
||||
output_sig.append(assign_map(p.second));
|
||||
else
|
||||
input_sig.append(assign_map(p.second));
|
||||
|
|
@ -189,7 +189,7 @@ struct FsmExpand
|
|||
|
||||
if (GetSize(input_sig) > 10)
|
||||
log_warning("Cell %s.%s (%s) has %d input bits, merging into FSM %s.%s might be problematic.\n",
|
||||
cell->module, cell, cell->type.unescape(),
|
||||
cell->module, cell, cell->type.unescaped(),
|
||||
GetSize(input_sig), fsm_cell->module, fsm_cell);
|
||||
|
||||
if (GetSize(fsm_data.transition_table) > 10000)
|
||||
|
|
@ -230,9 +230,9 @@ struct FsmExpand
|
|||
|
||||
for (auto &cell_it : module->cells_) {
|
||||
RTLIL::Cell *c = cell_it.second;
|
||||
if (ct.cell_known(c->type) && design->selected(mod, c))
|
||||
if (ct.cell_known(c->type_impl) && design->selected(mod, c))
|
||||
for (auto &p : c->connections()) {
|
||||
if (ct.cell_output(c->type, p.first))
|
||||
if (ct.cell_output(c->type_impl, p.first))
|
||||
sig2driver.insert(assign_map(p.second), c);
|
||||
else
|
||||
sig2user.insert(assign_map(p.second), c);
|
||||
|
|
@ -298,7 +298,7 @@ struct FsmExpandPass : public Pass {
|
|||
for (auto mod : design->selected_modules()) {
|
||||
std::vector<RTLIL::Cell*> fsm_cells;
|
||||
for (auto cell : mod->selected_cells())
|
||||
if (cell->type == ID($fsm))
|
||||
if (cell->type == TW($fsm))
|
||||
fsm_cells.push_back(cell);
|
||||
for (auto c : fsm_cells) {
|
||||
FsmExpand fsm_expand(c, design, mod, full_mode);
|
||||
|
|
|
|||
|
|
@ -175,7 +175,7 @@ struct FsmExportPass : public Pass {
|
|||
|
||||
for (auto mod : design->selected_modules())
|
||||
for (auto cell : mod->selected_cells())
|
||||
if (cell->type == ID($fsm)) {
|
||||
if (cell->type == TW($fsm)) {
|
||||
attr_it = cell->attributes.find(ID::fsm_export);
|
||||
if (!flag_noauto || (attr_it != cell->attributes.end())) {
|
||||
write_kiss2(mod, cell, filename, flag_origenc);
|
||||
|
|
|
|||
|
|
@ -70,7 +70,7 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
|
|||
for (auto &cellport : cellport_list)
|
||||
{
|
||||
RTLIL::Cell *cell = module->cell(cellport.first);
|
||||
if ((cell->type != ID($mux) && cell->type != ID($pmux)) || cellport.second != TW::Y) {
|
||||
if ((cell->type != TW($mux) && cell->type != TW($pmux)) || cellport.second != TW::Y) {
|
||||
log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type, log_id(cell));
|
||||
return false;
|
||||
}
|
||||
|
|
@ -272,14 +272,14 @@ static void extract_fsm(RTLIL::Wire *wire)
|
|||
sig2driver.find(dff_out, cellport_list);
|
||||
for (auto &cellport : cellport_list) {
|
||||
RTLIL::Cell *cell = module->cell(cellport.first);
|
||||
if ((cell->type != ID($dff) && cell->type != ID($adff)) || cellport.second != TW::Q)
|
||||
if ((cell->type != TW($dff) && cell->type != TW($adff)) || cellport.second != TW::Q)
|
||||
continue;
|
||||
log(" found %s cell for state register: %s\n", cell->type, log_id(cell));
|
||||
RTLIL::SigSpec sig_q = assign_map(cell->getPort(TW::Q));
|
||||
RTLIL::SigSpec sig_d = assign_map(cell->getPort(TW::D));
|
||||
clk = cell->getPort(TW::CLK);
|
||||
clk_polarity = cell->parameters[ID::CLK_POLARITY].as_bool();
|
||||
if (cell->type == ID($adff)) {
|
||||
if (cell->type == TW($adff)) {
|
||||
arst = cell->getPort(TW::ARST);
|
||||
arst_polarity = cell->parameters[ID::ARST_POLARITY].as_bool();
|
||||
reset_state = cell->parameters[ID::ARST_VALUE];
|
||||
|
|
@ -368,7 +368,7 @@ static void extract_fsm(RTLIL::Wire *wire)
|
|||
|
||||
// create fsm cell
|
||||
|
||||
RTLIL::Cell *fsm_cell = module->addCell(Twine{stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++)}, ID($fsm));
|
||||
RTLIL::Cell *fsm_cell = module->addCell(Twine{stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++)}, TW($fsm));
|
||||
fsm_cell->setPort(TW::CLK, clk);
|
||||
fsm_cell->setPort(TW::ARST, arst);
|
||||
fsm_cell->parameters[ID::CLK_POLARITY] = clk_polarity ? State::S1 : State::S0;
|
||||
|
|
@ -446,19 +446,19 @@ struct FsmExtractPass : public Pass {
|
|||
exclusive_ctrls.clear();
|
||||
for (auto cell : module->cells()) {
|
||||
for (auto &conn_it : cell->connections()) {
|
||||
if (ct.cell_output(cell->type, conn_it.first) || !ct.cell_known(cell->type)) {
|
||||
if (ct.cell_output(cell->type_impl, conn_it.first) || !ct.cell_known(cell->type_impl)) {
|
||||
RTLIL::SigSpec sig = conn_it.second;
|
||||
assign_map.apply(sig);
|
||||
sig2driver.insert(sig, sig2driver_entry_t(cell->meta_->name, conn_it.first));
|
||||
}
|
||||
if (ct.cell_input(cell->type, conn_it.first) && cell->hasPort(TW::Y) &&
|
||||
if (ct.cell_input(cell->type_impl, conn_it.first) && cell->hasPort(TW::Y) &&
|
||||
cell->getPort(TW::Y).size() == 1 && (conn_it.first == TW::A || conn_it.first == TW::B)) {
|
||||
RTLIL::SigSpec sig = conn_it.second;
|
||||
assign_map.apply(sig);
|
||||
sig2trigger.insert(sig, sig2driver_entry_t(cell->meta_->name, conn_it.first));
|
||||
}
|
||||
}
|
||||
if (cell->type == ID($pmux)) {
|
||||
if (cell->type == TW($pmux)) {
|
||||
RTLIL::SigSpec sel_sig = assign_map(cell->getPort(TW::S));
|
||||
for (auto &bit1 : sel_sig)
|
||||
for (auto &bit2 : sel_sig)
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ struct FsmInfoPass : public Pass {
|
|||
|
||||
for (auto mod : design->selected_modules())
|
||||
for (auto cell : mod->selected_cells())
|
||||
if (cell->type == ID($fsm)) {
|
||||
if (cell->type == TW($fsm)) {
|
||||
log("\n");
|
||||
log("FSM `%s' from module `%s':\n", cell, mod);
|
||||
FsmData fsm_data;
|
||||
|
|
|
|||
|
|
@ -74,7 +74,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
|
|||
RTLIL::Wire *eq_wire = module->addWire(NEW_TWINE);
|
||||
and_sig.append(RTLIL::SigSpec(eq_wire));
|
||||
|
||||
RTLIL::Cell *eq_cell = module->addCell(NEW_TWINE, ID($eq));
|
||||
RTLIL::Cell *eq_cell = module->addCell(NEW_TWINE, TW($eq));
|
||||
eq_cell->setPort(TW::A, eq_sig_a);
|
||||
eq_cell->setPort(TW::B, eq_sig_b);
|
||||
eq_cell->setPort(TW::Y, RTLIL::SigSpec(eq_wire));
|
||||
|
|
@ -102,7 +102,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
|
|||
RTLIL::Wire *or_wire = module->addWire(NEW_TWINE);
|
||||
and_sig.append(RTLIL::SigSpec(or_wire));
|
||||
|
||||
RTLIL::Cell *or_cell = module->addCell(NEW_TWINE, ID($reduce_or));
|
||||
RTLIL::Cell *or_cell = module->addCell(NEW_TWINE, TW($reduce_or));
|
||||
or_cell->setPort(TW::A, or_sig);
|
||||
or_cell->setPort(TW::Y, RTLIL::SigSpec(or_wire));
|
||||
or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
|
||||
|
|
@ -118,7 +118,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
|
|||
RTLIL::Wire *and_wire = module->addWire(NEW_TWINE);
|
||||
cases_vector.append(RTLIL::SigSpec(and_wire));
|
||||
|
||||
RTLIL::Cell *and_cell = module->addCell(NEW_TWINE, ID($and));
|
||||
RTLIL::Cell *and_cell = module->addCell(NEW_TWINE, TW($and));
|
||||
and_cell->setPort(TW::A, and_sig.extract(0, 1));
|
||||
and_cell->setPort(TW::B, and_sig.extract(1, 1));
|
||||
and_cell->setPort(TW::Y, RTLIL::SigSpec(and_wire));
|
||||
|
|
@ -141,7 +141,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
|
|||
}
|
||||
|
||||
if (cases_vector.size() > 1) {
|
||||
RTLIL::Cell *or_cell = module->addCell(NEW_TWINE, ID($reduce_or));
|
||||
RTLIL::Cell *or_cell = module->addCell(NEW_TWINE, TW($reduce_or));
|
||||
or_cell->setPort(TW::A, cases_vector);
|
||||
or_cell->setPort(TW::Y, output);
|
||||
or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
|
||||
|
|
@ -212,7 +212,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
|
|||
{
|
||||
encoding_is_onehot = false;
|
||||
|
||||
RTLIL::Cell *eq_cell = module->addCell(NEW_TWINE, ID($eq));
|
||||
RTLIL::Cell *eq_cell = module->addCell(NEW_TWINE, TW($eq));
|
||||
eq_cell->setPort(TW::A, sig_a);
|
||||
eq_cell->setPort(TW::B, sig_b);
|
||||
eq_cell->setPort(TW::Y, RTLIL::SigSpec(state_onehot, i));
|
||||
|
|
@ -285,7 +285,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
|
|||
}
|
||||
}
|
||||
|
||||
RTLIL::Cell *mux_cell = module->addCell(NEW_TWINE, ID($pmux));
|
||||
RTLIL::Cell *mux_cell = module->addCell(NEW_TWINE, TW($pmux));
|
||||
mux_cell->setPort(TW::A, sig_a);
|
||||
mux_cell->setPort(TW::B, sig_b);
|
||||
mux_cell->setPort(TW::S, sig_s);
|
||||
|
|
@ -339,7 +339,7 @@ struct FsmMapPass : public Pass {
|
|||
for (auto mod : design->selected_modules()) {
|
||||
std::vector<RTLIL::Cell*> fsm_cells;
|
||||
for (auto cell : mod->selected_cells())
|
||||
if (cell->type == ID($fsm))
|
||||
if (cell->type == TW($fsm))
|
||||
fsm_cells.push_back(cell);
|
||||
for (auto cell : fsm_cells)
|
||||
map_fsm(cell, mod);
|
||||
|
|
|
|||
|
|
@ -348,7 +348,7 @@ struct FsmOptPass : public Pass {
|
|||
|
||||
for (auto mod : design->selected_modules())
|
||||
for (auto cell : mod->selected_cells())
|
||||
if (cell->type == ID($fsm))
|
||||
if (cell->type == TW($fsm))
|
||||
FsmData::optimize_fsm(cell, mod);
|
||||
}
|
||||
} FsmOptPass;
|
||||
|
|
|
|||
|
|
@ -184,7 +184,7 @@ struct FsmRecodePass : public Pass {
|
|||
|
||||
for (auto mod : design->selected_modules())
|
||||
for (auto cell : mod->selected_cells())
|
||||
if (cell->type == ID($fsm))
|
||||
if (cell->type == TW($fsm))
|
||||
fsm_recode(cell, mod, fm_set_fsm_file, encfile, default_encoding);
|
||||
|
||||
if (fm_set_fsm_file != NULL)
|
||||
|
|
|
|||
|
|
@ -209,7 +209,7 @@ struct FlattenWorker
|
|||
}
|
||||
|
||||
for (auto tpl_cell : tpl->cells()) {
|
||||
if (tpl_cell->type.in(ID($input_port), ID($output_port), ID($public)))
|
||||
if (tpl_cell->type.in(TW($input_port), TW($output_port), TW($public)))
|
||||
continue;
|
||||
RTLIL::Cell *new_cell = module->addCell(map_name(cell, tpl_cell, separator), tpl_cell);
|
||||
map_attributes(cell, new_cell, tpl_cell->name);
|
||||
|
|
@ -308,7 +308,7 @@ struct FlattenWorker
|
|||
if (create_scopeinfo && cell_name.isPublic())
|
||||
{
|
||||
// The $scopeinfo's name will be changed below after removing the flattened cell
|
||||
scopeinfo = module->addCell(NEW_TWINE, ID($scopeinfo));
|
||||
scopeinfo = module->addCell(NEW_TWINE, TW($scopeinfo));
|
||||
scopeinfo->setParam(ID::TYPE, RTLIL::Const("module"));
|
||||
|
||||
for (auto const &attr : cell->attributes)
|
||||
|
|
@ -316,7 +316,7 @@ struct FlattenWorker
|
|||
if (attr.first == ID::hdlname)
|
||||
scopeinfo->attributes.insert(attr);
|
||||
else
|
||||
scopeinfo->attributes.emplace(stringf("\\cell_%s", attr.first.unescape()), attr.second);
|
||||
scopeinfo->attributes.emplace(stringf("\\cell_%s", design->twines.unescaped_str(attr.first)), attr.second);
|
||||
}
|
||||
// src lives outside cell->attributes after the typed-src
|
||||
// migration — fold it into the renamed-attribute view by
|
||||
|
|
@ -325,7 +325,7 @@ struct FlattenWorker
|
|||
scopeinfo->attributes.emplace(ID(cell_src), RTLIL::Const(cell->get_src_attribute()));
|
||||
|
||||
for (auto const &attr : tpl->attributes)
|
||||
scopeinfo->attributes.emplace(stringf("\\module_%s", attr.first.unescape()), attr.second);
|
||||
scopeinfo->attributes.emplace(stringf("\\module_%s", design->twines.unescaped_str(attr.first)), attr.second);
|
||||
if (tpl->src_id() != Twine::Null)
|
||||
scopeinfo->attributes.emplace(ID(module_src), RTLIL::Const(tpl->get_src_attribute()));
|
||||
|
||||
|
|
@ -364,7 +364,7 @@ struct FlattenWorker
|
|||
continue;
|
||||
}
|
||||
|
||||
log_debug("Flattening %s.%s (%s).\n", module, cell, cell->type.unescape());
|
||||
log_debug("Flattening %s.%s (%s).\n", module, cell, cell->type.unescaped());
|
||||
// If a design is fully selected and has a top module defined, topological sorting ensures that all cells
|
||||
// added during flattening are black boxes, and flattening is finished in one pass. However, when flattening
|
||||
// individual modules, this isn't the case, and the newly added cells might have to be flattened further.
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
|
|||
if (cell->type.begins_with("$") && !cell->type.begins_with("$__"))
|
||||
continue;
|
||||
for (auto &pattern : celltypes)
|
||||
if (patmatch(pattern.c_str(), cell->type.unescape().c_str()))
|
||||
if (patmatch(pattern.c_str(), cell->type.unescaped().c_str()))
|
||||
found_celltypes.insert(cell->type);
|
||||
}
|
||||
|
||||
|
|
@ -132,7 +132,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
|
|||
mod->fixup_ports();
|
||||
|
||||
for (auto ¶ : parameters)
|
||||
log(" ignoring parameter %s.\n", para.unescape());
|
||||
log(" ignoring parameter %s.\n", design->twines.unescaped_str(para));
|
||||
|
||||
log(" module %s created.\n", mod);
|
||||
}
|
||||
|
|
@ -238,7 +238,7 @@ struct IFExpander
|
|||
// about it and don't set has_interfaces_not_found (to avoid a
|
||||
// loop).
|
||||
log_warning("Could not find interface instance for `%s' in `%s'\n",
|
||||
interface_name.unescape(), &module);
|
||||
design->twines.unescaped_str(interface_name), &module);
|
||||
}
|
||||
|
||||
// Handle an interface connection from the module
|
||||
|
|
@ -282,8 +282,8 @@ struct IFExpander
|
|||
// Go over all wires in interface, and add replacements to lists.
|
||||
std::string conn_name_str(design.twines.str(conn_name));
|
||||
for (auto mod_wire : mod_replace_ports->wires()) {
|
||||
std::string signal_name1 = conn_name_str + "." + mod_wire->name.unescape();
|
||||
std::string signal_name2 = interface_name.str() + "." + mod_wire->name.unescape();
|
||||
std::string signal_name1 = conn_name_str + "." + design->twines.unescaped_str(mod_wire->name);
|
||||
std::string signal_name2 = interface_name.str() + "." + design->twines.unescaped_str(mod_wire->name);
|
||||
connections_to_add.push_back(design.twines.add(Twine{signal_name1}));
|
||||
TwineRef signal_name2_ref = design.twines.lookup(signal_name2);
|
||||
if(module.wire(signal_name2_ref) == nullptr) {
|
||||
|
|
@ -412,7 +412,7 @@ RTLIL::Module *get_module(RTLIL::Design &design,
|
|||
};
|
||||
|
||||
for (auto &ext : extensions_list) {
|
||||
std::string filename = dir + "/" + cell.type.unescape() + ext.first;
|
||||
std::string filename = dir + "/" + design->twines.unescaped_str(cell.type) + ext.first;
|
||||
if (!check_file_exists(filename))
|
||||
continue;
|
||||
|
||||
|
|
@ -447,7 +447,7 @@ void check_cell_connections(const RTLIL::Module &module, RTLIL::Cell &cell, RTLI
|
|||
if (id <= 0 || id > GetSize(mod.ports))
|
||||
log_error("Module `%s' referenced in module `%s' in cell `%s' "
|
||||
"has only %d ports, requested port %d.\n",
|
||||
cell.type.unescape(), &module, &cell,
|
||||
design->twines.unescaped_str(cell.type), &module, &cell,
|
||||
GetSize(mod.ports), id);
|
||||
continue;
|
||||
}
|
||||
|
|
@ -456,7 +456,7 @@ void check_cell_connections(const RTLIL::Module &module, RTLIL::Cell &cell, RTLI
|
|||
if (!wire || wire->port_id == 0) {
|
||||
log_error("Module `%s' referenced in module `%s' in cell `%s' "
|
||||
"does not have a port named '%s'.\n",
|
||||
cell.type.unescape(), &module, &cell,
|
||||
design->twines.unescaped_str(cell.type), &module, &cell,
|
||||
module.design->twines.str(conn.first).data());
|
||||
}
|
||||
}
|
||||
|
|
@ -465,7 +465,7 @@ void check_cell_connections(const RTLIL::Module &module, RTLIL::Cell &cell, RTLI
|
|||
if (id <= 0 || id > GetSize(mod.avail_parameters))
|
||||
log_error("Module `%s' referenced in module `%s' in cell `%s' "
|
||||
"has only %d parameters, requested parameter %d.\n",
|
||||
cell.type.unescape(), &module, &cell,
|
||||
design->twines.unescaped_str(cell.type), &module, &cell,
|
||||
GetSize(mod.avail_parameters), id);
|
||||
continue;
|
||||
}
|
||||
|
|
@ -475,8 +475,8 @@ void check_cell_connections(const RTLIL::Module &module, RTLIL::Cell &cell, RTLI
|
|||
strchr(param.first.c_str(), '.') == NULL) {
|
||||
log_error("Module `%s' referenced in module `%s' in cell `%s' "
|
||||
"does not have a parameter named '%s'.\n",
|
||||
cell.type.unescape(), &module, &cell,
|
||||
param.first.unescape());
|
||||
design->twines.unescaped_str(cell.type), &module, &cell,
|
||||
design->twines.unescaped_str(param.first));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -619,7 +619,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
|
|||
int idx = it.second.first, num = it.second.second;
|
||||
|
||||
if (design->module(cell->type) == nullptr)
|
||||
log_error("Array cell `%s.%s' of unknown type `%s'.\n", module, cell, cell->type.unescape());
|
||||
log_error("Array cell `%s.%s' of unknown type `%s'.\n", module, cell, cell->type.unescaped());
|
||||
|
||||
RTLIL::Module *mod = design->module(cell->type);
|
||||
|
||||
|
|
@ -715,7 +715,7 @@ bool set_keep_print(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
|
|||
if (mod->meta_->name == mod->design->twines.add(Twine{c->type.str()}))
|
||||
continue;
|
||||
RTLIL::Module *m = mod->design->module(c->type);
|
||||
if ((m != nullptr && set_keep_print(cache, m)) || c->type == ID($print))
|
||||
if ((m != nullptr && set_keep_print(cache, m)) || c->type == TW($print))
|
||||
return cache[mod] = true;
|
||||
}
|
||||
return cache[mod];
|
||||
|
|
@ -728,7 +728,7 @@ bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
|
|||
if (mod->meta_->name == mod->design->twines.add(Twine{c->type.str()}))
|
||||
continue;
|
||||
RTLIL::Module *m = mod->design->module(c->type);
|
||||
if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in(ID($check), ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
|
||||
if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in(TW($check), TW($assert), TW($assume), TW($live), TW($fair), TW($cover)))
|
||||
return cache[mod] = true;
|
||||
}
|
||||
return cache[mod];
|
||||
|
|
@ -1221,7 +1221,7 @@ struct HierarchyPass : public Pass {
|
|||
if (flag_simcheck || flag_smtcheck) {
|
||||
for (auto mod : design->modules()) {
|
||||
for (auto cell : mod->cells()) {
|
||||
if (!cell->type.in(ID($check), ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
|
||||
if (!cell->type.in(TW($check), TW($assert), TW($assume), TW($live), TW($fair), TW($cover)))
|
||||
continue;
|
||||
if (!cell->has_attribute(ID(unsupported_sva)))
|
||||
continue;
|
||||
|
|
@ -1263,7 +1263,7 @@ struct HierarchyPass : public Pass {
|
|||
if (read_id_num(p.first, &id)) {
|
||||
if (id <= 0 || id > GetSize(cell_mod->avail_parameters)) {
|
||||
log(" Failed to map positional parameter %d of cell %s.%s (%s).\n",
|
||||
id, mod, cell, cell->type.unescape());
|
||||
id, mod, cell, cell->type.unescaped());
|
||||
} else {
|
||||
params_rename.insert(std::make_pair(p.first, cell_mod->avail_parameters[id - 1]));
|
||||
}
|
||||
|
|
@ -1285,7 +1285,7 @@ struct HierarchyPass : public Pass {
|
|||
RTLIL::Module *module = work.first;
|
||||
RTLIL::Cell *cell = work.second;
|
||||
log("Mapping positional arguments of cell %s.%s (%s).\n",
|
||||
module, cell, cell->type.unescape());
|
||||
module, cell, cell->type.unescaped());
|
||||
dict<TwineRef, RTLIL::SigSpec> new_connections_twine;
|
||||
for (auto &conn : cell->connections()) {
|
||||
int id;
|
||||
|
|
@ -1293,7 +1293,7 @@ struct HierarchyPass : public Pass {
|
|||
std::pair<RTLIL::Module*,int> key(design->module(cell->type), id);
|
||||
if (pos_map.count(key) == 0) {
|
||||
log(" Failed to map positional argument %d of cell %s.%s (%s).\n",
|
||||
id, module, cell, cell->type.unescape());
|
||||
id, module, cell, cell->type.unescaped());
|
||||
new_connections_twine[conn.first] = conn.second;
|
||||
} else
|
||||
new_connections_twine[design->twines.add(Twine{pos_map.at(key).str()})] = conn.second;
|
||||
|
|
@ -1327,7 +1327,7 @@ struct HierarchyPass : public Pass {
|
|||
|
||||
if (m == nullptr)
|
||||
log_error("Cell %s.%s (%s) has implicit port connections but the module it instantiates is unknown.\n",
|
||||
module, cell, cell->type.unescape());
|
||||
module, cell, cell->type.unescaped());
|
||||
|
||||
// Need accurate port widths for error checking; so must derive blackboxes with dynamic port widths
|
||||
if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute(ID::dynports)) {
|
||||
|
|
@ -1356,11 +1356,11 @@ struct HierarchyPass : public Pass {
|
|||
|
||||
if (parent_wire == nullptr)
|
||||
log_error("No matching wire for implicit port connection `%s' of cell %s.%s (%s).\n",
|
||||
wire, module, cell, cell->type.unescape());
|
||||
wire, module, cell, cell->type.unescaped());
|
||||
if (parent_wire->width != wire->width)
|
||||
log_error("Width mismatch between wire (%d bits) and port (%d bits) for implicit port connection `%s' of cell %s.%s (%s).\n",
|
||||
parent_wire->width, wire->width,
|
||||
wire, module, cell, cell->type.unescape());
|
||||
wire, module, cell, cell->type.unescaped());
|
||||
cell->setPort(wire->meta_->name, parent_wire);
|
||||
}
|
||||
cell->attributes.erase(ID::wildcard_port_conns);
|
||||
|
|
@ -1578,7 +1578,7 @@ struct HierarchyPass : public Pass {
|
|||
|
||||
if (w->port_output && !w->port_input && sig.has_const())
|
||||
log_error("Output port %s.%s.%s (%s) is connected to constants: %s\n",
|
||||
module, cell, design->twines.str(conn.first).data(), cell->type.unescape(), log_signal(sig));
|
||||
module, cell, design->twines.str(conn.first).data(), cell->type.unescaped(), log_signal(sig));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -61,7 +61,7 @@ struct ThresholdHierarchyKeeping {
|
|||
RTLIL::Module *submodule = design->module(cell->type);
|
||||
if (!submodule)
|
||||
log_error("Hierarchy contains unknown module '%s' (instanced as %s in %s)\n",
|
||||
cell->type.unescape(), cell, module);
|
||||
cell->type.unescaped(), cell, module);
|
||||
size += visit(submodule);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -91,9 +91,9 @@ struct SubmodWorker
|
|||
|
||||
wire_flags.clear();
|
||||
for (RTLIL::Cell *cell : submod.cells) {
|
||||
if (ct.cell_known(cell->type)) {
|
||||
if (ct.cell_known(cell->type_impl)) {
|
||||
for (auto &conn : cell->connections())
|
||||
flag_signal(conn.second, true, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first), false, false);
|
||||
flag_signal(conn.second, true, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type_impl, conn.first), false, false);
|
||||
} else {
|
||||
log_warning("Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name, cell->type);
|
||||
for (auto &conn : cell->connections())
|
||||
|
|
@ -103,9 +103,9 @@ struct SubmodWorker
|
|||
for (auto cell : module->cells()) {
|
||||
if (submod.cells.count(cell) > 0)
|
||||
continue;
|
||||
if (ct.cell_known(cell->type)) {
|
||||
if (ct.cell_known(cell->type_impl)) {
|
||||
for (auto &conn : cell->connections())
|
||||
flag_signal(conn.second, false, false, false, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first));
|
||||
flag_signal(conn.second, false, false, false, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type_impl, conn.first));
|
||||
} else {
|
||||
flag_found_something = false;
|
||||
for (auto &conn : cell->connections())
|
||||
|
|
|
|||
|
|
@ -84,7 +84,7 @@ struct UniquifyPass : public Pass {
|
|||
if (tmod->get_bool_attribute(ID::unique) && newname_ref == tmod->meta_->name)
|
||||
continue;
|
||||
|
||||
log("Creating module %s from %s.\n", newname.unescape(), tmod);
|
||||
log("Creating module %s from %s.\n", design->twines.unescaped_str(newname), tmod);
|
||||
|
||||
auto smod = tmod->clone();
|
||||
smod->meta_->name = newname_ref;
|
||||
|
|
|
|||
|
|
@ -140,7 +140,7 @@ struct RamClock {
|
|||
};
|
||||
|
||||
struct Ram {
|
||||
IdString id;
|
||||
TwineRef id;
|
||||
RamKind kind;
|
||||
dict<std::string, Const> options;
|
||||
std::vector<PortGroup> port_groups;
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ struct MemoryBmux2RomPass : public Pass {
|
|||
|
||||
for (auto module : design->selected_modules()) {
|
||||
for (auto cell : module->selected_cells()) {
|
||||
if (cell->type != ID($bmux))
|
||||
if (cell->type != TW($bmux))
|
||||
continue;
|
||||
|
||||
SigSpec sig_a = cell->getPort(TW::A);
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@ struct rules_t
|
|||
|
||||
void dump_config() const
|
||||
{
|
||||
log(" bram %s # variant %d\n", name.unescape(), variant);
|
||||
log(" bram %s # variant %d\n", design->twines.unescaped_str(name), variant);
|
||||
log(" init %d\n", init);
|
||||
log(" abits %d\n", abits);
|
||||
log(" dbits %d\n", dbits);
|
||||
|
|
@ -61,16 +61,16 @@ struct rules_t
|
|||
|
||||
void check_vectors() const
|
||||
{
|
||||
if (groups != GetSize(ports)) log_error("Bram %s variant %d has %d groups but only %d entries in 'ports'.\n", name.unescape(), variant, groups, GetSize(ports));
|
||||
if (groups != GetSize(wrmode)) log_error("Bram %s variant %d has %d groups but only %d entries in 'wrmode'.\n", name.unescape(), variant, groups, GetSize(wrmode));
|
||||
if (groups != GetSize(enable)) log_error("Bram %s variant %d has %d groups but only %d entries in 'enable'.\n", name.unescape(), variant, groups, GetSize(enable));
|
||||
if (groups != GetSize(transp)) log_error("Bram %s variant %d has %d groups but only %d entries in 'transp'.\n", name.unescape(), variant, groups, GetSize(transp));
|
||||
if (groups != GetSize(clocks)) log_error("Bram %s variant %d has %d groups but only %d entries in 'clocks'.\n", name.unescape(), variant, groups, GetSize(clocks));
|
||||
if (groups != GetSize(clkpol)) log_error("Bram %s variant %d has %d groups but only %d entries in 'clkpol'.\n", name.unescape(), variant, groups, GetSize(clkpol));
|
||||
if (groups != GetSize(ports)) log_error("Bram %s variant %d has %d groups but only %d entries in 'ports'.\n", design->twines.unescaped_str(name), variant, groups, GetSize(ports));
|
||||
if (groups != GetSize(wrmode)) log_error("Bram %s variant %d has %d groups but only %d entries in 'wrmode'.\n", design->twines.unescaped_str(name), variant, groups, GetSize(wrmode));
|
||||
if (groups != GetSize(enable)) log_error("Bram %s variant %d has %d groups but only %d entries in 'enable'.\n", design->twines.unescaped_str(name), variant, groups, GetSize(enable));
|
||||
if (groups != GetSize(transp)) log_error("Bram %s variant %d has %d groups but only %d entries in 'transp'.\n", design->twines.unescaped_str(name), variant, groups, GetSize(transp));
|
||||
if (groups != GetSize(clocks)) log_error("Bram %s variant %d has %d groups but only %d entries in 'clocks'.\n", design->twines.unescaped_str(name), variant, groups, GetSize(clocks));
|
||||
if (groups != GetSize(clkpol)) log_error("Bram %s variant %d has %d groups but only %d entries in 'clkpol'.\n", design->twines.unescaped_str(name), variant, groups, GetSize(clkpol));
|
||||
|
||||
int group = 0;
|
||||
for (auto e : enable)
|
||||
if (e > dbits) log_error("Bram %s variant %d group %d has %d enable bits but only %d dbits.\n", name.unescape(), variant, group, e, dbits);
|
||||
if (e > dbits) log_error("Bram %s variant %d group %d has %d enable bits but only %d dbits.\n", design->twines.unescaped_str(name), variant, group, e, dbits);
|
||||
}
|
||||
|
||||
vector<portinfo_t> make_portinfos() const
|
||||
|
|
@ -100,7 +100,7 @@ struct rules_t
|
|||
log_assert(name == other.name);
|
||||
|
||||
if (groups != other.groups)
|
||||
log_error("Bram %s variants %d and %d have different values for 'groups'.\n", name.unescape(), variant, other.variant);
|
||||
log_error("Bram %s variants %d and %d have different values for 'groups'.\n", design->twines.unescaped_str(name), variant, other.variant);
|
||||
|
||||
if (abits != other.abits)
|
||||
variant_params[ID::CFG_ABITS] = abits;
|
||||
|
|
@ -112,7 +112,7 @@ struct rules_t
|
|||
for (int i = 0; i < groups; i++)
|
||||
{
|
||||
if (ports[i] != other.ports[i])
|
||||
log_error("Bram %s variants %d and %d have different number of %c-ports.\n", name.unescape(), variant, other.variant, 'A'+i);
|
||||
log_error("Bram %s variants %d and %d have different number of %c-ports.\n", design->twines.unescaped_str(name), variant, other.variant, 'A'+i);
|
||||
if (wrmode[i] != other.wrmode[i])
|
||||
variant_params[stringf("\\CFG_WRMODE_%c", 'A' + i)] = wrmode[i];
|
||||
if (enable[i] != other.enable[i])
|
||||
|
|
@ -490,7 +490,7 @@ bool replace_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals, const
|
|||
transp_max = max(transp_max, pi.transp);
|
||||
}
|
||||
|
||||
log(" Mapping to bram type %s (variant %d):\n", bram.name.unescape(), bram.variant);
|
||||
log(" Mapping to bram type %s (variant %d):\n", design->twines.unescaped_str(bram.name), bram.variant);
|
||||
// bram.dump_config();
|
||||
|
||||
std::vector<int> shuffle_map;
|
||||
|
|
@ -777,7 +777,7 @@ grow_read_ports:;
|
|||
for (auto it : match.min_limits) {
|
||||
if (!match_properties.count(it.first))
|
||||
log_error("Unknown property '%s' in match rule for bram type %s.\n",
|
||||
it.first.c_str(), match.name.unescape());
|
||||
it.first.c_str(), design->twines.unescaped_str(match.name));
|
||||
if (match_properties[it.first] >= it.second)
|
||||
continue;
|
||||
log(" Rule for bram type %s rejected: requirement 'min %s %d' not met.\n",
|
||||
|
|
@ -787,7 +787,7 @@ grow_read_ports:;
|
|||
for (auto it : match.max_limits) {
|
||||
if (!match_properties.count(it.first))
|
||||
log_error("Unknown property '%s' in match rule for bram type %s.\n",
|
||||
it.first.c_str(), match.name.unescape());
|
||||
it.first.c_str(), design->twines.unescaped_str(match.name));
|
||||
if (match_properties[it.first] <= it.second)
|
||||
continue;
|
||||
log(" Rule for bram type %s rejected: requirement 'max %s %d' not met.\n",
|
||||
|
|
@ -821,7 +821,7 @@ grow_read_ports:;
|
|||
if (!exists)
|
||||
ss << "!";
|
||||
IdString key = std::get<1>(sums.front());
|
||||
ss << key.unescape();
|
||||
ss << design->twines.unescaped_str(key);
|
||||
const Const &value = rules.map_case(std::get<2>(sums.front()));
|
||||
if (exists && value != Const(1))
|
||||
ss << "=\"" << value.decode_string() << "\"";
|
||||
|
|
@ -936,7 +936,7 @@ grow_read_ports:;
|
|||
for (int dupidx = 0; dupidx < dup_count; dupidx++)
|
||||
{
|
||||
Cell *c = module->addCell(module->uniquify(module->design->twines.add(Twine{stringf("%s.%d.%d.%d", mem.memid.str(), grid_d, grid_a, dupidx)})), bram.name);
|
||||
log(" Creating %s cell at grid position <%d %d %d>: %s\n", bram.name.unescape(), grid_d, grid_a, dupidx, c);
|
||||
log(" Creating %s cell at grid position <%d %d %d>: %s\n", design->twines.unescaped_str(bram.name), grid_d, grid_a, dupidx, c);
|
||||
|
||||
for (auto &vp : variant_params)
|
||||
c->setParam(vp.first, vp.second);
|
||||
|
|
@ -1066,7 +1066,7 @@ grow_read_ports:;
|
|||
|
||||
void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
|
||||
{
|
||||
log("Processing %s.%s:\n", mem.module, mem.memid.unescape());
|
||||
log("Processing %s.%s:\n", mem.module, design->twines.unescaped_str(mem.memid));
|
||||
mem.narrow();
|
||||
|
||||
bool cell_init = !mem.inits.empty();
|
||||
|
|
@ -1093,7 +1093,7 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
|
|||
auto &match = rules.matches.at(i);
|
||||
|
||||
if (!rules.brams.count(rules.matches[i].name))
|
||||
log_error("No bram description for resource %s found!\n", rules.matches[i].name.unescape());
|
||||
log_error("No bram description for resource %s found!\n", design->twines.unescaped_str(rules.matches[i].name));
|
||||
|
||||
for (int vi = 0; vi < GetSize(rules.brams.at(match.name)); vi++)
|
||||
{
|
||||
|
|
@ -1109,7 +1109,7 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
|
|||
avail_wr_ports += GetSize(bram.ports) < j ? bram.ports.at(j) : 0;
|
||||
}
|
||||
|
||||
log(" Checking rule #%d for bram type %s (variant %d):\n", i+1, bram.name.unescape(), bram.variant);
|
||||
log(" Checking rule #%d for bram type %s (variant %d):\n", i+1, design->twines.unescaped_str(bram.name), bram.variant);
|
||||
log(" Bram geometry: abits=%d dbits=%d wports=%d rports=%d\n", bram.abits, bram.dbits, avail_wr_ports, avail_rd_ports);
|
||||
|
||||
int dups = avail_rd_ports ? (match_properties["rports"] + avail_rd_ports - 1) / avail_rd_ports : 1;
|
||||
|
|
@ -1143,7 +1143,7 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
|
|||
|
||||
if (cell_init && bram.init == 0) {
|
||||
log(" Rule #%d for bram type %s (variant %d) rejected: cannot be initialized.\n",
|
||||
i+1, bram.name.unescape(), bram.variant);
|
||||
i+1, design->twines.unescaped_str(bram.name), bram.variant);
|
||||
goto next_match_rule;
|
||||
}
|
||||
|
||||
|
|
@ -1152,11 +1152,11 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
|
|||
continue;
|
||||
if (!match_properties.count(it.first))
|
||||
log_error("Unknown property '%s' in match rule for bram type %s.\n",
|
||||
it.first.c_str(), match.name.unescape());
|
||||
it.first.c_str(), design->twines.unescaped_str(match.name));
|
||||
if (match_properties[it.first] >= it.second)
|
||||
continue;
|
||||
log(" Rule #%d for bram type %s (variant %d) rejected: requirement 'min %s %d' not met.\n",
|
||||
i+1, bram.name.unescape(), bram.variant, it.first.c_str(), it.second);
|
||||
i+1, design->twines.unescaped_str(bram.name), bram.variant, it.first.c_str(), it.second);
|
||||
goto next_match_rule;
|
||||
}
|
||||
|
||||
|
|
@ -1165,11 +1165,11 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
|
|||
continue;
|
||||
if (!match_properties.count(it.first))
|
||||
log_error("Unknown property '%s' in match rule for bram type %s.\n",
|
||||
it.first.c_str(), match.name.unescape());
|
||||
it.first.c_str(), design->twines.unescaped_str(match.name));
|
||||
if (match_properties[it.first] <= it.second)
|
||||
continue;
|
||||
log(" Rule #%d for bram type %s (variant %d) rejected: requirement 'max %s %d' not met.\n",
|
||||
i+1, bram.name.unescape(), bram.variant, it.first.c_str(), it.second);
|
||||
i+1, design->twines.unescaped_str(bram.name), bram.variant, it.first.c_str(), it.second);
|
||||
goto next_match_rule;
|
||||
}
|
||||
|
||||
|
|
@ -1199,7 +1199,7 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
|
|||
if (!exists)
|
||||
ss << "!";
|
||||
IdString key = std::get<1>(sums.front());
|
||||
ss << key.unescape();
|
||||
ss << design->twines.unescaped_str(key);
|
||||
const Const &value = rules.map_case(std::get<2>(sums.front()));
|
||||
if (exists && value != Const(1))
|
||||
ss << "=\"" << value.decode_string() << "\"";
|
||||
|
|
@ -1210,7 +1210,7 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
|
|||
}
|
||||
}
|
||||
|
||||
log(" Rule #%d for bram type %s (variant %d) accepted.\n", i+1, bram.name.unescape(), bram.variant);
|
||||
log(" Rule #%d for bram type %s (variant %d) accepted.\n", i+1, design->twines.unescaped_str(bram.name), bram.variant);
|
||||
|
||||
if (or_next_if_better || !best_rule_cache.empty())
|
||||
{
|
||||
|
|
@ -1218,7 +1218,7 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
|
|||
log_error("Found 'or_next_if_better' in last match rule.\n");
|
||||
|
||||
if (!replace_memory(mem, rules, initvals, bram, match, match_properties, 1)) {
|
||||
log(" Mapping to bram type %s failed.\n", match.name.unescape());
|
||||
log(" Mapping to bram type %s failed.\n", design->twines.unescaped_str(match.name));
|
||||
failed_brams.insert(pair<IdString, int>(bram.name, bram.variant));
|
||||
goto next_match_rule;
|
||||
}
|
||||
|
|
@ -1245,12 +1245,12 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
|
|||
|
||||
auto &best_bram = rules.brams.at(rules.matches.at(best_rule.first).name).at(best_rule.second);
|
||||
if (!replace_memory(mem, rules, initvals, best_bram, rules.matches.at(best_rule.first), match_properties, 2))
|
||||
log_error("Mapping to bram type %s (variant %d) after pre-selection failed.\n", best_bram.name.unescape(), best_bram.variant);
|
||||
log_error("Mapping to bram type %s (variant %d) after pre-selection failed.\n", design->twines.unescaped_str(best_bram.name), best_bram.variant);
|
||||
return;
|
||||
}
|
||||
|
||||
if (!replace_memory(mem, rules, initvals, bram, match, match_properties, 0)) {
|
||||
log(" Mapping to bram type %s failed.\n", match.name.unescape());
|
||||
log(" Mapping to bram type %s failed.\n", design->twines.unescaped_str(match.name));
|
||||
failed_brams.insert(pair<IdString, int>(bram.name, bram.variant));
|
||||
goto next_match_rule;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -174,7 +174,7 @@ struct MemQueryCache
|
|||
if (GetSize(drivers) != 1)
|
||||
return false;
|
||||
auto driver = *drivers.begin();
|
||||
if (!driver.cell->type.in(ID($mux), ID($pmux)))
|
||||
if (!driver.cell->type.in(TW($mux), TW($pmux)))
|
||||
return false;
|
||||
log_assert(driver.port == TW::Y);
|
||||
SigSpec sig_s = driver.cell->getPort(TW::S);
|
||||
|
|
@ -247,7 +247,7 @@ struct MemoryDffWorker
|
|||
continue;
|
||||
auto consumer = *consumers.begin();
|
||||
bool is_b;
|
||||
if (consumer.cell->type == ID($mux)) {
|
||||
if (consumer.cell->type == TW($mux)) {
|
||||
if (consumer.port == TW::A) {
|
||||
is_b = false;
|
||||
} else if (consumer.port == TW::B) {
|
||||
|
|
@ -255,7 +255,7 @@ struct MemoryDffWorker
|
|||
} else {
|
||||
continue;
|
||||
}
|
||||
} else if (consumer.cell->type == ID($pmux)) {
|
||||
} else if (consumer.cell->type == TW($pmux)) {
|
||||
if (consumer.port == TW::A) {
|
||||
is_b = false;
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -140,7 +140,7 @@ struct MapWorker {
|
|||
MapWorker(Module *module) : module(module), modwalker(module->design, module), sigmap(module), sigmap_xmux(module), initvals(&sigmap, module) {
|
||||
for (auto cell : module->cells())
|
||||
{
|
||||
if (cell->type == ID($mux))
|
||||
if (cell->type == TW($mux))
|
||||
{
|
||||
RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(TW::A));
|
||||
RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(TW::B));
|
||||
|
|
@ -204,7 +204,7 @@ struct MemMapping {
|
|||
if (!check_init(rdef))
|
||||
continue;
|
||||
if (rdef.prune_rom && mem.wr_ports.empty()) {
|
||||
log_debug("memory %s.%s: rejecting mapping to %s: ROM mapping disabled (prune_rom set)\n", log_id(mem.module), mem.memid.unescape(), rdef.id.unescape());
|
||||
log_debug("memory %s.%s: rejecting mapping to %s: ROM mapping disabled (prune_rom set)\n", log_id(mem.module), design->twines.unescaped_str(mem.memid), mem.module->design->twines.unescaped_str(rdef.id));
|
||||
continue;
|
||||
}
|
||||
MemConfig cfg;
|
||||
|
|
@ -323,7 +323,7 @@ struct MemMapping {
|
|||
|
||||
void log_reject(const Ram &ram, std::string message) {
|
||||
if(ys_debug(1)) {
|
||||
rejected_cfg_debug_msgs += stringf("can't map to to %s: ", ram.id.unescape());
|
||||
rejected_cfg_debug_msgs += stringf("can't map to to %s: ", mem.module->design->twines.unescaped_str(ram.id));
|
||||
rejected_cfg_debug_msgs += message;
|
||||
rejected_cfg_debug_msgs += "\n";
|
||||
}
|
||||
|
|
@ -338,7 +338,7 @@ struct MemMapping {
|
|||
rejected_cfg_debug_msgs += portname;
|
||||
first = false;
|
||||
}
|
||||
rejected_cfg_debug_msgs += stringf("] of %s: ", ram.id.unescape());
|
||||
rejected_cfg_debug_msgs += stringf("] of %s: ", mem.module->design->twines.unescaped_str(ram.id));
|
||||
rejected_cfg_debug_msgs += message;
|
||||
rejected_cfg_debug_msgs += "\n";
|
||||
}
|
||||
|
|
@ -361,7 +361,7 @@ struct MemMapping {
|
|||
rejected_cfg_debug_msgs += portname;
|
||||
first = false;
|
||||
}
|
||||
rejected_cfg_debug_msgs += stringf("] of %s: ", ram.id.unescape());
|
||||
rejected_cfg_debug_msgs += stringf("] of %s: ", mem.module->design->twines.unescaped_str(ram.id));
|
||||
rejected_cfg_debug_msgs += message;
|
||||
rejected_cfg_debug_msgs += "\n";
|
||||
}
|
||||
|
|
@ -380,7 +380,7 @@ void MemMapping::dump_configs(int stage) {
|
|||
default:
|
||||
abort();
|
||||
}
|
||||
log_debug("Memory %s.%s mapping candidates (%s):\n", log_id(mem.module), mem.memid.unescape(), stage_name);
|
||||
log_debug("Memory %s.%s mapping candidates (%s):\n", log_id(mem.module), design->twines.unescaped_str(mem.memid), stage_name);
|
||||
if (logic_ok) {
|
||||
log_debug("- logic fallback\n");
|
||||
log_debug(" - cost: %f\n", logic_cost);
|
||||
|
|
@ -391,7 +391,7 @@ void MemMapping::dump_configs(int stage) {
|
|||
}
|
||||
|
||||
void MemMapping::dump_config(MemConfig &cfg) {
|
||||
log_debug("- %s:\n", cfg.def->id.unescape());
|
||||
log_debug("- %s:\n", mem.module->design->twines.unescaped_str(cfg.def->id));
|
||||
for (auto &it: cfg.def->options)
|
||||
log_debug(" - option %s %s\n", it.first, log_const(it.second));
|
||||
log_debug(" - emulation score: %d\n", cfg.score_emu);
|
||||
|
|
@ -527,7 +527,7 @@ void MemMapping::determine_style() {
|
|||
auto find_attr = search_for_attribute(mem, ID::lram);
|
||||
if (find_attr.first && find_attr.second.as_bool()) {
|
||||
kind = RamKind::Huge;
|
||||
log("found attribute 'lram' on memory %s.%s, forced mapping to huge RAM\n", log_id(mem.module), mem.memid.unescape());
|
||||
log("found attribute 'lram' on memory %s.%s, forced mapping to huge RAM\n", log_id(mem.module), design->twines.unescaped_str(mem.memid));
|
||||
return;
|
||||
}
|
||||
for (auto attr: {ID::ram_block, ID::rom_block, ID::ram_style, ID::rom_style, ID::ramstyle, ID::romstyle, ID::syn_ramstyle, ID::syn_romstyle}) {
|
||||
|
|
@ -536,7 +536,7 @@ void MemMapping::determine_style() {
|
|||
Const val = find_attr.second;
|
||||
if (val == 1) {
|
||||
kind = RamKind::NotLogic;
|
||||
log("found attribute '%s = 1' on memory %s.%s, disabled mapping to FF\n", attr.unescape(), log_id(mem.module), mem.memid.unescape());
|
||||
log("found attribute '%s = 1' on memory %s.%s, disabled mapping to FF\n", design->twines.unescaped_str(attr), log_id(mem.module), design->twines.unescaped_str(mem.memid));
|
||||
return;
|
||||
}
|
||||
std::string val_s = val.decode_string();
|
||||
|
|
@ -549,20 +549,20 @@ void MemMapping::determine_style() {
|
|||
// Nothing.
|
||||
} else if (val_s == "logic" || val_s == "registers") {
|
||||
kind = RamKind::Logic;
|
||||
log("found attribute '%s = %s' on memory %s.%s, forced mapping to FF\n", attr.unescape(), val_s, log_id(mem.module), mem.memid.unescape());
|
||||
log("found attribute '%s = %s' on memory %s.%s, forced mapping to FF\n", design->twines.unescaped_str(attr), val_s, log_id(mem.module), design->twines.unescaped_str(mem.memid));
|
||||
} else if (val_s == "distributed") {
|
||||
kind = RamKind::Distributed;
|
||||
log("found attribute '%s = %s' on memory %s.%s, forced mapping to distributed RAM\n", attr.unescape(), val_s, log_id(mem.module), mem.memid.unescape());
|
||||
log("found attribute '%s = %s' on memory %s.%s, forced mapping to distributed RAM\n", design->twines.unescaped_str(attr), val_s, log_id(mem.module), design->twines.unescaped_str(mem.memid));
|
||||
} else if (val_s == "block" || val_s == "block_ram" || val_s == "ebr") {
|
||||
kind = RamKind::Block;
|
||||
log("found attribute '%s = %s' on memory %s.%s, forced mapping to block RAM\n", attr.unescape(), val_s, log_id(mem.module), mem.memid.unescape());
|
||||
log("found attribute '%s = %s' on memory %s.%s, forced mapping to block RAM\n", design->twines.unescaped_str(attr), val_s, log_id(mem.module), design->twines.unescaped_str(mem.memid));
|
||||
} else if (val_s == "huge" || val_s == "ultra") {
|
||||
kind = RamKind::Huge;
|
||||
log("found attribute '%s = %s' on memory %s.%s, forced mapping to huge RAM\n", attr.unescape(), val_s, log_id(mem.module), mem.memid.unescape());
|
||||
log("found attribute '%s = %s' on memory %s.%s, forced mapping to huge RAM\n", design->twines.unescaped_str(attr), val_s, log_id(mem.module), design->twines.unescaped_str(mem.memid));
|
||||
} else {
|
||||
kind = RamKind::NotLogic;
|
||||
style = val_s;
|
||||
log("found attribute '%s = %s' on memory %s.%s, forced mapping to %s RAM\n", attr.unescape(), val_s, log_id(mem.module), mem.memid.unescape(), val_s);
|
||||
log("found attribute '%s = %s' on memory %s.%s, forced mapping to %s RAM\n", design->twines.unescaped_str(attr), val_s, log_id(mem.module), design->twines.unescaped_str(mem.memid), val_s);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
|
@ -1991,7 +1991,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
|
|||
}
|
||||
|
||||
void MemMapping::emit(const MemConfig &cfg) {
|
||||
log("mapping memory %s.%s via %s\n", log_id(mem.module), mem.memid.unescape(), cfg.def->id.unescape());
|
||||
log("mapping memory %s.%s via %s\n", log_id(mem.module), design->twines.unescaped_str(mem.memid), mem.module->design->twines.unescaped_str(cfg.def->id));
|
||||
// First, handle emulations.
|
||||
if (cfg.emu_read_first)
|
||||
mem.emulate_read_first(&worker.initvals);
|
||||
|
|
@ -2068,7 +2068,7 @@ void MemMapping::emit(const MemConfig &cfg) {
|
|||
for (int rp = 0; rp < cfg.repl_port; rp++) {
|
||||
std::vector<Cell *> cells;
|
||||
for (int rd = 0; rd < cfg.repl_d; rd++) {
|
||||
Cell *cell = mem.module->addCell(mem.module->design->twines.add(Twine{stringf("%s.%d.%d", mem.memid.str(), rp, rd)}), cfg.def->id);
|
||||
Cell *cell = mem.module->addCell(Twine{stringf("%s.%d.%d", mem.memid.str(), rp, rd)}, cfg.def->id);
|
||||
if (cfg.def->width_mode == WidthMode::Global || opts.force_params)
|
||||
cell->setParam(ID::WIDTH, cfg.def->dbits[cfg.base_width_log2]);
|
||||
if (opts.force_params)
|
||||
|
|
@ -2252,9 +2252,9 @@ struct MemoryLibMapPass : public Pass {
|
|||
int best = map.logic_cost;
|
||||
if (!map.logic_ok) {
|
||||
if (map.cfgs.empty()) {
|
||||
log_debug("Rejected candidates for mapping memory %s.%s:\n", log_id(module), mem.memid.unescape());
|
||||
log_debug("Rejected candidates for mapping memory %s.%s:\n", log_id(module), design->twines.unescaped_str(mem.memid));
|
||||
log_debug("%s", map.rejected_cfg_debug_msgs);
|
||||
log_error("no valid mapping found for memory %s.%s\n", log_id(module), mem.memid.unescape());
|
||||
log_error("no valid mapping found for memory %s.%s\n", log_id(module), design->twines.unescaped_str(mem.memid));
|
||||
}
|
||||
idx = 0;
|
||||
best = map.cfgs[0].cost;
|
||||
|
|
@ -2266,7 +2266,7 @@ struct MemoryLibMapPass : public Pass {
|
|||
}
|
||||
}
|
||||
if (idx == -1) {
|
||||
log("using FF mapping for memory %s.%s\n", log_id(module), mem.memid.unescape());
|
||||
log("using FF mapping for memory %s.%s\n", log_id(module), design->twines.unescaped_str(mem.memid));
|
||||
} else {
|
||||
map.emit(map.cfgs[idx]);
|
||||
// Rebuild indices after modifying module
|
||||
|
|
|
|||
|
|
@ -238,17 +238,17 @@ struct MemoryMapWorker
|
|||
if (static_only) {
|
||||
// non-static part is a ROM, we only reach this with keepdc
|
||||
if (formal) {
|
||||
c = module->addCell(design->twines.add(Twine{ff_id}), ID($ff));
|
||||
c = module->addCell(Twine{ff_id}, TW($ff));
|
||||
} else {
|
||||
c = module->addCell(design->twines.add(Twine{ff_id}), ID($dff));
|
||||
c = module->addCell(Twine{ff_id}, TW($dff));
|
||||
c->parameters[ID::CLK_POLARITY] = RTLIL::Const(RTLIL::State::S1);
|
||||
c->setPort(TW::CLK, RTLIL::SigSpec(RTLIL::State::S0));
|
||||
}
|
||||
} else if (async_wr) {
|
||||
log_assert(formal); // General async write not implemented yet, checked against above
|
||||
c = module->addCell(design->twines.add(Twine{ff_id}), ID($ff));
|
||||
c = module->addCell(Twine{ff_id}, TW($ff));
|
||||
} else {
|
||||
c = module->addCell(design->twines.add(Twine{ff_id}), ID($dff));
|
||||
c = module->addCell(Twine{ff_id}, TW($dff));
|
||||
c->parameters[ID::CLK_POLARITY] = RTLIL::Const(refclock_pol);
|
||||
c->setPort(TW::CLK, refclock);
|
||||
}
|
||||
|
|
@ -306,15 +306,15 @@ struct MemoryMapWorker
|
|||
|
||||
for (size_t k = 0; k < rd_signals.size(); k++)
|
||||
{
|
||||
RTLIL::Cell *c = module->addCell(design->twines.add(Twine{genid(mem.memid, "$rdmux", i, "", j, "", k)}), ID($mux));
|
||||
RTLIL::Cell *c = module->addCell(Twine{genid(mem.memid, "$rdmux", i, "", j, "", k)}, TW($mux));
|
||||
c->set_src_attribute(mem_src.empty() ? Twine::Null : design->twines.add(Twine{mem_src}));
|
||||
c->parameters[ID::WIDTH] = GetSize(port.data);
|
||||
c->setPort(TW::Y, rd_signals[k]);
|
||||
c->setPort(TW::S, rd_addr.extract(abits-j-1, 1));
|
||||
count_mux++;
|
||||
|
||||
c->setPort(TW::A, module->addWire(design->twines.add(Twine{genid(mem.memid, "$rdmux", i, "", j, "", k, "$a")}), GetSize(port.data)));
|
||||
c->setPort(TW::B, module->addWire(design->twines.add(Twine{genid(mem.memid, "$rdmux", i, "", j, "", k, "$b")}), GetSize(port.data)));
|
||||
c->setPort(TW::A, module->addWire(Twine{genid(mem.memid, "$rdmux", i, "", j, "", k, "$a")}, GetSize(port.data)));
|
||||
c->setPort(TW::B, module->addWire(Twine{genid(mem.memid, "$rdmux", i, "", j, "", k, "$b")}, GetSize(port.data)));
|
||||
|
||||
next_rd_signals.push_back(c->getPort(TW::A));
|
||||
next_rd_signals.push_back(c->getPort(TW::B));
|
||||
|
|
@ -366,7 +366,7 @@ struct MemoryMapWorker
|
|||
|
||||
if (wr_bit != State::S1)
|
||||
{
|
||||
RTLIL::Cell *c = module->addCell(design->twines.add(Twine{genid(mem.memid, "$wren", addr, "", j, "", wr_offset)}), ID($and));
|
||||
RTLIL::Cell *c = module->addCell(design->twines.add(Twine{genid(mem.memid, "$wren", addr, "", j, "", wr_offset)}), TW($and));
|
||||
c->set_src_attribute(mem_src.empty() ? Twine::Null : design->twines.add(Twine{mem_src}));
|
||||
c->parameters[ID::A_SIGNED] = RTLIL::Const(0);
|
||||
c->parameters[ID::B_SIGNED] = RTLIL::Const(0);
|
||||
|
|
@ -380,7 +380,7 @@ struct MemoryMapWorker
|
|||
c->setPort(TW::Y, RTLIL::SigSpec(w));
|
||||
}
|
||||
|
||||
RTLIL::Cell *c = module->addCell(design->twines.add(Twine{genid(mem.memid, "$wrmux", addr, "", j, "", wr_offset)}), ID($mux));
|
||||
RTLIL::Cell *c = module->addCell(design->twines.add(Twine{genid(mem.memid, "$wrmux", addr, "", j, "", wr_offset)}), TW($mux));
|
||||
c->set_src_attribute(mem_src.empty() ? Twine::Null : design->twines.add(Twine{mem_src}));
|
||||
c->parameters[ID::WIDTH] = wr_width;
|
||||
c->setPort(TW::A, sig.extract(wr_offset, wr_width));
|
||||
|
|
|
|||
|
|
@ -60,7 +60,7 @@ struct MemoryMemxPass : public Pass {
|
|||
{
|
||||
if (port.clk_enable)
|
||||
log_error("Memory %s.%s has a synchronous read port. Synchronous read ports are not supported by memory_memx!\n",
|
||||
module, mem.memid.unescape());
|
||||
module, design->twines.unescaped_str(mem.memid));
|
||||
|
||||
SigSpec addr_ok = make_addr_check(mem, port.addr);
|
||||
Wire *raw_rdata = module->addWire(NEW_TWINE, GetSize(port.data));
|
||||
|
|
|
|||
|
|
@ -80,7 +80,7 @@ struct MemoryShareWorker
|
|||
if (GetSize(mem.rd_ports) <= 1)
|
||||
return false;
|
||||
|
||||
log("Consolidating read ports of memory %s.%s by address:\n", module, mem.memid.unescape());
|
||||
log("Consolidating read ports of memory %s.%s by address:\n", module, design->twines.unescaped_str(mem.memid));
|
||||
|
||||
bool changed = false;
|
||||
int abits = 0;
|
||||
|
|
@ -197,7 +197,7 @@ struct MemoryShareWorker
|
|||
if (GetSize(mem.wr_ports) <= 1)
|
||||
return false;
|
||||
|
||||
log("Consolidating write ports of memory %s.%s by address:\n", module, mem.memid.unescape());
|
||||
log("Consolidating write ports of memory %s.%s by address:\n", module, design->twines.unescaped_str(mem.memid));
|
||||
|
||||
bool changed = false;
|
||||
int abits = 0;
|
||||
|
|
@ -316,7 +316,7 @@ struct MemoryShareWorker
|
|||
if (eligible_ports.size() <= 1)
|
||||
return;
|
||||
|
||||
log("Consolidating write ports of memory %s.%s using sat-based resource sharing:\n", module, mem.memid.unescape());
|
||||
log("Consolidating write ports of memory %s.%s using sat-based resource sharing:\n", module, design->twines.unescaped_str(mem.memid));
|
||||
|
||||
// Group eligible ports by clock domain and width.
|
||||
|
||||
|
|
@ -482,7 +482,7 @@ struct MemoryShareWorker
|
|||
sigmap_xmux = sigmap;
|
||||
for (auto cell : module->cells())
|
||||
{
|
||||
if (cell->type == ID($mux))
|
||||
if (cell->type == TW($mux))
|
||||
{
|
||||
RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(TW::A));
|
||||
RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(TW::B));
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ struct ExclusiveDatabase
|
|||
SigBit y_port;
|
||||
pool<Cell*> reduce_or;
|
||||
for (auto cell : module->cells()) {
|
||||
if (cell->type == ID($eq)) {
|
||||
if (cell->type == TW($eq)) {
|
||||
SigSpec y_sig = sigmap(cell->getPort(TW::Y));
|
||||
if (GetSize(y_sig) == 0)
|
||||
continue;
|
||||
|
|
@ -50,7 +50,7 @@ struct ExclusiveDatabase
|
|||
}
|
||||
y_port = y_sig[0];
|
||||
}
|
||||
else if (cell->type == ID($logic_not)) {
|
||||
else if (cell->type == TW($logic_not)) {
|
||||
SigSpec y_sig = sigmap(cell->getPort(TW::Y));
|
||||
if (GetSize(y_sig) == 0)
|
||||
continue;
|
||||
|
|
@ -58,7 +58,7 @@ struct ExclusiveDatabase
|
|||
const_sig = Const(State::S0, GetSize(nonconst_sig));
|
||||
y_port = y_sig[0];
|
||||
}
|
||||
else if (cell->type == ID($reduce_or)) {
|
||||
else if (cell->type == TW($reduce_or)) {
|
||||
reduce_or.insert(cell);
|
||||
continue;
|
||||
}
|
||||
|
|
@ -152,11 +152,11 @@ struct MuxpackWorker
|
|||
|
||||
for (auto cell : module->cells())
|
||||
{
|
||||
if (cell->type.in(ID($mux), ID($pmux)) && !cell->get_bool_attribute(ID::keep))
|
||||
if (cell->type.in(TW($mux), TW($pmux)) && !cell->get_bool_attribute(ID::keep))
|
||||
{
|
||||
SigSpec a_sig = sigmap(cell->getPort(TW::A));
|
||||
SigSpec b_sig;
|
||||
if (cell->type == ID($mux))
|
||||
if (cell->type == TW($mux))
|
||||
b_sig = sigmap(cell->getPort(TW::B));
|
||||
SigSpec y_sig = sigmap(cell->getPort(TW::Y));
|
||||
|
||||
|
|
@ -193,10 +193,10 @@ struct MuxpackWorker
|
|||
{
|
||||
for (auto cell : candidate_cells)
|
||||
{
|
||||
log_debug("Considering %s (%s)\n", cell, cell->type.unescape());
|
||||
log_debug("Considering %s (%s)\n", cell, cell->type.unescaped());
|
||||
|
||||
SigSpec a_sig = sigmap(cell->getPort(TW::A));
|
||||
if (cell->type == ID($mux)) {
|
||||
if (cell->type == TW($mux)) {
|
||||
SigSpec b_sig = sigmap(cell->getPort(TW::B));
|
||||
if (sig_chain_prev.count(a_sig) + sig_chain_prev.count(b_sig) != 1)
|
||||
goto start_cell;
|
||||
|
|
@ -204,7 +204,7 @@ struct MuxpackWorker
|
|||
if (!sig_chain_prev.count(a_sig))
|
||||
a_sig = b_sig;
|
||||
}
|
||||
else if (cell->type == ID($pmux)) {
|
||||
else if (cell->type == TW($pmux)) {
|
||||
if (!sig_chain_prev.count(a_sig))
|
||||
goto start_cell;
|
||||
}
|
||||
|
|
@ -289,7 +289,7 @@ struct MuxpackWorker
|
|||
s_sig.append(cursor_cell->getPort(TW::S));
|
||||
}
|
||||
else {
|
||||
log_assert(cursor_cell->type == ID($mux));
|
||||
log_assert(cursor_cell->type == TW($mux));
|
||||
b_sig.append(cursor_cell->getPort(TW::A));
|
||||
s_sig.append(module->LogicNot(NEW_TWINE, cursor_cell->getPort(TW::S)));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -48,10 +48,10 @@ struct OptBalanceTreeWorker {
|
|||
|
||||
// Calculate the "natural" output width for this operation
|
||||
int natural_width;
|
||||
if (cell_type == ID($add)) {
|
||||
if (cell_type == TW($add)) {
|
||||
// Addition produces max(A_WIDTH, B_WIDTH) + 1 (for carry bit)
|
||||
natural_width = std::max(a_width, b_width) + 1;
|
||||
} else if (cell_type == ID($mul)) {
|
||||
} else if (cell_type == TW($mul)) {
|
||||
// Multiplication produces A_WIDTH + B_WIDTH
|
||||
natural_width = a_width + b_width;
|
||||
} else {
|
||||
|
|
@ -84,9 +84,9 @@ struct OptBalanceTreeWorker {
|
|||
|
||||
// Create output wire
|
||||
int out_width = cell->getParam(ID::Y_WIDTH).as_int();
|
||||
if (cell_type == ID($add))
|
||||
if (cell_type == TW($add))
|
||||
out_width = max(sources[0].size(), sources[1].size()) + 1;
|
||||
else if (cell_type == ID($mul))
|
||||
else if (cell_type == TW($mul))
|
||||
out_width = sources[0].size() + sources[1].size();
|
||||
Wire* out_wire = module->addWire(NEW_TWINE, out_width);
|
||||
|
||||
|
|
@ -119,9 +119,9 @@ struct OptBalanceTreeWorker {
|
|||
|
||||
// Create output wire
|
||||
int out_width = cell->getParam(ID::Y_WIDTH).as_int();
|
||||
if (cell_type == ID($add))
|
||||
if (cell_type == TW($add))
|
||||
out_width = max(left_tree.size(), right_tree.size()) + 1;
|
||||
else if (cell_type == ID($mul))
|
||||
else if (cell_type == TW($mul))
|
||||
out_width = left_tree.size() + right_tree.size();
|
||||
Wire* out_wire = module->addWire(NEW_TWINE, out_width);
|
||||
|
||||
|
|
@ -344,14 +344,14 @@ struct OptBalanceTreePass : public Pass {
|
|||
|
||||
// Handle arguments
|
||||
size_t argidx;
|
||||
vector<IdString> cell_types = {ID($and), ID($or), ID($xor), ID($add), ID($mul)};
|
||||
vector<IdString> cell_types = {TW($and), TW($or), TW($xor), TW($add), TW($mul)};
|
||||
for (argidx = 1; argidx < args.size(); argidx++) {
|
||||
if (args[argidx] == "-arith") {
|
||||
cell_types = {ID($add), ID($mul)};
|
||||
cell_types = {TW($add), TW($mul)};
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-logic") {
|
||||
cell_types = {ID($and), ID($or), ID($xor)};
|
||||
cell_types = {TW($and), TW($or), TW($xor)};
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
|
|
@ -369,7 +369,7 @@ struct OptBalanceTreePass : public Pass {
|
|||
|
||||
// Log stats
|
||||
for (auto cell_type : cell_types)
|
||||
log("Converted %d %s cells into trees.\n", cell_count[cell_type], cell_type.unescape());
|
||||
log("Converted %d %s cells into trees.\n", cell_count[cell_type], design->twines.unescaped_str(cell_type));
|
||||
|
||||
// Clean up
|
||||
Yosys::run_pass("clean -purge");
|
||||
|
|
|
|||
|
|
@ -120,7 +120,7 @@ struct ConflictLogs {
|
|||
// We could do this in parallel but hopefully this is rare.
|
||||
for (auto [_, cell] : mod->cells_) {
|
||||
for (auto &[port, sig] : cell->connections()) {
|
||||
if (clean_ctx.ct_all.cell_known(cell->type) && !clean_ctx.ct_all.cell_input(cell->type, port))
|
||||
if (clean_ctx.ct_all.cell_known(cell->type_impl) && !clean_ctx.ct_all.cell_input(cell->type_impl, port))
|
||||
continue;
|
||||
for (auto raw_bit : wire_map(sig))
|
||||
used_raw_bits.insert(raw_bit);
|
||||
|
|
@ -189,17 +189,17 @@ ConflictLogs explore(CellAnalysis& analysis, CellTraversal& traversal, const Sig
|
|||
actx.subpool.run([&analysis, &traversal, &logs, &wire_map, &mem2cells_vector, &wire2driver_builder, &actx, &clean_ctx](const ParallelDispatchThreadPool::RunCtx &ctx) {
|
||||
for (int i : ctx.item_range(actx.mod->cells_size())) {
|
||||
Cell *cell = actx.mod->cell_at(i);
|
||||
if (cell->type.in(ID($memwr), ID($memwr_v2), ID($meminit), ID($meminit_v2)))
|
||||
if (cell->type.in(TW($memwr), TW($memwr_v2), TW($meminit), TW($meminit_v2)))
|
||||
mem2cells_vector.insert(ctx, {cell->getParam(ID::MEMID).decode_string(), i});
|
||||
|
||||
for (auto &it2 : cell->connections()) {
|
||||
if (clean_ctx.ct_all.cell_known(cell->type) && !clean_ctx.ct_all.cell_output(cell->type, it2.first))
|
||||
if (clean_ctx.ct_all.cell_known(cell->type_impl) && !clean_ctx.ct_all.cell_output(cell->type_impl, it2.first))
|
||||
continue;
|
||||
for (auto raw_bit : it2.second) {
|
||||
if (raw_bit.wire == nullptr)
|
||||
continue;
|
||||
auto bit = actx.assign_map(raw_bit);
|
||||
if (bit.wire == nullptr && clean_ctx.ct_all.cell_known(cell->type)) {
|
||||
if (bit.wire == nullptr && clean_ctx.ct_all.cell_known(cell->type_impl)) {
|
||||
auto twines = cell->module->design->twines;
|
||||
std::string msg = stringf("Driver-driver conflict "
|
||||
"for %s between cell %s.%s and constant %s in %s: Resolved using constant.",
|
||||
|
|
@ -257,11 +257,11 @@ void fixup_unused_cells_and_mems(CellAnalysis& analysis, MemAnalysis& mem_analys
|
|||
for (auto cell_index : cell_indices) {
|
||||
Cell *cell = actx.mod->cell_at(cell_index);
|
||||
for (auto &it : cell->connections())
|
||||
if (!clean_ctx.ct_all.cell_known(cell->type) || clean_ctx.ct_all.cell_input(cell->type, it.first))
|
||||
if (!clean_ctx.ct_all.cell_known(cell->type_impl) || clean_ctx.ct_all.cell_input(cell->type_impl, it.first))
|
||||
for (auto bit : actx.assign_map(it.second))
|
||||
bits.insert(bit);
|
||||
|
||||
if (cell->type.in(ID($memrd), ID($memrd_v2))) {
|
||||
if (cell->type.in(TW($memrd), TW($memrd_v2))) {
|
||||
std::string mem_id = cell->getParam(ID::MEMID).decode_string();
|
||||
if (mem_analysis.indices.count(mem_id)) {
|
||||
int mem_index = mem_analysis.indices[mem_id];
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ USING_YOSYS_NAMESPACE
|
|||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
||||
bool is_signed(RTLIL::Cell* cell) {
|
||||
return cell->type == ID($pos) && cell->getParam(ID::A_SIGNED).as_bool();
|
||||
return cell->type == TW($pos) && cell->getParam(ID::A_SIGNED).as_bool();
|
||||
}
|
||||
|
||||
bool trim_buf(RTLIL::Cell* cell, ShardedVector<RTLIL::SigSig>& new_connections, const ParallelDispatchThreadPool::RunCtx &ctx) {
|
||||
|
|
@ -56,16 +56,16 @@ bool remove(ShardedVector<RTLIL::Cell*>& cells, RTLIL::Module* mod, bool verbose
|
|||
bool did_something = false;
|
||||
for (RTLIL::Cell *cell : cells) {
|
||||
if (verbose) {
|
||||
if (cell->type == ID($connect)) {
|
||||
if (cell->type == TW($connect)) {
|
||||
log_debug(" removing connect cell `%s': %s <-> %s\n", cell->name,
|
||||
log_signal(cell->getPort(TW::A)), log_signal(cell->getPort(TW::B)));
|
||||
} else if (cell->type == ID($input_port)) {
|
||||
} else if (cell->type == TW($input_port)) {
|
||||
log_debug(" removing input port marker cell `%s': %s\n", cell->name,
|
||||
log_signal(cell->getPort(TW::Y)));
|
||||
} else if (cell->type == ID($output_port)) {
|
||||
} else if (cell->type == TW($output_port)) {
|
||||
log_debug(" removing output port marker cell `%s': %s\n", cell->name,
|
||||
log_signal(cell->getPort(TW::A)));
|
||||
} else if (cell->type == ID($public)) {
|
||||
} else if (cell->type == TW($public)) {
|
||||
log_debug(" removing public wire marker cell `%s': %s\n", cell->name,
|
||||
log_signal(cell->getPort(TW::A)));
|
||||
} else {
|
||||
|
|
@ -89,17 +89,17 @@ void remove_temporary_cells(RTLIL::Module *module, ParallelDispatchThreadPool::S
|
|||
subpool.run([const_module, &delcells, &new_connections](const ParallelDispatchThreadPool::RunCtx &ctx) {
|
||||
for (int i : ctx.item_range(const_module->cells_size())) {
|
||||
RTLIL::Cell *cell = const_module->cell_at(i);
|
||||
if (cell->type.in(ID($pos), ID($_BUF_), ID($buf)) && !cell->has_keep_attr()) {
|
||||
if (cell->type.in(TW($pos), TW($_BUF_), TW($buf)) && !cell->has_keep_attr()) {
|
||||
if (trim_buf(cell, new_connections, ctx))
|
||||
delcells.insert(ctx, cell);
|
||||
} else if (cell->type.in(ID($connect)) && !cell->has_keep_attr()) {
|
||||
} else if (cell->type.in(TW($connect)) && !cell->has_keep_attr()) {
|
||||
RTLIL::SigSpec a = cell->getPort(TW::A);
|
||||
RTLIL::SigSpec b = cell->getPort(TW::B);
|
||||
if (a.has_const() && !b.has_const())
|
||||
std::swap(a, b);
|
||||
new_connections.insert(ctx, {a, b});
|
||||
delcells.insert(ctx, cell);
|
||||
} else if (cell->type.in(ID($input_port), ID($output_port), ID($public)) && !cell->has_keep_attr()) {
|
||||
} else if (cell->type.in(TW($input_port), TW($output_port), TW($public)) && !cell->has_keep_attr()) {
|
||||
delcells.insert(ctx, cell);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@ ShardedVector<std::pair<SigBit, State>> build_inits(AnalysisContext& actx) {
|
|||
actx.subpool.run([&results, &actx](const ParallelDispatchThreadPool::RunCtx &ctx) {
|
||||
for (int i : ctx.item_range(actx.mod->cells_size())) {
|
||||
RTLIL::Cell *cell = actx.mod->cell_at(i);
|
||||
if (StaticCellTypes::Compat::internals_mem_ff(cell->type) && cell->hasPort(TW::Q))
|
||||
if (StaticCellTypes::Compat::internals_mem_ff(cell->type_impl) && cell->hasPort(TW::Q))
|
||||
{
|
||||
SigSpec sig = cell->getPort(TW::Q);
|
||||
|
||||
|
|
|
|||
|
|
@ -75,7 +75,7 @@ struct KeepCache
|
|||
{
|
||||
if (keep_cell(cell, purge_mode))
|
||||
return true;
|
||||
if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
|
||||
if (cell->type.in(TW($specify2), TW($specify3), TW($specrule)))
|
||||
return true;
|
||||
if (cell->module && cell->module->design) {
|
||||
RTLIL::Module *cell_module = cell->module->design->module(cell->type);
|
||||
|
|
@ -145,19 +145,19 @@ private:
|
|||
|
||||
static bool keep_cell(Cell *cell, bool purge_mode)
|
||||
{
|
||||
if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
|
||||
if (cell->type.in(TW($assert), TW($assume), TW($live), TW($fair), TW($cover)))
|
||||
return true;
|
||||
|
||||
if (cell->type.in(ID($overwrite_tag)))
|
||||
if (cell->type.in(TW($overwrite_tag)))
|
||||
return true;
|
||||
|
||||
if (cell->type == ID($print) || cell->type == ID($check))
|
||||
if (cell->type == TW($print) || cell->type == TW($check))
|
||||
return true;
|
||||
|
||||
if (cell->has_keep_attr())
|
||||
return true;
|
||||
|
||||
if (!purge_mode && cell->type == ID($scopeinfo))
|
||||
if (!purge_mode && cell->type == TW($scopeinfo))
|
||||
return true;
|
||||
return false;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -251,20 +251,20 @@ struct SigConnKinds {
|
|||
for (int i : ctx.item_range(actx.mod->cells_size())) {
|
||||
RTLIL::Cell *cell = actx.mod->cell_at(i);
|
||||
if (!purge_mode) {
|
||||
if (clean_ctx.ct_reg(cell->type)) {
|
||||
if (clean_ctx.ct_reg(cell->type_impl)) {
|
||||
// Improve witness signal naming when clk2fflogic used
|
||||
// see commit message e36c71b5
|
||||
bool clk2fflogic = cell->get_bool_attribute(ID::clk2fflogic);
|
||||
for (auto &[port, sig] : cell->connections())
|
||||
if (clk2fflogic ? port == TW::D : clean_ctx.ct_all.cell_output(cell->type, port))
|
||||
if (clk2fflogic ? port == TW::D : clean_ctx.ct_all.cell_output(cell->type_impl, port))
|
||||
add_spec(raw_register_builder, ctx, sig);
|
||||
}
|
||||
for (auto &[_, sig] : cell->connections())
|
||||
add_spec(raw_cell_connected_builder, ctx, sig);
|
||||
}
|
||||
if (clean_ctx.ct_all.cell_known(cell->type))
|
||||
if (clean_ctx.ct_all.cell_known(cell->type_impl))
|
||||
for (auto &[port, sig] : cell->connections())
|
||||
if (clean_ctx.ct_all.cell_output(cell->type, port)) {
|
||||
if (clean_ctx.ct_all.cell_output(cell->type_impl, port)) {
|
||||
RTLIL::SigSpec spec = actx.assign_map(sig);
|
||||
unsigned int hash = spec.hash_into(Hasher()).yield();
|
||||
exact_cell_output_builder.insert(ctx, {std::move(spec), hash});
|
||||
|
|
@ -367,7 +367,7 @@ DeferredUpdates analyse_connectivity(UsedSignals& used, SigConnKinds& sig_analys
|
|||
deferred.update_connections.insert(ctx, {cell, port, spec});
|
||||
add_spec(raw_conn_builder, ctx, spec);
|
||||
add_spec(conn_builder, ctx, spec);
|
||||
if (!clean_ctx.ct_all.cell_output(cell->type, port))
|
||||
if (!clean_ctx.ct_all.cell_output(cell->type_impl, port))
|
||||
add_spec(used_builder, ctx, spec);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ void demorgan_worker(
|
|||
//TODO: Add support for reduce_xor
|
||||
//DeMorgan of XOR is either XOR (if even number of inputs) or XNOR (if odd number)
|
||||
|
||||
if( (cell->type != ID($reduce_and)) && (cell->type != ID($reduce_or)) )
|
||||
if( (cell->type != TW($reduce_and)) && (cell->type != TW($reduce_or)) )
|
||||
return;
|
||||
|
||||
auto insig = sigmap(cell->getPort(TW::A));
|
||||
|
|
@ -43,7 +43,7 @@ void demorgan_worker(
|
|||
if (GetSize(insig) < 1)
|
||||
return;
|
||||
|
||||
log("Inspecting %s cell %s (%d inputs)\n", cell->type.unescape(), cell->module->design->twines.str(cell->meta_->name), GetSize(insig));
|
||||
log("Inspecting %s cell %s (%d inputs)\n", cell->type.unescaped(), cell->module->design->twines.str(cell->meta_->name), GetSize(insig));
|
||||
int num_inverted = 0;
|
||||
for(int i=0; i<GetSize(insig); i++)
|
||||
{
|
||||
|
|
@ -55,7 +55,7 @@ void demorgan_worker(
|
|||
bool inverted = false;
|
||||
for(auto x : ports)
|
||||
{
|
||||
if(x.port == TW::Y && x.cell->type == ID($_NOT_))
|
||||
if(x.port == TW::Y && x.cell->type == TW($_NOT_))
|
||||
{
|
||||
inverted = true;
|
||||
break;
|
||||
|
|
@ -89,7 +89,7 @@ void demorgan_worker(
|
|||
RTLIL::Cell* srcinv = NULL;
|
||||
for(auto x : ports)
|
||||
{
|
||||
if(x.port == TW::Y && x.cell->type == ID($_NOT_))
|
||||
if(x.port == TW::Y && x.cell->type == TW($_NOT_))
|
||||
{
|
||||
srcinv = x.cell;
|
||||
break;
|
||||
|
|
@ -158,9 +158,9 @@ void demorgan_worker(
|
|||
cell->setPort(TW::A, insig);
|
||||
|
||||
//Change the cell type
|
||||
if(cell->type == ID($reduce_and))
|
||||
if(cell->type == TW($reduce_and))
|
||||
cell->type_impl = TW::$reduce_or;
|
||||
else if(cell->type == ID($reduce_or))
|
||||
else if(cell->type == TW($reduce_or))
|
||||
cell->type_impl = TW::$reduce_and;
|
||||
//don't change XOR
|
||||
|
||||
|
|
|
|||
|
|
@ -123,7 +123,7 @@ struct OptDffWorker
|
|||
bitusers[bit]++;
|
||||
|
||||
for (auto cell : module->cells()) {
|
||||
if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_))) {
|
||||
if (cell->type.in(TW($mux), TW($pmux), TW($_MUX_))) {
|
||||
RTLIL::SigSpec sig_y = sigmap(cell->getPort(TW::Y));
|
||||
for (int i = 0; i < GetSize(sig_y); i++)
|
||||
bit2mux[sig_y[i]] = cell_int_t(cell, i);
|
||||
|
|
@ -302,7 +302,7 @@ struct OptDffWorker
|
|||
initvals.remove_init(ff.sig_q[i]);
|
||||
module->connect(ff.sig_q[i], State::S0);
|
||||
log("Handling always-active CLR at position %d on %s (%s) from module %s (changing to const driver).\n",
|
||||
i, cell, cell->type.unescape(), module);
|
||||
i, cell, cell->type.unescaped(), module);
|
||||
sr_removed = true;
|
||||
} else if (is_always_active(ff.sig_set[i], ff.pol_set)) {
|
||||
initvals.remove_init(ff.sig_q[i]);
|
||||
|
|
@ -313,7 +313,7 @@ struct OptDffWorker
|
|||
else
|
||||
module->addNot(NEW_TWINE, ff.sig_clr[i], ff.sig_q[i]);
|
||||
log("Handling always-active SET at position %d on %s (%s) from module %s (changing to combinatorial circuit).\n",
|
||||
i, cell, cell->type.unescape(), module);
|
||||
i, cell, cell->type.unescaped(), module);
|
||||
sr_removed = true;
|
||||
} else {
|
||||
keep_bits.push_back(i);
|
||||
|
|
@ -336,7 +336,7 @@ struct OptDffWorker
|
|||
|
||||
if (clr_inactive && signal_all_same(ff.sig_set)) {
|
||||
log("Removing never-active CLR on %s (%s) from module %s.\n",
|
||||
cell, cell->type.unescape(), module);
|
||||
cell, cell->type.unescaped(), module);
|
||||
ff.has_sr = false;
|
||||
ff.has_arst = true;
|
||||
ff.pol_arst = ff.pol_set;
|
||||
|
|
@ -345,7 +345,7 @@ struct OptDffWorker
|
|||
changed = true;
|
||||
} else if (set_inactive && signal_all_same(ff.sig_clr)) {
|
||||
log("Removing never-active SET on %s (%s) from module %s.\n",
|
||||
cell, cell->type.unescape(), module);
|
||||
cell, cell->type.unescaped(), module);
|
||||
ff.has_sr = false;
|
||||
ff.has_arst = true;
|
||||
ff.pol_arst = ff.pol_clr;
|
||||
|
|
@ -371,7 +371,7 @@ struct OptDffWorker
|
|||
|
||||
if (!failed) {
|
||||
log("Converting CLR/SET to ARST on %s (%s) from module %s.\n",
|
||||
cell, cell->type.unescape(), module);
|
||||
cell, cell->type.unescaped(), module);
|
||||
ff.has_sr = false;
|
||||
ff.has_arst = true;
|
||||
ff.val_arst = val_arst_builder.build();
|
||||
|
|
@ -390,7 +390,7 @@ struct OptDffWorker
|
|||
// Converts constant Async Load to ARST
|
||||
if (is_always_inactive(ff.sig_aload, ff.pol_aload)) {
|
||||
log("Removing never-active async load on %s (%s) from module %s.\n",
|
||||
cell, cell->type.unescape(), module);
|
||||
cell, cell->type.unescaped(), module);
|
||||
ff.has_aload = false;
|
||||
changed = true;
|
||||
return false;
|
||||
|
|
@ -399,7 +399,7 @@ struct OptDffWorker
|
|||
if (is_active(ff.sig_aload, ff.pol_aload)) {
|
||||
// ALOAD always active
|
||||
log("Handling always-active async load on %s (%s) from module %s (changing to combinatorial circuit).\n",
|
||||
cell, cell->type.unescape(), module);
|
||||
cell, cell->type.unescaped(), module);
|
||||
ff.remove();
|
||||
|
||||
if (ff.has_sr) {
|
||||
|
|
@ -434,7 +434,7 @@ struct OptDffWorker
|
|||
// AD is constant -> ARST
|
||||
if (ff.sig_ad.is_fully_const() && !ff.has_arst && !ff.has_sr) {
|
||||
log("Changing const-value async load to async reset on %s (%s) from module %s.\n",
|
||||
cell, cell->type.unescape(), module);
|
||||
cell, cell->type.unescaped(), module);
|
||||
ff.has_arst = true;
|
||||
ff.has_aload = false;
|
||||
ff.sig_arst = ff.sig_aload;
|
||||
|
|
@ -451,12 +451,12 @@ struct OptDffWorker
|
|||
// Removes ARST if never active or replaces FF if always active
|
||||
if (is_inactive(ff.sig_arst, ff.pol_arst)) {
|
||||
log("Removing never-active ARST on %s (%s) from module %s.\n",
|
||||
cell, cell->type.unescape(), module);
|
||||
cell, cell->type.unescaped(), module);
|
||||
ff.has_arst = false;
|
||||
changed = true;
|
||||
} else if (is_always_active(ff.sig_arst, ff.pol_arst)) {
|
||||
log("Handling always-active ARST on %s (%s) from module %s (changing to const driver).\n",
|
||||
cell, cell->type.unescape(), module);
|
||||
cell, cell->type.unescaped(), module);
|
||||
ff.remove();
|
||||
module->connect(ff.sig_q, ff.val_arst);
|
||||
return true;
|
||||
|
|
@ -470,12 +470,12 @@ struct OptDffWorker
|
|||
// Removes SRST if never active or forces D to reset value if always active
|
||||
if (is_inactive(ff.sig_srst, ff.pol_srst)) {
|
||||
log("Removing never-active SRST on %s (%s) from module %s.\n",
|
||||
cell, cell->type.unescape(), module);
|
||||
cell, cell->type.unescaped(), module);
|
||||
ff.has_srst = false;
|
||||
changed = true;
|
||||
} else if (is_always_active(ff.sig_srst, ff.pol_srst)) {
|
||||
log("Handling always-active SRST on %s (%s) from module %s (changing to const D).\n",
|
||||
cell, cell->type.unescape(), module);
|
||||
cell, cell->type.unescaped(), module);
|
||||
ff.has_srst = false;
|
||||
if (!ff.ce_over_srst)
|
||||
ff.has_ce = false;
|
||||
|
|
@ -490,7 +490,7 @@ struct OptDffWorker
|
|||
if (is_always_inactive(ff.sig_ce, ff.pol_ce)) {
|
||||
if (ff.has_srst && !ff.ce_over_srst) {
|
||||
log("Handling never-active EN on %s (%s) from module %s (connecting SRST instead).\n",
|
||||
cell, cell->type.unescape(), module);
|
||||
cell, cell->type.unescaped(), module);
|
||||
ff.pol_ce = ff.pol_srst;
|
||||
ff.sig_ce = ff.sig_srst;
|
||||
ff.has_srst = false;
|
||||
|
|
@ -498,7 +498,7 @@ struct OptDffWorker
|
|||
changed = true;
|
||||
} else if (!opt.keepdc || ff.val_init.is_fully_def()) {
|
||||
log("Handling never-active EN on %s (%s) from module %s (removing D path).\n",
|
||||
cell, cell->type.unescape(), module);
|
||||
cell, cell->type.unescaped(), module);
|
||||
ff.has_ce = ff.has_clk = ff.has_srst = false;
|
||||
changed = true;
|
||||
} else {
|
||||
|
|
@ -508,7 +508,7 @@ struct OptDffWorker
|
|||
}
|
||||
} else if (is_active(ff.sig_ce, ff.pol_ce)) {
|
||||
log("Removing always-active EN on %s (%s) from module %s.\n",
|
||||
cell, cell->type.unescape(), module);
|
||||
cell, cell->type.unescaped(), module);
|
||||
ff.has_ce = false;
|
||||
changed = true;
|
||||
}
|
||||
|
|
@ -518,7 +518,7 @@ struct OptDffWorker
|
|||
{
|
||||
if (!opt.keepdc || ff.val_init.is_fully_def()) {
|
||||
log("Handling const CLK on %s (%s) from module %s (removing D path).\n",
|
||||
cell, cell->type.unescape(), module);
|
||||
cell, cell->type.unescaped(), module);
|
||||
ff.has_ce = ff.has_clk = ff.has_srst = false;
|
||||
changed = true;
|
||||
} else if (ff.has_ce || ff.has_srst || ff.sig_d != ff.sig_q) {
|
||||
|
|
@ -533,7 +533,7 @@ struct OptDffWorker
|
|||
// Detect feedback loops where D is hardwired to Q
|
||||
if (ff.has_clk && ff.has_srst) {
|
||||
log("Handling D = Q on %s (%s) from module %s (conecting SRST instead).\n",
|
||||
cell, cell->type.unescape(), module);
|
||||
cell, cell->type.unescaped(), module);
|
||||
if (ff.has_ce && ff.ce_over_srst) {
|
||||
SigSpec ce = ff.pol_ce ? ff.sig_ce : create_not(ff.sig_ce, ff.is_fine);
|
||||
SigSpec srst = ff.pol_srst ? ff.sig_srst : create_not(ff.sig_srst, ff.is_fine);
|
||||
|
|
@ -550,7 +550,7 @@ struct OptDffWorker
|
|||
changed = true;
|
||||
} else if (!opt.keepdc || ff.val_init.is_fully_def()) {
|
||||
log("Handling D = Q on %s (%s) from module %s (removing D path).\n",
|
||||
cell, cell->type.unescape(), module);
|
||||
cell, cell->type.unescaped(), module);
|
||||
ff.has_gclk = ff.has_clk = ff.has_ce = false;
|
||||
changed = true;
|
||||
}
|
||||
|
|
@ -623,7 +623,7 @@ struct OptDffWorker
|
|||
dff_cells.push_back(new_cell);
|
||||
|
||||
log("Adding SRST signal on %s (%s) from module %s (D = %s, Q = %s, rval = %s).\n",
|
||||
cell, cell->type.unescape(), module,
|
||||
cell, cell->type.unescaped(), module,
|
||||
log_signal(new_ff.sig_d), log_signal(new_ff.sig_q), log_signal(new_ff.val_srst));
|
||||
}
|
||||
|
||||
|
|
@ -693,7 +693,7 @@ struct OptDffWorker
|
|||
dff_cells.push_back(new_cell);
|
||||
|
||||
log("Adding EN signal on %s (%s) from module %s (D = %s, Q = %s).\n",
|
||||
cell, cell->type.unescape(), module,
|
||||
cell, cell->type.unescaped(), module,
|
||||
log_signal(new_ff.sig_d), log_signal(new_ff.sig_q));
|
||||
}
|
||||
|
||||
|
|
@ -760,7 +760,7 @@ struct OptDffWorker
|
|||
|
||||
if (ff.has_aload && !ff.has_clk && ff.sig_ad == ff.sig_q) {
|
||||
log("Handling AD = Q on %s (%s) from module %s (removing async load path).\n",
|
||||
cell, cell->type.unescape(), module);
|
||||
cell, cell->type.unescaped(), module);
|
||||
ff.has_aload = false;
|
||||
changed = true;
|
||||
}
|
||||
|
|
@ -878,7 +878,7 @@ struct OptDffWorker
|
|||
}
|
||||
|
||||
log("Setting constant %d-bit at position %d on %s (%s) from module %s.\n",
|
||||
val ? 1 : 0, i, cell, cell->type.unescape(), module);
|
||||
val ? 1 : 0, i, cell, cell->type.unescaped(), module);
|
||||
|
||||
// Replace the Q output with the constant value
|
||||
initvals.remove_init(ff.sig_q[i]);
|
||||
|
|
|
|||
|
|
@ -46,9 +46,9 @@ void replace_undriven(RTLIL::Module *module, const NewCellTypes &ct)
|
|||
|
||||
for (auto cell : module->cells())
|
||||
for (auto &conn : cell->connections()) {
|
||||
if (!ct.cell_known(cell->type) || ct.cell_output(cell->type, conn.first))
|
||||
if (!ct.cell_known(cell->type_impl) || ct.cell_output(cell->type_impl, conn.first))
|
||||
driven_signals.add(sigmap(conn.second));
|
||||
if (!ct.cell_known(cell->type) || ct.cell_input(cell->type, conn.first))
|
||||
if (!ct.cell_known(cell->type_impl) || ct.cell_input(cell->type_impl, conn.first))
|
||||
used_signals.add(sigmap(conn.second));
|
||||
}
|
||||
|
||||
|
|
@ -180,20 +180,20 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
|
|||
int group_idx = GRP_DYN;
|
||||
RTLIL::SigBit bit_a = bits_a[i], bit_b = bits_b[i];
|
||||
|
||||
if (cell->type == ID($or)) {
|
||||
if (cell->type == TW($or)) {
|
||||
if (bit_a == RTLIL::State::S1 || bit_b == RTLIL::State::S1)
|
||||
bit_a = bit_b = RTLIL::State::S1;
|
||||
}
|
||||
else if (cell->type == ID($and)) {
|
||||
else if (cell->type == TW($and)) {
|
||||
if (bit_a == RTLIL::State::S0 || bit_b == RTLIL::State::S0)
|
||||
bit_a = bit_b = RTLIL::State::S0;
|
||||
}
|
||||
else if (!keepdc) {
|
||||
if (cell->type == ID($xor)) {
|
||||
if (cell->type == TW($xor)) {
|
||||
if (bit_a == bit_b)
|
||||
bit_a = bit_b = RTLIL::State::S0;
|
||||
}
|
||||
else if (cell->type == ID($xnor)) {
|
||||
else if (cell->type == TW($xnor)) {
|
||||
if (bit_a == bit_b)
|
||||
bit_a = bit_b = RTLIL::State::S1; // For consistency with gate-level which does $xnor -> $_XOR_ + $_NOT_
|
||||
}
|
||||
|
|
@ -257,15 +257,15 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
|
|||
slot++;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($and), ID($or)) && kind == GRP_CONST_A) {
|
||||
if (cell->type.in(TW($and), TW($or)) && kind == GRP_CONST_A) {
|
||||
if (!keepdc) {
|
||||
if (cell->type == ID($and))
|
||||
if (cell->type == TW($and))
|
||||
new_a.replace(dict<SigBit,SigBit>{{State::Sx, State::S0}, {State::Sz, State::S0}}, &new_b);
|
||||
else if (cell->type == ID($or))
|
||||
else if (cell->type == TW($or))
|
||||
new_a.replace(dict<SigBit,SigBit>{{State::Sx, State::S1}, {State::Sz, State::S1}}, &new_b);
|
||||
else log_abort();
|
||||
}
|
||||
log_debug(" Direct Connection: %s (%s with %s)\n", log_signal(new_b), cell->type.unescape(), log_signal(new_a));
|
||||
log_debug(" Direct Connection: %s (%s with %s)\n", log_signal(new_b), cell->type.unescaped(), log_signal(new_a));
|
||||
// new_y becomes new_b directly: rewrite any bit_map entries pointing at new_y bits.
|
||||
dict<SigBit, SigBit> remap;
|
||||
for (int j = 0; j < group_size; j++)
|
||||
|
|
@ -277,26 +277,26 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
|
|||
continue;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($xor), ID($xnor)) && kind == GRP_CONST_A) {
|
||||
if (cell->type.in(TW($xor), TW($xnor)) && kind == GRP_CONST_A) {
|
||||
SigSpec undef_a, undef_y, undef_b;
|
||||
SigSpec def_y, def_a, def_b;
|
||||
for (int j = 0; j < GetSize(new_y); j++) {
|
||||
bool undef = new_a[j] == State::Sx || new_a[j] == State::Sz;
|
||||
if (!keepdc && (undef || new_a[j] == new_b[j])) {
|
||||
undef_a.append(new_a[j]);
|
||||
if (cell->type == ID($xor))
|
||||
if (cell->type == TW($xor))
|
||||
undef_b.append(State::S0);
|
||||
// For consistency since simplemap does $xnor -> $_XOR_ + $_NOT_
|
||||
else if (cell->type == ID($xnor))
|
||||
else if (cell->type == TW($xnor))
|
||||
undef_b.append(State::S1);
|
||||
else log_abort();
|
||||
undef_y.append(new_y[j]);
|
||||
}
|
||||
else if (new_a[j] == State::S0 || new_a[j] == State::S1) {
|
||||
undef_a.append(new_a[j]);
|
||||
if (cell->type == ID($xor))
|
||||
if (cell->type == TW($xor))
|
||||
undef_b.append(new_a[j] == State::S1 ? patcher.Not(NEW_TWINE, new_b[j]).as_bit() : new_b[j]);
|
||||
else if (cell->type == ID($xnor))
|
||||
else if (cell->type == TW($xnor))
|
||||
undef_b.append(new_a[j] == State::S1 ? new_b[j] : patcher.Not(NEW_TWINE, new_b[j]).as_bit());
|
||||
else log_abort();
|
||||
undef_y.append(new_y[j]);
|
||||
|
|
@ -308,7 +308,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
|
|||
}
|
||||
}
|
||||
if (!undef_y.empty()) {
|
||||
log_debug(" Direct Connection: %s (%s with %s)\n", log_signal(undef_b), cell->type.unescape(), log_signal(undef_a));
|
||||
log_debug(" Direct Connection: %s (%s with %s)\n", log_signal(undef_b), cell->type.unescaped(), log_signal(undef_a));
|
||||
dict<SigBit, SigBit> remap;
|
||||
for (int j = 0; j < GetSize(undef_y); j++)
|
||||
remap[undef_y[j]] = undef_b[j];
|
||||
|
|
@ -324,7 +324,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
|
|||
new_y = std::move(def_y);
|
||||
}
|
||||
|
||||
RTLIL::Cell *c = patcher.addCell(NEW_TWINE, cell->type);
|
||||
RTLIL::Cell *c = patcher.addCell(NEW_TWINE, cell->type_impl);
|
||||
|
||||
c->setPort(TW::A, new_a);
|
||||
c->parameters[ID::A_WIDTH] = new_a.size();
|
||||
|
|
@ -362,7 +362,7 @@ std::optional<SigBit> get_inverted_raw(SigBit s)
|
|||
if (!s.is_wire() || !s.wire->known_driver())
|
||||
return std::nullopt;
|
||||
Cell* cell = s.wire->driverCell();
|
||||
if (!cell->type.in(ID($_NOT_), ID($not), ID($logic_not)))
|
||||
if (!cell->type.in(TW($_NOT_), TW($not), TW($logic_not)))
|
||||
return std::nullopt;
|
||||
if (GetSize(cell->getPort(TW::A)) != 1 || GetSize(cell->getPort(TW::Y)) != 1)
|
||||
return std::nullopt;
|
||||
|
|
@ -385,8 +385,9 @@ void handle_polarity_inv(Cell *cell, TwineRef port, IdString param, const SigMap
|
|||
SigBit sig = assign_map(raw);
|
||||
if (auto inv_a = get_inverted_raw(sig)) {
|
||||
SigBit new_sig = assign_map(*inv_a);
|
||||
auto twines = cell->module->design->twines;
|
||||
log_debug("Inverting %s of %s cell `%s' in module `%s': %s -> %s\n",
|
||||
IdString(RTLIL::StaticId(port)).unescape(), cell->type.unescape(), cell, cell->module,
|
||||
twines.unescaped_str(port), cell->type.unescaped(), cell, cell->module,
|
||||
log_signal(sig), log_signal(new_sig));
|
||||
cell->setPort(port, new_sig);
|
||||
cell->setParam(param, !cell->getParam(param).as_bool());
|
||||
|
|
@ -413,10 +414,11 @@ void handle_clkpol_celltype_swap(Cell *cell, string type1, string type2, TwineRe
|
|||
|
||||
if (cell->type.in(type1, type2)) {
|
||||
SigSpec sig = assign_map(cell->getPort(port));
|
||||
auto twines = cell->module->design->twines;
|
||||
if (auto inv_a = get_inverted_raw(sig)) {
|
||||
SigSpec new_sig = assign_map(*inv_a);
|
||||
log_debug("Inverting %s of %s cell `%s' in module `%s': %s -> %s\n",
|
||||
IdString(RTLIL::StaticId(port)).unescape(), cell->type.unescape(), cell, cell->module,
|
||||
twines.unescaped_str(port), cell->type.unescaped(), cell, cell->module,
|
||||
log_signal(sig), log_signal(new_sig));
|
||||
cell->setPort(port, new_sig);
|
||||
cell->type_impl = cell->module->design->twines.add(Twine{cell->type == type1 ? type2 : type1});
|
||||
|
|
@ -480,27 +482,27 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
if (!noclkinv)
|
||||
for (auto cell : dirty_cells)
|
||||
if (design->selected(module, cell)) {
|
||||
if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($sdff), ID($sdffe), ID($sdffce), ID($fsm), ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2)))
|
||||
if (cell->type.in(TW($dff), TW($dffe), TW($dffsr), TW($dffsre), TW($adff), TW($adffe), TW($aldff), TW($aldffe), TW($sdff), TW($sdffe), TW($sdffce), TW($fsm), TW($memrd), TW($memrd_v2), TW($memwr), TW($memwr_v2)))
|
||||
handle_polarity_inv(cell, TW::CLK, ID::CLK_POLARITY, assign_map);
|
||||
|
||||
if (cell->type.in(ID($sr), ID($dffsr), ID($dffsre), ID($dlatchsr))) {
|
||||
if (cell->type.in(TW($sr), TW($dffsr), TW($dffsre), TW($dlatchsr))) {
|
||||
handle_polarity_inv(cell, TW::SET, ID::SET_POLARITY, assign_map);
|
||||
handle_polarity_inv(cell, TW::CLR, ID::CLR_POLARITY, assign_map);
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($adff), ID($adffe), ID($adlatch)))
|
||||
if (cell->type.in(TW($adff), TW($adffe), TW($adlatch)))
|
||||
handle_polarity_inv(cell, TW::ARST, ID::ARST_POLARITY, assign_map);
|
||||
|
||||
if (cell->type.in(ID($aldff), ID($aldffe)))
|
||||
if (cell->type.in(TW($aldff), TW($aldffe)))
|
||||
handle_polarity_inv(cell, TW::ALOAD, ID::ALOAD_POLARITY, assign_map);
|
||||
|
||||
if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce)))
|
||||
if (cell->type.in(TW($sdff), TW($sdffe), TW($sdffce)))
|
||||
handle_polarity_inv(cell, TW::SRST, ID::SRST_POLARITY, assign_map);
|
||||
|
||||
if (cell->type.in(ID($dffe), ID($adffe), ID($aldffe), ID($sdffe), ID($sdffce), ID($dffsre), ID($dlatch), ID($adlatch), ID($dlatchsr)))
|
||||
if (cell->type.in(TW($dffe), TW($adffe), TW($aldffe), TW($sdffe), TW($sdffce), TW($dffsre), TW($dlatch), TW($adlatch), TW($dlatchsr)))
|
||||
handle_polarity_inv(cell, TW::EN, ID::EN_POLARITY, assign_map);
|
||||
|
||||
if (!StaticCellTypes::Compat::stdcells_mem(cell->type))
|
||||
if (!StaticCellTypes::Compat::stdcells_mem(cell->type_impl))
|
||||
continue;
|
||||
|
||||
handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", TW::S, assign_map);
|
||||
|
|
@ -560,19 +562,19 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
dict<RTLIL::SigBit, Cell*> outbit_to_cell;
|
||||
|
||||
for (auto cell : dirty_cells)
|
||||
if (design->selected(module, cell) && yosys_celltypes.cell_evaluable(cell->type)) {
|
||||
if (design->selected(module, cell) && yosys_celltypes.cell_evaluable(cell->type_impl)) {
|
||||
for (auto &conn : cell->connections())
|
||||
if (yosys_celltypes.cell_output(cell->type, conn.first))
|
||||
if (yosys_celltypes.cell_output(cell->type_impl, conn.first))
|
||||
for (auto bit : assign_map(conn.second))
|
||||
outbit_to_cell[bit] = cell;
|
||||
cells.node(cell);
|
||||
}
|
||||
|
||||
for (auto cell : dirty_cells)
|
||||
if (design->selected(module, cell) && yosys_celltypes.cell_evaluable(cell->type)) {
|
||||
if (design->selected(module, cell) && yosys_celltypes.cell_evaluable(cell->type_impl)) {
|
||||
const int r_index = cells.node(cell);
|
||||
for (auto &conn : cell->connections())
|
||||
if (yosys_celltypes.cell_input(cell->type, conn.first))
|
||||
if (yosys_celltypes.cell_input(cell->type_impl, conn.first))
|
||||
for (auto bit : assign_map(conn.second))
|
||||
if (outbit_to_cell.count(bit))
|
||||
cells.edge(cells.node(outbit_to_cell.at(bit)), r_index);
|
||||
|
|
@ -594,16 +596,16 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
bool detect_const_and = false;
|
||||
bool detect_const_or = false;
|
||||
|
||||
if (cell->type.in(ID($reduce_and), ID($_AND_)))
|
||||
if (cell->type.in(TW($reduce_and), TW($_AND_)))
|
||||
detect_const_and = true;
|
||||
|
||||
if (cell->type.in(ID($and), ID($logic_and)) && GetSize(cell->getPort(TW::A)) == 1 && GetSize(cell->getPort(TW::B)) == 1 && !cell->getParam(ID::A_SIGNED).as_bool())
|
||||
if (cell->type.in(TW($and), TW($logic_and)) && GetSize(cell->getPort(TW::A)) == 1 && GetSize(cell->getPort(TW::B)) == 1 && !cell->getParam(ID::A_SIGNED).as_bool())
|
||||
detect_const_and = true;
|
||||
|
||||
if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($_OR_)))
|
||||
if (cell->type.in(TW($reduce_or), TW($reduce_bool), TW($_OR_)))
|
||||
detect_const_or = true;
|
||||
|
||||
if (cell->type.in(ID($or), ID($logic_or)) && GetSize(cell->getPort(TW::A)) == 1 && GetSize(cell->getPort(TW::B)) == 1 && !cell->getParam(ID::A_SIGNED).as_bool())
|
||||
if (cell->type.in(TW($or), TW($logic_or)) && GetSize(cell->getPort(TW::A)) == 1 && GetSize(cell->getPort(TW::B)) == 1 && !cell->getParam(ID::A_SIGNED).as_bool())
|
||||
detect_const_or = true;
|
||||
|
||||
if (detect_const_and || detect_const_or)
|
||||
|
|
@ -656,17 +658,17 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
}
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($_XOR_), ID($_XNOR_)) || (cell->type.in(ID($xor), ID($xnor)) && GetSize(cell->getPort(TW::A)) == 1 && GetSize(cell->getPort(TW::B)) == 1 && !cell->getParam(ID::A_SIGNED).as_bool()))
|
||||
if (cell->type.in(TW($_XOR_), TW($_XNOR_)) || (cell->type.in(TW($xor), TW($xnor)) && GetSize(cell->getPort(TW::A)) == 1 && GetSize(cell->getPort(TW::B)) == 1 && !cell->getParam(ID::A_SIGNED).as_bool()))
|
||||
{
|
||||
SigBit sig_a = assign_map(cell->getPort(TW::A));
|
||||
SigBit sig_b = assign_map(cell->getPort(TW::B));
|
||||
if (!keepdc && (sig_a == sig_b || sig_a == State::Sx || sig_a == State::Sz || sig_b == State::Sx || sig_b == State::Sz)) {
|
||||
OptExprPatcher patcher(module, &assign_map);
|
||||
if (cell->type.in(ID($xor), ID($_XOR_))) {
|
||||
if (cell->type.in(TW($xor), TW($_XOR_))) {
|
||||
patcher.patch(cell, TW::Y, RTLIL::State::S0, "const_xor");
|
||||
goto next_cell;
|
||||
}
|
||||
if (cell->type.in(ID($xnor), ID($_XNOR_))) {
|
||||
if (cell->type.in(TW($xnor), TW($_XNOR_))) {
|
||||
// For consistency since simplemap does $xnor -> $_XOR_ + $_NOT_
|
||||
int width = GetSize(cell->getPort(TW::Y));
|
||||
patcher.patch(cell, TW::Y, SigSpec(RTLIL::State::S1, width), "const_xnor");
|
||||
|
|
@ -679,9 +681,9 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
std::swap(sig_a, sig_b);
|
||||
if (sig_b == State::S0 || sig_b == State::S1) {
|
||||
OptExprPatcher patcher(module, &assign_map);
|
||||
bool is_gate = cell->type.in(ID($_XOR_), ID($_XNOR_));
|
||||
bool is_gate = cell->type.in(TW($_XOR_), TW($_XNOR_));
|
||||
int width = is_gate ? 1 : cell->getParam(ID::Y_WIDTH).as_int();
|
||||
if (cell->type.in(ID($xor), ID($_XOR_))) {
|
||||
if (cell->type.in(TW($xor), TW($_XOR_))) {
|
||||
if (sig_b == State::S0) {
|
||||
SigSpec sig_y = sig_a;
|
||||
sig_y.append(RTLIL::Const(State::S0, width-1));
|
||||
|
|
@ -693,7 +695,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
}
|
||||
goto next_cell;
|
||||
}
|
||||
if (cell->type.in(ID($xnor), ID($_XNOR_))) {
|
||||
if (cell->type.in(TW($xnor), TW($_XNOR_))) {
|
||||
if (sig_b == State::S1) {
|
||||
SigSpec sig_y = sig_a;
|
||||
sig_y.append(RTLIL::Const(State::S1, width-1));
|
||||
|
|
@ -709,10 +711,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
}
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($reduce_xor), ID($reduce_xnor), ID($neg)) &&
|
||||
if (cell->type.in(TW($reduce_and), TW($reduce_or), TW($reduce_bool), TW($reduce_xor), TW($reduce_xnor), TW($neg)) &&
|
||||
GetSize(cell->getPort(TW::A)) == 1 && GetSize(cell->getPort(TW::Y)) == 1)
|
||||
{
|
||||
if (cell->type == ID($reduce_xnor)) {
|
||||
if (cell->type == TW($reduce_xnor)) {
|
||||
log_debug("Replacing %s cell `%s' in module `%s' with $not cell.\n",
|
||||
cell->type.unescape(), cell->module->design->twines.str(cell->meta_->name), module);
|
||||
cell->type_impl = TW::$not;
|
||||
|
|
@ -724,7 +726,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
goto next_cell;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor)))
|
||||
if (cell->type.in(TW($and), TW($or), TW($xor), TW($xnor)))
|
||||
{
|
||||
RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
|
||||
RTLIL::SigSpec sig_b = assign_map(cell->getPort(TW::B));
|
||||
|
|
@ -750,8 +752,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
// Per-i (group, position_in_group); group = -1 means leave as Sx
|
||||
std::vector<std::pair<int, int>> origin(width, {-1, 0});
|
||||
|
||||
auto group_0 = cell->type == ID($xnor) ? 1 : 0;
|
||||
auto group_1 = cell->type == ID($xnor) ? 0 : 1;
|
||||
auto group_0 = cell->type == TW($xnor) ? 1 : 0;
|
||||
auto group_1 = cell->type == TW($xnor) ? 0 : 1;
|
||||
|
||||
for (int i = 0; i < width; i++) {
|
||||
auto bit_a = sig_a[i].data;
|
||||
|
|
@ -760,13 +762,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
else if (bit_a == State::Sx) origin[i] = {2, b_group_x.size()}, b_group_x.append(sig_b[i]);
|
||||
}
|
||||
|
||||
if (cell->type == ID($xnor))
|
||||
if (cell->type == TW($xnor))
|
||||
std::swap(b_group_0, b_group_1);
|
||||
|
||||
OptExprPatcher patcher(module, &assign_map);
|
||||
RTLIL::SigSpec y_new_0, y_new_1, y_new_x;
|
||||
|
||||
if (cell->type == ID($and)) {
|
||||
if (cell->type == TW($and)) {
|
||||
if (!b_group_0.empty()) y_new_0 = Const(State::S0, GetSize(b_group_0));
|
||||
if (!b_group_1.empty()) y_new_1 = b_group_1;
|
||||
if (!b_group_x.empty()) {
|
||||
|
|
@ -775,7 +777,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
else
|
||||
y_new_x = Const(State::S0, GetSize(b_group_x));
|
||||
}
|
||||
} else if (cell->type == ID($or)) {
|
||||
} else if (cell->type == TW($or)) {
|
||||
if (!b_group_0.empty()) y_new_0 = b_group_0;
|
||||
if (!b_group_1.empty()) y_new_1 = Const(State::S1, GetSize(b_group_1));
|
||||
if (!b_group_x.empty()) {
|
||||
|
|
@ -784,7 +786,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
else
|
||||
y_new_x = Const(State::S1, GetSize(b_group_x));
|
||||
}
|
||||
} else if (cell->type.in(ID($xor), ID($xnor))) {
|
||||
} else if (cell->type.in(TW($xor), TW($xnor))) {
|
||||
if (!b_group_0.empty()) y_new_0 = b_group_0;
|
||||
if (!b_group_1.empty()) y_new_1 = patcher.Not(NEW_TWINE, b_group_1);
|
||||
if (!b_group_x.empty()) {
|
||||
|
|
@ -809,7 +811,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
}
|
||||
}
|
||||
|
||||
if (cell->type == ID($bwmux))
|
||||
if (cell->type == TW($bwmux))
|
||||
{
|
||||
RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
|
||||
RTLIL::SigSpec sig_b = assign_map(cell->getPort(TW::B));
|
||||
|
|
@ -866,13 +868,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
|
||||
if (do_fine)
|
||||
{
|
||||
if (cell->type.in(ID($not), ID($pos), ID($and), ID($or), ID($xor), ID($xnor)))
|
||||
if (cell->type.in(TW($not), TW($pos), TW($and), TW($or), TW($xor), TW($xnor)))
|
||||
if (group_cell_inputs(module, cell, true, assign_map, keepdc))
|
||||
goto next_cell;
|
||||
|
||||
if (cell->type.in(ID($logic_not), ID($logic_and), ID($logic_or), ID($reduce_or), ID($reduce_and), ID($reduce_bool)))
|
||||
if (cell->type.in(TW($logic_not), TW($logic_and), TW($logic_or), TW($reduce_or), TW($reduce_and), TW($reduce_bool)))
|
||||
{
|
||||
SigBit neutral_bit = cell->type == ID($reduce_and) ? State::S1 : State::S0;
|
||||
SigBit neutral_bit = cell->type == TW($reduce_and) ? State::S1 : State::S0;
|
||||
|
||||
RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
|
||||
RTLIL::SigSpec new_sig_a;
|
||||
|
|
@ -892,7 +894,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
}
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($logic_and), ID($logic_or)))
|
||||
if (cell->type.in(TW($logic_and), TW($logic_or)))
|
||||
{
|
||||
SigBit neutral_bit = State::S0;
|
||||
|
||||
|
|
@ -914,7 +916,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
}
|
||||
}
|
||||
|
||||
if (cell->type == ID($reduce_and))
|
||||
if (cell->type == TW($reduce_and))
|
||||
{
|
||||
RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
|
||||
|
||||
|
|
@ -939,7 +941,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
}
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($logic_not), ID($logic_and), ID($logic_or), ID($reduce_or), ID($reduce_bool)))
|
||||
if (cell->type.in(TW($logic_not), TW($logic_and), TW($logic_or), TW($reduce_or), TW($reduce_bool)))
|
||||
{
|
||||
RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
|
||||
|
||||
|
|
@ -964,7 +966,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
}
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($logic_and), ID($logic_or)))
|
||||
if (cell->type.in(TW($logic_and), TW($logic_or)))
|
||||
{
|
||||
RTLIL::SigSpec sig_b = assign_map(cell->getPort(TW::B));
|
||||
|
||||
|
|
@ -989,13 +991,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
}
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($add), ID($sub)))
|
||||
if (cell->type.in(TW($add), TW($sub)))
|
||||
{
|
||||
RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
|
||||
RTLIL::SigSpec sig_b = assign_map(cell->getPort(TW::B));
|
||||
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
|
||||
bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
|
||||
bool sub = cell->type == ID($sub);
|
||||
bool sub = cell->type == TW($sub);
|
||||
|
||||
int minsz = GetSize(sig_y);
|
||||
minsz = std::min(minsz, GetSize(sig_a));
|
||||
|
|
@ -1015,7 +1017,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
break;
|
||||
}
|
||||
if (i > 0) {
|
||||
log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, cell->type.unescape(), cell, module);
|
||||
log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, cell->type.unescaped(), cell, module);
|
||||
SigSpec new_a = sig_a.extract_end(i);
|
||||
SigSpec new_b = sig_b.extract_end(i);
|
||||
if (new_a.empty() && is_signed)
|
||||
|
|
@ -1030,7 +1032,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
}
|
||||
}
|
||||
|
||||
if (cell->type == ID($alu))
|
||||
if (cell->type == TW($alu))
|
||||
{
|
||||
RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
|
||||
RTLIL::SigSpec sig_b = assign_map(cell->getPort(TW::B));
|
||||
|
|
@ -1071,7 +1073,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
break;
|
||||
}
|
||||
if (i > 0) {
|
||||
log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, cell->type.unescape(), cell, module);
|
||||
log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, cell->type.unescaped(), cell, module);
|
||||
SigSpec new_a = sig_a.extract_end(i);
|
||||
SigSpec new_b = sig_b.extract_end(i);
|
||||
if (new_a.empty() && is_signed)
|
||||
|
|
@ -1090,13 +1092,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
}
|
||||
skip_fine_alu:
|
||||
|
||||
if (cell->type.in(ID($reduce_xor), ID($reduce_xnor), ID($shift), ID($shiftx), ID($shl), ID($shr), ID($sshl), ID($sshr),
|
||||
ID($lt), ID($le), ID($ge), ID($gt), ID($neg), ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow)))
|
||||
if (cell->type.in(TW($reduce_xor), TW($reduce_xnor), TW($shift), TW($shiftx), TW($shl), TW($shr), TW($sshl), TW($sshr),
|
||||
TW($lt), TW($le), TW($ge), TW($gt), TW($neg), TW($add), TW($sub), TW($mul), TW($div), TW($mod), TW($divfloor), TW($modfloor), TW($pow)))
|
||||
{
|
||||
RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
|
||||
RTLIL::SigSpec sig_b = cell->hasPort(TW::B) ? assign_map(cell->getPort(TW::B)) : RTLIL::SigSpec();
|
||||
|
||||
if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)))
|
||||
if (cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx)))
|
||||
sig_a = RTLIL::SigSpec();
|
||||
|
||||
for (auto &bit : sig_a.to_sigbit_vector())
|
||||
|
|
@ -1110,7 +1112,7 @@ skip_fine_alu:
|
|||
if (0) {
|
||||
found_the_x_bit:
|
||||
OptExprPatcher patcher(module, &assign_map);
|
||||
if (cell->type.in(ID($reduce_xor), ID($reduce_xnor), ID($lt), ID($le), ID($ge), ID($gt)))
|
||||
if (cell->type.in(TW($reduce_xor), TW($reduce_xnor), TW($lt), TW($le), TW($ge), TW($gt)))
|
||||
patcher.patch(cell, TW::Y, RTLIL::State::Sx, "x-bit in input");
|
||||
else
|
||||
patcher.patch(cell, TW::Y, RTLIL::SigSpec(RTLIL::State::Sx, GetSize(cell->getPort(TW::Y))), "x-bit in input");
|
||||
|
|
@ -1118,11 +1120,11 @@ skip_fine_alu:
|
|||
}
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($shiftx), ID($shift)) && (cell->type == ID($shiftx) || !cell->getParam(ID::A_SIGNED).as_bool())) {
|
||||
if (cell->type.in(TW($shiftx), TW($shift)) && (cell->type == TW($shiftx) || !cell->getParam(ID::A_SIGNED).as_bool())) {
|
||||
SigSpec sig_a = assign_map(cell->getPort(TW::A));
|
||||
int width;
|
||||
bool trim_x = cell->type == ID($shiftx) || !keepdc;
|
||||
bool trim_0 = cell->type == ID($shift);
|
||||
bool trim_x = cell->type == TW($shiftx) || !keepdc;
|
||||
bool trim_0 = cell->type == TW($shift);
|
||||
for (width = GetSize(sig_a); width > 1; width--) {
|
||||
if ((trim_x && sig_a[width-1] == State::Sx) ||
|
||||
(trim_0 && sig_a[width-1] == State::S0))
|
||||
|
|
@ -1139,7 +1141,7 @@ skip_fine_alu:
|
|||
}
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) && GetSize(cell->getPort(TW::Y)) == 1 && GetSize(cell->getPort(TW::A)) == 1) {
|
||||
if (cell->type.in(TW($_NOT_), TW($not), TW($logic_not)) && GetSize(cell->getPort(TW::Y)) == 1 && GetSize(cell->getPort(TW::A)) == 1) {
|
||||
if (auto inv_a = get_inverted(cell->getPort(TW::A), assign_map)) {
|
||||
OptExprPatcher patcher(module, &assign_map);
|
||||
patcher.patch(cell, TW::Y, *inv_a, "double_invert");
|
||||
|
|
@ -1147,9 +1149,9 @@ skip_fine_alu:
|
|||
}
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($_MUX_), ID($mux))) {
|
||||
if (cell->type.in(TW($_MUX_), TW($mux))) {
|
||||
if (auto inv_a = get_inverted(cell->getPort(TW::S), assign_map)) {
|
||||
log_debug("Optimizing away select inverter for %s cell `%s' in module `%s'.\n", cell->type.unescape(), cell, module);
|
||||
log_debug("Optimizing away select inverter for %s cell `%s' in module `%s'.\n", cell->type.unescaped(), cell, module);
|
||||
RTLIL::SigSpec tmp = cell->getPort(TW::A);
|
||||
cell->setPort(TW::A, cell->getPort(TW::B));
|
||||
cell->setPort(TW::B, tmp);
|
||||
|
|
@ -1159,7 +1161,7 @@ skip_fine_alu:
|
|||
}
|
||||
}
|
||||
|
||||
if (cell->type == ID($_NOT_)) {
|
||||
if (cell->type == TW($_NOT_)) {
|
||||
RTLIL::SigSpec input = cell->getPort(TW::A);
|
||||
assign_map.apply(input);
|
||||
if (input.match("1")) ACTION_DO_Y(0);
|
||||
|
|
@ -1167,7 +1169,7 @@ skip_fine_alu:
|
|||
if (input.match("*")) ACTION_DO_Y(x);
|
||||
}
|
||||
|
||||
if (cell->type == ID($_AND_)) {
|
||||
if (cell->type == TW($_AND_)) {
|
||||
RTLIL::SigSpec input;
|
||||
input.append(cell->getPort(TW::B));
|
||||
input.append(cell->getPort(TW::A));
|
||||
|
|
@ -1186,7 +1188,7 @@ skip_fine_alu:
|
|||
if (input.match("1 ")) ACTION_DO(TW::Y, input.extract(0, 1));
|
||||
}
|
||||
|
||||
if (cell->type == ID($_OR_)) {
|
||||
if (cell->type == TW($_OR_)) {
|
||||
RTLIL::SigSpec input;
|
||||
input.append(cell->getPort(TW::B));
|
||||
input.append(cell->getPort(TW::A));
|
||||
|
|
@ -1205,7 +1207,7 @@ skip_fine_alu:
|
|||
if (input.match("0 ")) ACTION_DO(TW::Y, input.extract(0, 1));
|
||||
}
|
||||
|
||||
if (cell->type == ID($_XOR_)) {
|
||||
if (cell->type == TW($_XOR_)) {
|
||||
RTLIL::SigSpec input;
|
||||
input.append(cell->getPort(TW::B));
|
||||
input.append(cell->getPort(TW::A));
|
||||
|
|
@ -1220,7 +1222,7 @@ skip_fine_alu:
|
|||
}
|
||||
}
|
||||
|
||||
if (cell->type == ID($_MUX_)) {
|
||||
if (cell->type == TW($_MUX_)) {
|
||||
RTLIL::SigSpec input;
|
||||
input.append(cell->getPort(TW::S));
|
||||
input.append(cell->getPort(TW::B));
|
||||
|
|
@ -1250,8 +1252,8 @@ skip_fine_alu:
|
|||
}
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($_TBUF_), ID($tribuf))) {
|
||||
RTLIL::SigSpec input = cell->getPort(cell->type == ID($_TBUF_) ? TW::E : TW::EN);
|
||||
if (cell->type.in(TW($_TBUF_), TW($tribuf))) {
|
||||
RTLIL::SigSpec input = cell->getPort(cell->type == TW($_TBUF_) ? TW::E : TW::EN);
|
||||
RTLIL::SigSpec a = cell->getPort(TW::A);
|
||||
assign_map.apply(input);
|
||||
assign_map.apply(a);
|
||||
|
|
@ -1266,7 +1268,7 @@ skip_fine_alu:
|
|||
}
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex)))
|
||||
if (cell->type.in(TW($eq), TW($ne), TW($eqx), TW($nex)))
|
||||
{
|
||||
RTLIL::SigSpec a = cell->getPort(TW::A);
|
||||
RTLIL::SigSpec b = cell->getPort(TW::B);
|
||||
|
|
@ -1282,7 +1284,7 @@ skip_fine_alu:
|
|||
log_assert(GetSize(a) == GetSize(b));
|
||||
for (int i = 0; i < GetSize(a); i++) {
|
||||
if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) {
|
||||
RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in(ID($eq), ID($eqx)) ? RTLIL::State::S0 : RTLIL::State::S1);
|
||||
RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in(TW($eq), TW($eqx)) ? RTLIL::State::S0 : RTLIL::State::S1);
|
||||
new_y.extend_u0(cell->parameters[ID::Y_WIDTH].as_int(), false);
|
||||
OptExprPatcher patcher(module, &assign_map);
|
||||
patcher.patch(cell, TW::Y, new_y, "isneq");
|
||||
|
|
@ -1300,7 +1302,7 @@ skip_fine_alu:
|
|||
}
|
||||
|
||||
if (new_a.size() == 0) {
|
||||
RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in(ID($eq), ID($eqx)) ? RTLIL::State::S1 : RTLIL::State::S0);
|
||||
RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in(TW($eq), TW($eqx)) ? RTLIL::State::S1 : RTLIL::State::S0);
|
||||
new_y.extend_u0(cell->parameters[ID::Y_WIDTH].as_int(), false);
|
||||
OptExprPatcher patcher(module, &assign_map);
|
||||
patcher.patch(cell, TW::Y, new_y, "empty");
|
||||
|
|
@ -1315,7 +1317,7 @@ skip_fine_alu:
|
|||
}
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($eq), ID($ne)) && cell->parameters[ID::Y_WIDTH].as_int() == 1 &&
|
||||
if (cell->type.in(TW($eq), TW($ne)) && cell->parameters[ID::Y_WIDTH].as_int() == 1 &&
|
||||
cell->parameters[ID::A_WIDTH].as_int() == 1 && cell->parameters[ID::B_WIDTH].as_int() == 1)
|
||||
{
|
||||
RTLIL::SigSpec a = assign_map(cell->getPort(TW::A));
|
||||
|
|
@ -1332,11 +1334,11 @@ skip_fine_alu:
|
|||
RTLIL::SigSpec input = b;
|
||||
ACTION_DO(TW::Y, Const(State::Sx, GetSize(cell->getPort(TW::Y))));
|
||||
} else
|
||||
if (b.as_bool() == (cell->type == ID($eq))) {
|
||||
if (b.as_bool() == (cell->type == TW($eq))) {
|
||||
RTLIL::SigSpec input = b;
|
||||
ACTION_DO(TW::Y, cell->getPort(TW::A));
|
||||
} else {
|
||||
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", cell->type.unescape(), cell, module);
|
||||
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", cell->type.unescaped(), cell, module);
|
||||
cell->parameters.erase(ID::B_WIDTH);
|
||||
cell->parameters.erase(ID::B_SIGNED);
|
||||
cell->unsetPort(TW::B);
|
||||
|
|
@ -1347,11 +1349,11 @@ skip_fine_alu:
|
|||
}
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($eq), ID($ne)) &&
|
||||
if (cell->type.in(TW($eq), TW($ne)) &&
|
||||
(assign_map(cell->getPort(TW::A)).is_fully_zero() || assign_map(cell->getPort(TW::B)).is_fully_zero()))
|
||||
{
|
||||
log_debug("Replacing %s cell `%s' in module `%s' with %s.\n", cell->type.unescape(), cell,
|
||||
module, cell->type == ID($eq) ? "$logic_not" : "$reduce_bool");
|
||||
log_debug("Replacing %s cell `%s' in module `%s' with %s.\n", cell->type.unescaped(), cell,
|
||||
module, cell->type == TW($eq) ? "$logic_not" : "$reduce_bool");
|
||||
if (assign_map(cell->getPort(TW::A)).is_fully_zero()) {
|
||||
cell->setPort(TW::A, cell->getPort(TW::B));
|
||||
cell->setParam(ID::A_SIGNED, cell->getParam(ID::B_SIGNED));
|
||||
|
|
@ -1360,28 +1362,28 @@ skip_fine_alu:
|
|||
cell->unsetPort(TW::B);
|
||||
cell->unsetParam(ID::B_SIGNED);
|
||||
cell->unsetParam(ID::B_WIDTH);
|
||||
cell->type_impl = (cell->type == ID($eq)) ? TW::$logic_not : TW::$reduce_bool;
|
||||
cell->type_impl = (cell->type == TW($eq)) ? TW::$logic_not : TW::$reduce_bool;
|
||||
did_something = true;
|
||||
goto next_cell;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)) && (keepdc ? assign_map(cell->getPort(TW::B)).is_fully_def() : assign_map(cell->getPort(TW::B)).is_fully_const()))
|
||||
if (cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx)) && (keepdc ? assign_map(cell->getPort(TW::B)).is_fully_def() : assign_map(cell->getPort(TW::B)).is_fully_const()))
|
||||
{
|
||||
bool sign_ext = cell->type == ID($sshr) && cell->getParam(ID::A_SIGNED).as_bool();
|
||||
bool sign_ext = cell->type == TW($sshr) && cell->getParam(ID::A_SIGNED).as_bool();
|
||||
RTLIL::SigSpec sig_b = assign_map(cell->getPort(TW::B));
|
||||
const bool b_sign_ext = cell->type.in(ID($shift), ID($shiftx)) && cell->getParam(ID::B_SIGNED).as_bool();
|
||||
const bool b_sign_ext = cell->type.in(TW($shift), TW($shiftx)) && cell->getParam(ID::B_SIGNED).as_bool();
|
||||
// We saturate the value to prevent overflow, but note that this could
|
||||
// cause incorrect opimization in the impractical case that A is 2^32 bits
|
||||
// wide
|
||||
int shift_bits = sig_b.as_int_saturating(b_sign_ext);
|
||||
|
||||
if (cell->type.in(ID($shl), ID($sshl)))
|
||||
if (cell->type.in(TW($shl), TW($sshl)))
|
||||
shift_bits *= -1;
|
||||
|
||||
RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
|
||||
RTLIL::SigSpec sig_y(cell->type == ID($shiftx) ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam(ID::Y_WIDTH).as_int());
|
||||
RTLIL::SigSpec sig_y(cell->type == TW($shiftx) ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam(ID::Y_WIDTH).as_int());
|
||||
|
||||
if (cell->type != ID($shiftx) && GetSize(sig_a) < GetSize(sig_y))
|
||||
if (cell->type != TW($shiftx) && GetSize(sig_a) < GetSize(sig_y))
|
||||
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
|
||||
|
||||
// Limit indexing to the size of a, which is behaviourally identical (result is all 0)
|
||||
|
|
@ -1411,14 +1413,14 @@ skip_fine_alu:
|
|||
bool identity_wrt_b = false;
|
||||
bool arith_inverse = false;
|
||||
|
||||
if (cell->type.in(ID($add), ID($sub), ID($alu), ID($or), ID($xor)))
|
||||
if (cell->type.in(TW($add), TW($sub), TW($alu), TW($or), TW($xor)))
|
||||
{
|
||||
RTLIL::SigSpec a = assign_map(cell->getPort(TW::A));
|
||||
RTLIL::SigSpec b = assign_map(cell->getPort(TW::B));
|
||||
|
||||
bool sub = cell->type == ID($sub);
|
||||
bool sub = cell->type == TW($sub);
|
||||
|
||||
if (cell->type == ID($alu)) {
|
||||
if (cell->type == TW($alu)) {
|
||||
RTLIL::SigBit sig_ci = assign_map(cell->getPort(TW::CI));
|
||||
RTLIL::SigBit sig_bi = assign_map(cell->getPort(TW::BI));
|
||||
|
||||
|
|
@ -1437,7 +1439,7 @@ skip_fine_alu:
|
|||
identity_wrt_a = true;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)))
|
||||
if (cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx)))
|
||||
{
|
||||
RTLIL::SigSpec b = assign_map(cell->getPort(TW::B));
|
||||
|
||||
|
|
@ -1445,7 +1447,7 @@ skip_fine_alu:
|
|||
identity_wrt_a = true;
|
||||
}
|
||||
|
||||
if (cell->type == ID($mul))
|
||||
if (cell->type == TW($mul))
|
||||
{
|
||||
RTLIL::SigSpec a = assign_map(cell->getPort(TW::A));
|
||||
RTLIL::SigSpec b = assign_map(cell->getPort(TW::B));
|
||||
|
|
@ -1457,7 +1459,7 @@ skip_fine_alu:
|
|||
identity_wrt_a = true;
|
||||
}
|
||||
|
||||
if (cell->type == ID($div))
|
||||
if (cell->type == TW($div))
|
||||
{
|
||||
RTLIL::SigSpec b = assign_map(cell->getPort(TW::B));
|
||||
|
||||
|
|
@ -1470,7 +1472,7 @@ skip_fine_alu:
|
|||
log_debug("Replacing %s cell `%s' in module `%s' with identity for port %c.\n",
|
||||
cell->type.c_str(), cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str(), identity_wrt_a ? 'A' : 'B');
|
||||
|
||||
if (cell->type == ID($alu)) {
|
||||
if (cell->type == TW($alu)) {
|
||||
bool a_signed = cell->parameters[ID::A_SIGNED].as_bool();
|
||||
bool b_signed = cell->parameters[ID::B_SIGNED].as_bool();
|
||||
bool is_signed = a_signed && b_signed;
|
||||
|
|
@ -1502,7 +1504,7 @@ skip_fine_alu:
|
|||
a_port_width = cell->getParam(identity_wrt_a ? ID::A_WIDTH : ID::B_WIDTH).as_int();
|
||||
}
|
||||
|
||||
IdString new_type = arith_inverse ? ID($neg) : ID($pos);
|
||||
TwineRef new_type = arith_inverse ? TW($neg) : TW($pos);
|
||||
SigSpec new_y = patcher.addWire(NEW_TWINE, y_width);
|
||||
Cell *new_cell = patcher.addCell(NEW_TWINE, new_type);
|
||||
new_cell->setPort(TW::A, a_port);
|
||||
|
|
@ -1533,20 +1535,20 @@ skip_fine_alu:
|
|||
}
|
||||
skip_identity:
|
||||
|
||||
if (mux_bool && cell->type.in(ID($mux), ID($_MUX_)) &&
|
||||
if (mux_bool && cell->type.in(TW($mux), TW($_MUX_)) &&
|
||||
cell->getPort(TW::A) == State::S0 && cell->getPort(TW::B) == State::S1) {
|
||||
OptExprPatcher patcher(module, &assign_map);
|
||||
patcher.patch(cell, TW::Y, cell->getPort(TW::S), "mux_bool");
|
||||
goto next_cell;
|
||||
}
|
||||
|
||||
if (mux_bool && cell->type.in(ID($mux), ID($_MUX_)) &&
|
||||
if (mux_bool && cell->type.in(TW($mux), TW($_MUX_)) &&
|
||||
cell->getPort(TW::A) == State::S1 && cell->getPort(TW::B) == State::S0) {
|
||||
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", cell->type.unescape(), cell, module);
|
||||
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", cell->type.unescaped(), cell, module);
|
||||
cell->setPort(TW::A, cell->getPort(TW::S));
|
||||
cell->unsetPort(TW::B);
|
||||
cell->unsetPort(TW::S);
|
||||
if (cell->type == ID($mux)) {
|
||||
if (cell->type == TW($mux)) {
|
||||
Const width = cell->parameters[ID::WIDTH];
|
||||
cell->parameters[ID::A_WIDTH] = width;
|
||||
cell->parameters[ID::Y_WIDTH] = width;
|
||||
|
|
@ -1559,11 +1561,11 @@ skip_identity:
|
|||
goto next_cell;
|
||||
}
|
||||
|
||||
if (consume_x && mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(TW::A) == State::S0) {
|
||||
log_debug("Replacing %s cell `%s' in module `%s' with and-gate.\n", cell->type.unescape(), cell, module);
|
||||
if (consume_x && mux_bool && cell->type.in(TW($mux), TW($_MUX_)) && cell->getPort(TW::A) == State::S0) {
|
||||
log_debug("Replacing %s cell `%s' in module `%s' with and-gate.\n", cell->type.unescaped(), cell, module);
|
||||
cell->setPort(TW::A, cell->getPort(TW::S));
|
||||
cell->unsetPort(TW::S);
|
||||
if (cell->type == ID($mux)) {
|
||||
if (cell->type == TW($mux)) {
|
||||
Const width = cell->parameters[ID::WIDTH];
|
||||
cell->parameters[ID::A_WIDTH] = width;
|
||||
cell->parameters[ID::B_WIDTH] = width;
|
||||
|
|
@ -1578,11 +1580,11 @@ skip_identity:
|
|||
goto next_cell;
|
||||
}
|
||||
|
||||
if (consume_x && mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(TW::B) == State::S1) {
|
||||
log_debug("Replacing %s cell `%s' in module `%s' with or-gate.\n", cell->type.unescape(), cell, module);
|
||||
if (consume_x && mux_bool && cell->type.in(TW($mux), TW($_MUX_)) && cell->getPort(TW::B) == State::S1) {
|
||||
log_debug("Replacing %s cell `%s' in module `%s' with or-gate.\n", cell->type.unescaped(), cell, module);
|
||||
cell->setPort(TW::B, cell->getPort(TW::S));
|
||||
cell->unsetPort(TW::S);
|
||||
if (cell->type == ID($mux)) {
|
||||
if (cell->type == TW($mux)) {
|
||||
Const width = cell->parameters[ID::WIDTH];
|
||||
cell->parameters[ID::A_WIDTH] = width;
|
||||
cell->parameters[ID::B_WIDTH] = width;
|
||||
|
|
@ -1597,7 +1599,7 @@ skip_identity:
|
|||
goto next_cell;
|
||||
}
|
||||
|
||||
if (mux_undef && cell->type.in(ID($mux), ID($pmux))) {
|
||||
if (mux_undef && cell->type.in(TW($mux), TW($pmux))) {
|
||||
RTLIL::SigSpec new_a, new_b, new_s;
|
||||
int width = GetSize(cell->getPort(TW::A));
|
||||
if ((cell->getPort(TW::A).is_fully_undef() && cell->getPort(TW::B).is_fully_undef()) ||
|
||||
|
|
@ -1632,7 +1634,7 @@ skip_identity:
|
|||
}
|
||||
if (cell->getPort(TW::S).size() != new_s.size()) {
|
||||
log_debug("Optimized away %d select inputs of %s cell `%s' in module `%s'.\n",
|
||||
GetSize(cell->getPort(TW::S)) - GetSize(new_s), cell->type.unescape(), cell, module);
|
||||
GetSize(cell->getPort(TW::S)) - GetSize(new_s), cell->type.unescaped(), cell, module);
|
||||
cell->setPort(TW::A, new_a);
|
||||
cell->setPort(TW::B, new_b);
|
||||
cell->setPort(TW::S, new_s);
|
||||
|
|
@ -1647,10 +1649,10 @@ skip_identity:
|
|||
}
|
||||
}
|
||||
|
||||
if (mux_undef && cell->type.in(ID($_MUX4_), ID($_MUX8_), ID($_MUX16_))) {
|
||||
if (mux_undef && cell->type.in(TW($_MUX4_), TW($_MUX8_), TW($_MUX16_))) {
|
||||
int num_inputs = 4;
|
||||
if (cell->type == ID($_MUX8_)) num_inputs = 8;
|
||||
if (cell->type == ID($_MUX16_)) num_inputs = 16;
|
||||
if (cell->type == TW($_MUX8_)) num_inputs = 8;
|
||||
if (cell->type == TW($_MUX16_)) num_inputs = 16;
|
||||
int undef_inputs = 0;
|
||||
for (auto &conn : cell->connections())
|
||||
if (conn.first != TW::S && conn.first != TW::T && conn.first != TW::U && conn.first != TW::V && conn.first != TW::Y)
|
||||
|
|
@ -1663,7 +1665,7 @@ skip_identity:
|
|||
}
|
||||
|
||||
#define FOLD_1ARG_CELL(_t) \
|
||||
if (cell->type == ID($##_t)) { \
|
||||
if (cell->type == TW($##_t)) { \
|
||||
RTLIL::SigSpec a = cell->getPort(TW::A); \
|
||||
assign_map.apply(a); \
|
||||
if (a.is_fully_const()) { \
|
||||
|
|
@ -1677,7 +1679,7 @@ skip_identity:
|
|||
} \
|
||||
}
|
||||
#define FOLD_2ARG_CELL(_t) \
|
||||
if (cell->type == ID($##_t)) { \
|
||||
if (cell->type == TW($##_t)) { \
|
||||
RTLIL::SigSpec a = cell->getPort(TW::A); \
|
||||
RTLIL::SigSpec b = cell->getPort(TW::B); \
|
||||
assign_map.apply(a), assign_map.apply(b); \
|
||||
|
|
@ -1692,7 +1694,7 @@ skip_identity:
|
|||
} \
|
||||
}
|
||||
#define FOLD_2ARG_SIMPLE_CELL(_t, B_ID) \
|
||||
if (cell->type == ID($##_t)) { \
|
||||
if (cell->type == TW($##_t)) { \
|
||||
RTLIL::SigSpec a = cell->getPort(TW::A); \
|
||||
RTLIL::SigSpec b = cell->getPort(B_ID); \
|
||||
assign_map.apply(a), assign_map.apply(b); \
|
||||
|
|
@ -1704,7 +1706,7 @@ skip_identity:
|
|||
} \
|
||||
}
|
||||
#define FOLD_MUX_CELL(_t) \
|
||||
if (cell->type == ID($##_t)) { \
|
||||
if (cell->type == TW($##_t)) { \
|
||||
RTLIL::SigSpec a = cell->getPort(TW::A); \
|
||||
RTLIL::SigSpec b = cell->getPort(TW::B); \
|
||||
RTLIL::SigSpec s = cell->getPort(TW::S); \
|
||||
|
|
@ -1770,7 +1772,7 @@ skip_identity:
|
|||
FOLD_MUX_CELL(bwmux);
|
||||
|
||||
// be very conservative with optimizing $mux cells as we do not want to break mux trees
|
||||
if (cell->type == ID($mux)) {
|
||||
if (cell->type == TW($mux)) {
|
||||
RTLIL::SigSpec input = assign_map(cell->getPort(TW::S));
|
||||
RTLIL::SigSpec inA = assign_map(cell->getPort(TW::A));
|
||||
RTLIL::SigSpec inB = assign_map(cell->getPort(TW::B));
|
||||
|
|
@ -1779,7 +1781,7 @@ skip_identity:
|
|||
else if (inA == inB)
|
||||
ACTION_DO(TW::Y, cell->getPort(TW::A));
|
||||
}
|
||||
if (cell->type == ID($pow) && cell->getPort(TW::A).is_fully_const() && !cell->parameters[ID::B_SIGNED].as_bool()) {
|
||||
if (cell->type == TW($pow) && cell->getPort(TW::A).is_fully_const() && !cell->parameters[ID::B_SIGNED].as_bool()) {
|
||||
SigSpec sig_a = assign_map(cell->getPort(TW::A));
|
||||
SigSpec sig_y = assign_map(cell->getPort(TW::Y));
|
||||
int y_size = GetSize(sig_y);
|
||||
|
|
@ -1806,7 +1808,7 @@ skip_identity:
|
|||
int a_width = cell->parameters[ID::A_WIDTH].as_int();
|
||||
|
||||
SigSpec y_wire = patcher.addWire(NEW_TWINE, y_size);
|
||||
Cell *mul = patcher.addCell(NEW_TWINE, ID($mul));
|
||||
Cell *mul = patcher.addCell(NEW_TWINE, TW($mul));
|
||||
mul->setPort(TW::A, Const(bit_idx, a_width));
|
||||
mul->setPort(TW::B, cell->getPort(TW::B));
|
||||
mul->setPort(TW::Y, y_wire);
|
||||
|
|
@ -1826,7 +1828,7 @@ skip_identity:
|
|||
goto next_cell;
|
||||
}
|
||||
}
|
||||
if (!keepdc && cell->type == ID($mul))
|
||||
if (!keepdc && cell->type == TW($mul))
|
||||
{
|
||||
bool a_signed = cell->parameters[ID::A_SIGNED].as_bool();
|
||||
bool b_signed = cell->parameters[ID::B_SIGNED].as_bool();
|
||||
|
|
@ -1914,7 +1916,7 @@ skip_identity:
|
|||
}
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor)))
|
||||
if (cell->type.in(TW($div), TW($mod), TW($divfloor), TW($modfloor)))
|
||||
{
|
||||
bool a_signed = cell->parameters[ID::A_SIGNED].as_bool();
|
||||
bool b_signed = cell->parameters[ID::B_SIGNED].as_bool();
|
||||
|
|
@ -1937,9 +1939,9 @@ skip_identity:
|
|||
int exp;
|
||||
if (!keepdc && sig_b.is_onehot(&exp) && !(b_signed && exp == GetSize(sig_b) - 1))
|
||||
{
|
||||
if (cell->type.in(ID($div), ID($divfloor)))
|
||||
if (cell->type.in(TW($div), TW($divfloor)))
|
||||
{
|
||||
bool is_truncating = cell->type == ID($div);
|
||||
bool is_truncating = cell->type == TW($div);
|
||||
log_debug("Replacing %s-divide-by-%s cell `%s' in module `%s' with shift-by-%d.\n",
|
||||
is_truncating ? "truncating" : "flooring",
|
||||
log_signal(sig_b), cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str(), exp);
|
||||
|
|
@ -1965,9 +1967,9 @@ skip_identity:
|
|||
|
||||
cell->check();
|
||||
}
|
||||
else if (cell->type.in(ID($mod), ID($modfloor)))
|
||||
else if (cell->type.in(TW($mod), TW($modfloor)))
|
||||
{
|
||||
bool is_truncating = cell->type == ID($mod);
|
||||
bool is_truncating = cell->type == TW($mod);
|
||||
log_debug("Replacing %s-modulo-by-%s cell `%s' in module `%s' with bitmask.\n",
|
||||
is_truncating ? "truncating" : "flooring",
|
||||
log_signal(sig_b), cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str());
|
||||
|
|
@ -2010,7 +2012,7 @@ skip_identity:
|
|||
}
|
||||
|
||||
// Find places in $alu cell where the carry is constant, and split it at these points.
|
||||
if (do_fine && !keepdc && cell->type == ID($alu))
|
||||
if (do_fine && !keepdc && cell->type == TW($alu))
|
||||
{
|
||||
bool a_signed = cell->parameters[ID::A_SIGNED].as_bool();
|
||||
bool b_signed = cell->parameters[ID::B_SIGNED].as_bool();
|
||||
|
|
@ -2075,7 +2077,7 @@ skip_identity:
|
|||
SigSpec slice_x = patcher.addWire(NEW_TWINE, sz);
|
||||
SigSpec slice_co = patcher.addWire(NEW_TWINE, sz);
|
||||
|
||||
RTLIL::Cell *c = patcher.addCell(NEW_TWINE, cell->type);
|
||||
RTLIL::Cell *c = patcher.addCell(NEW_TWINE, cell->type_impl);
|
||||
c->setPort(TW::A, sig_a.extract(prev, sz));
|
||||
c->setPort(TW::B, sig_b.extract(prev, sz));
|
||||
c->setPort(TW::BI, sig_bi);
|
||||
|
|
@ -2107,7 +2109,7 @@ skip_alu_split:
|
|||
|
||||
// remove redundant pairs of bits in ==, ===, !=, and !==
|
||||
// replace cell with const driver if inputs can't be equal
|
||||
if (do_fine && cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex)))
|
||||
if (do_fine && cell->type.in(TW($eq), TW($ne), TW($eqx), TW($nex)))
|
||||
{
|
||||
pool<pair<SigBit, SigBit>> redundant_cache;
|
||||
mfp<SigBit> contradiction_cache;
|
||||
|
|
@ -2153,7 +2155,7 @@ skip_alu_split:
|
|||
if (contradiction_cache.find(State::S0) == contradiction_cache.find(State::S1))
|
||||
{
|
||||
SigSpec y_sig = cell->getPort(TW::Y);
|
||||
Const y_value(cell->type.in(ID($eq), ID($eqx)) ? 0 : 1, GetSize(y_sig));
|
||||
Const y_value(cell->type.in(TW($eq), TW($eqx)) ? 0 : 1, GetSize(y_sig));
|
||||
|
||||
log_debug("Replacing cell `%s' in module `%s' with constant driver %s.\n",
|
||||
cell, module, log_signal(y_value));
|
||||
|
|
@ -2166,7 +2168,7 @@ skip_alu_split:
|
|||
if (redundant_bits)
|
||||
{
|
||||
log_debug("Removed %d redundant input bits from %s cell `%s' in module `%s'.\n",
|
||||
redundant_bits, cell->type.unescape(), cell, module);
|
||||
redundant_bits, cell->type.unescaped(), cell, module);
|
||||
|
||||
cell->setPort(TW::A, sig_a);
|
||||
cell->setPort(TW::B, sig_b);
|
||||
|
|
@ -2179,7 +2181,7 @@ skip_alu_split:
|
|||
}
|
||||
|
||||
// simplify comparisons
|
||||
if (do_fine && cell->type.in(ID($lt), ID($ge), ID($gt), ID($le)))
|
||||
if (do_fine && cell->type.in(TW($lt), TW($ge), TW($gt), TW($le)))
|
||||
{
|
||||
IdString cmp_type = cell->type;
|
||||
SigSpec var_sig = cell->getPort(TW::A);
|
||||
|
|
@ -2192,14 +2194,14 @@ skip_alu_split:
|
|||
{
|
||||
std::swap(var_sig, const_sig);
|
||||
std::swap(var_width, const_width);
|
||||
if (cmp_type == ID($gt))
|
||||
cmp_type = ID($lt);
|
||||
else if (cmp_type == ID($lt))
|
||||
cmp_type = ID($gt);
|
||||
else if (cmp_type == ID($ge))
|
||||
cmp_type = ID($le);
|
||||
else if (cmp_type == ID($le))
|
||||
cmp_type = ID($ge);
|
||||
if (cmp_type == TW($gt))
|
||||
cmp_type = TW($lt);
|
||||
else if (cmp_type == TW($lt))
|
||||
cmp_type = TW($gt);
|
||||
else if (cmp_type == TW($ge))
|
||||
cmp_type = TW($le);
|
||||
else if (cmp_type == TW($le))
|
||||
cmp_type = TW($ge);
|
||||
}
|
||||
|
||||
if (const_sig.is_fully_def() && const_sig.is_fully_const())
|
||||
|
|
@ -2211,25 +2213,25 @@ skip_alu_split:
|
|||
|
||||
if (!is_signed)
|
||||
{ /* unsigned */
|
||||
if (const_sig.is_fully_zero() && cmp_type == ID($lt)) {
|
||||
if (const_sig.is_fully_zero() && cmp_type == TW($lt)) {
|
||||
condition = "unsigned X<0";
|
||||
replacement = "constant 0";
|
||||
replace_sig[0] = State::S0;
|
||||
replace = true;
|
||||
}
|
||||
if (const_sig.is_fully_zero() && cmp_type == ID($ge)) {
|
||||
if (const_sig.is_fully_zero() && cmp_type == TW($ge)) {
|
||||
condition = "unsigned X>=0";
|
||||
replacement = "constant 1";
|
||||
replace_sig[0] = State::S1;
|
||||
replace = true;
|
||||
}
|
||||
if (const_width == var_width && const_sig.is_fully_ones() && cmp_type == ID($gt)) {
|
||||
if (const_width == var_width && const_sig.is_fully_ones() && cmp_type == TW($gt)) {
|
||||
condition = "unsigned X>~0";
|
||||
replacement = "constant 0";
|
||||
replace_sig[0] = State::S0;
|
||||
replace = true;
|
||||
}
|
||||
if (const_width == var_width && const_sig.is_fully_ones() && cmp_type == ID($le)) {
|
||||
if (const_width == var_width && const_sig.is_fully_ones() && cmp_type == TW($le)) {
|
||||
condition = "unsigned X<=~0";
|
||||
replacement = "constant 1";
|
||||
replace_sig[0] = State::S1;
|
||||
|
|
@ -2244,14 +2246,14 @@ skip_alu_split:
|
|||
var_high_sig[i - const_bit_hot] = var_sig[i];
|
||||
}
|
||||
|
||||
if (cmp_type == ID($lt))
|
||||
if (cmp_type == TW($lt))
|
||||
{
|
||||
condition = stringf("unsigned X<%s", log_signal(const_sig));
|
||||
replacement = stringf("!X[%d:%d]", var_width - 1, const_bit_hot);
|
||||
replace_sig[0] = patcher.LogicNot(NEW_TWINE, var_high_sig).as_bit();
|
||||
replace = true;
|
||||
}
|
||||
if (cmp_type == ID($ge))
|
||||
if (cmp_type == TW($ge))
|
||||
{
|
||||
condition = stringf("unsigned X>=%s", log_signal(const_sig));
|
||||
replacement = stringf("|X[%d:%d]", var_width - 1, const_bit_hot);
|
||||
|
|
@ -2264,19 +2266,19 @@ skip_alu_split:
|
|||
if (const_bit_set >= var_width)
|
||||
{
|
||||
string cmp_name;
|
||||
if (cmp_type == ID($lt) || cmp_type == ID($le))
|
||||
if (cmp_type == TW($lt) || cmp_type == TW($le))
|
||||
{
|
||||
if (cmp_type == ID($lt)) cmp_name = "<";
|
||||
if (cmp_type == ID($le)) cmp_name = "<=";
|
||||
if (cmp_type == TW($lt)) cmp_name = "<";
|
||||
if (cmp_type == TW($le)) cmp_name = "<=";
|
||||
condition = stringf("unsigned X[%d:0]%s%s", var_width - 1, cmp_name, log_signal(const_sig));
|
||||
replacement = "constant 1";
|
||||
replace_sig[0] = State::S1;
|
||||
replace = true;
|
||||
}
|
||||
if (cmp_type == ID($gt) || cmp_type == ID($ge))
|
||||
if (cmp_type == TW($gt) || cmp_type == TW($ge))
|
||||
{
|
||||
if (cmp_type == ID($gt)) cmp_name = ">";
|
||||
if (cmp_type == ID($ge)) cmp_name = ">=";
|
||||
if (cmp_type == TW($gt)) cmp_name = ">";
|
||||
if (cmp_type == TW($ge)) cmp_name = ">=";
|
||||
condition = stringf("unsigned X[%d:0]%s%s", var_width - 1, cmp_name, log_signal(const_sig));
|
||||
replacement = "constant 0";
|
||||
replace_sig[0] = State::S0;
|
||||
|
|
@ -2286,14 +2288,14 @@ skip_alu_split:
|
|||
}
|
||||
else
|
||||
{ /* signed */
|
||||
if (const_sig.is_fully_zero() && cmp_type == ID($lt))
|
||||
if (const_sig.is_fully_zero() && cmp_type == TW($lt))
|
||||
{
|
||||
condition = "signed X<0";
|
||||
replacement = stringf("X[%d]", var_width - 1);
|
||||
replace_sig[0] = var_sig[var_width - 1];
|
||||
replace = true;
|
||||
}
|
||||
if (const_sig.is_fully_zero() && cmp_type == ID($ge))
|
||||
if (const_sig.is_fully_zero() && cmp_type == TW($ge))
|
||||
{
|
||||
condition = "signed X>=0";
|
||||
replacement = stringf("X[%d]", var_width - 1);
|
||||
|
|
|
|||
|
|
@ -52,9 +52,9 @@ struct OptFfInvWorker
|
|||
continue;
|
||||
if (port.port != TW::Y)
|
||||
return false;
|
||||
if (port.cell->type.in(ID($not), ID($_NOT_))) {
|
||||
if (port.cell->type.in(TW($not), TW($_NOT_))) {
|
||||
// OK
|
||||
} else if (port.cell->type.in(ID($lut))) {
|
||||
} else if (port.cell->type.in(TW($lut))) {
|
||||
if (port.cell->getParam(ID::WIDTH) != 1)
|
||||
return false;
|
||||
if (port.cell->getParam(ID::LUT).as_int() != 1)
|
||||
|
|
@ -78,7 +78,7 @@ struct OptFfInvWorker
|
|||
return false;
|
||||
if (port.port != TW::A)
|
||||
return false;
|
||||
if (!port.cell->type.in(ID($not), ID($_NOT_), ID($lut)))
|
||||
if (!port.cell->type.in(TW($not), TW($_NOT_), TW($lut)))
|
||||
return false;
|
||||
q_luts.insert(port.cell);
|
||||
}
|
||||
|
|
@ -87,7 +87,7 @@ struct OptFfInvWorker
|
|||
ff.sig_d = d_inv->getPort(TW::A);
|
||||
|
||||
for (Cell *lut: q_luts) {
|
||||
if (lut->type == ID($lut)) {
|
||||
if (lut->type == TW($lut)) {
|
||||
int flip_mask = 0;
|
||||
SigSpec sig_a = lut->getPort(TW::A);
|
||||
for (int i = 0; i < GetSize(sig_a); i++) {
|
||||
|
|
@ -137,7 +137,7 @@ struct OptFfInvWorker
|
|||
continue;
|
||||
if (port.port != TW::Y)
|
||||
return false;
|
||||
if (!port.cell->type.in(ID($not), ID($_NOT_), ID($lut)))
|
||||
if (!port.cell->type.in(TW($not), TW($_NOT_), TW($lut)))
|
||||
return false;
|
||||
log_assert(d_lut == nullptr);
|
||||
d_lut = port.cell;
|
||||
|
|
@ -157,9 +157,9 @@ struct OptFfInvWorker
|
|||
return false;
|
||||
if (port.port != TW::A)
|
||||
return false;
|
||||
if (port.cell->type.in(ID($not), ID($_NOT_))) {
|
||||
if (port.cell->type.in(TW($not), TW($_NOT_))) {
|
||||
// OK
|
||||
} else if (port.cell->type.in(ID($lut))) {
|
||||
} else if (port.cell->type.in(TW($lut))) {
|
||||
if (port.cell->getParam(ID::WIDTH) != 1)
|
||||
return false;
|
||||
if (port.cell->getParam(ID::LUT).as_int() != 1)
|
||||
|
|
@ -176,7 +176,7 @@ struct OptFfInvWorker
|
|||
ff.sig_q = q_inv->getPort(TW::Y);
|
||||
module->remove(q_inv);
|
||||
|
||||
if (d_lut->type == ID($lut)) {
|
||||
if (d_lut->type == TW($lut)) {
|
||||
Const mask = d_lut->getParam(ID::LUT);
|
||||
Const::Builder new_mask_builder(GetSize(mask));
|
||||
for (int i = 0; i < GetSize(mask); i++) {
|
||||
|
|
|
|||
|
|
@ -101,7 +101,7 @@ struct ModuleIndex {
|
|||
if (!port || (!port->port_input && !port->port_output) || port->width != value.size()) {
|
||||
log_error("Port %s connected on instance %s not found in module %s"
|
||||
" or width is not matching\n",
|
||||
port_name.unescape(), instantiation, module);
|
||||
design->twines.unescaped_str(port_name), instantiation, module);
|
||||
}
|
||||
|
||||
if (port->port_input && port->port_output) {
|
||||
|
|
@ -145,12 +145,12 @@ struct ModuleIndex {
|
|||
|
||||
if (nunused > 0) {
|
||||
log("Disconnected %d input bits of instance '%s' (type '%s') in '%s'\n",
|
||||
nunused, instantiation, instantiation->type.unescape(), parent.module);
|
||||
nunused, instantiation, design->twines.unescaped_str(instantiation->type), parent.module);
|
||||
changed = true;
|
||||
}
|
||||
if (nconstants > 0) {
|
||||
log("Substituting constant for %d output bits of instance '%s' (type '%s') in '%s'\n",
|
||||
nconstants, instantiation, instantiation->type.unescape(), parent.module);
|
||||
nconstants, instantiation, design->twines.unescaped_str(instantiation->type), parent.module);
|
||||
changed = true;
|
||||
}
|
||||
}
|
||||
|
|
@ -163,8 +163,8 @@ struct ModuleIndex {
|
|||
SigSpec new_tie;
|
||||
|
||||
for (auto port_bit : class_) {
|
||||
if (instantiation->connections_.count(port_bit.wire->name)) {
|
||||
SigBit bit = instantiation->connections_.at(port_bit.wire->name)[port_bit.offset];
|
||||
if (instantiation->connections_.count(port_bit.wire->meta_->name)) {
|
||||
SigBit bit = instantiation->connections_.at(port_bit.wire->meta_->name)[port_bit.offset];
|
||||
if (parent.used.check(bit)) {
|
||||
if (!new_tie.empty()) {
|
||||
severed_port_bits.append(port_bit);
|
||||
|
|
@ -181,7 +181,7 @@ struct ModuleIndex {
|
|||
|
||||
severed_port_bits.sort_and_unify();
|
||||
for (auto chunk : severed_port_bits.chunks()) {
|
||||
SigSpec &value = instantiation->connections_.at(chunk.wire->name);
|
||||
SigSpec &value = instantiation->connections_.at(chunk.wire->meta_->name);
|
||||
SigSpec dummy = parent.module->addWire(NEW_TWINE_SUFFIX("tie_together"), chunk.width);
|
||||
for (int i = 0; i < chunk.width; i++)
|
||||
value[chunk.offset + i] = dummy[i];
|
||||
|
|
@ -189,7 +189,7 @@ struct ModuleIndex {
|
|||
|
||||
if (ntie_togethers > 0) {
|
||||
log("Replacing %d output bits with tie-togethers on instance '%s' of '%s' in '%s'\n",
|
||||
ntie_togethers, instantiation, instantiation->type.unescape(), parent.module);
|
||||
ntie_togethers, instantiation, design->twines.unescaped_str(instantiation->type), parent.module);
|
||||
changed = true;
|
||||
}
|
||||
|
||||
|
|
@ -290,7 +290,7 @@ struct UsageData {
|
|||
if (!port || (!port->port_input && !port->port_output) || port->width != value.size()) {
|
||||
log_error("Port %s connected on instance %s not found in module %s"
|
||||
" or width is not matching\n",
|
||||
port_name.unescape(), instance, module);
|
||||
module->design->twines.unescaped_str(port_name), instance, module);
|
||||
}
|
||||
|
||||
if (port->port_input && port->port_output) {
|
||||
|
|
@ -338,7 +338,7 @@ struct UsageData {
|
|||
|
||||
dict<SigBit, SigBit> replacement_map;
|
||||
for (auto chunk : disconnect_outputs.chunks()) {
|
||||
Wire *repl_wire = module->addWire(module->uniquify(std::string("$") + chunk.wire->name.str()), chunk.size());
|
||||
Wire *repl_wire = module->addWire(module->uniquify(Twine{std::string("$") + chunk.wire->name.str()}), chunk.size());
|
||||
for (int i = 0; i < repl_wire->width; i++)
|
||||
replacement_map[SigSpec(chunk)[i]] = SigBit(repl_wire, i);
|
||||
}
|
||||
|
|
@ -454,7 +454,7 @@ struct OptHierPass : Pass {
|
|||
for (auto module : d->modules()) {
|
||||
for (auto cell : module->cells()) {
|
||||
if (usage_datas.count(cell->type)) {
|
||||
log_debug("Account for instance %s of %s in %s\n", cell, cell->type.unescape(), module);
|
||||
log_debug("Account for instance %s of %s in %s\n", cell, cell->type.unescaped(), module);
|
||||
usage_datas.at(cell->type).refine(cell, indices.at(module->name));
|
||||
}
|
||||
}
|
||||
|
|
@ -471,7 +471,7 @@ struct OptHierPass : Pass {
|
|||
|
||||
for (auto cell : module->cells()) {
|
||||
if (indices.count(cell->type)) {
|
||||
log_debug("Applying changes to instance %s of %s in %s\n", cell, cell->type.unescape(), module);
|
||||
log_debug("Applying changes to instance %s of %s in %s\n", cell, cell->type.unescaped(), module);
|
||||
did_something |= indices.at(cell->type).apply_changes(parent_index, cell);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -109,7 +109,7 @@ struct OptLutWorker
|
|||
log("Discovering LUTs.\n");
|
||||
for (auto cell : module->selected_cells())
|
||||
{
|
||||
if (cell->type == ID($lut))
|
||||
if (cell->type == TW($lut))
|
||||
{
|
||||
if (cell->has_keep_attr())
|
||||
continue;
|
||||
|
|
|
|||
|
|
@ -77,7 +77,7 @@ struct OptLutInsPass : public Pass {
|
|||
std::vector<SigBit> output;
|
||||
bool ignore_const = false;
|
||||
if (techname == "") {
|
||||
if (cell->type != ID($lut))
|
||||
if (cell->type != TW($lut))
|
||||
continue;
|
||||
inputs = cell->getPort(TW::A);
|
||||
output = cell->getPort(TW::Y);
|
||||
|
|
|
|||
|
|
@ -108,13 +108,13 @@ struct OptMemPass : public Pass {
|
|||
}
|
||||
State bit;
|
||||
if (!always_0[i]) {
|
||||
log("%s.%s: removing const-1 lane %d\n", module->name.unescape(), mem.memid.unescape(), i);
|
||||
log("%s.%s: removing const-1 lane %d\n", design->twines.unescaped_str(module->name), design->twines.unescaped_str(mem.memid), i);
|
||||
bit = State::S1;
|
||||
} else if (!always_1[i]) {
|
||||
log("%s.%s: removing const-0 lane %d\n", module->name.unescape(), mem.memid.unescape(), i);
|
||||
log("%s.%s: removing const-0 lane %d\n", design->twines.unescaped_str(module->name), design->twines.unescaped_str(mem.memid), i);
|
||||
bit = State::S0;
|
||||
} else {
|
||||
log("%s.%s: removing const-x lane %d\n", module->name.unescape(), mem.memid.unescape(), i);
|
||||
log("%s.%s: removing const-x lane %d\n", design->twines.unescaped_str(module->name), design->twines.unescaped_str(mem.memid), i);
|
||||
bit = State::Sx;
|
||||
}
|
||||
// Reconnect read port data.
|
||||
|
|
|
|||
|
|
@ -163,7 +163,7 @@ struct OptMemFeedbackWorker
|
|||
{
|
||||
auto &port = mem.wr_ports[i];
|
||||
|
||||
log(" Analyzing %s.%s write port %d.\n", module, mem.memid.unescape(), i);
|
||||
log(" Analyzing %s.%s write port %d.\n", module, design->twines.unescaped_str(mem.memid), i);
|
||||
|
||||
for (int sub = 0; sub < (1 << port.wide_log2); sub++)
|
||||
{
|
||||
|
|
@ -232,7 +232,7 @@ struct OptMemFeedbackWorker
|
|||
|
||||
// Okay, let's do it.
|
||||
|
||||
log("Populating enable bits on write ports of memory %s.%s with async read feedback:\n", module, mem.memid.unescape());
|
||||
log("Populating enable bits on write ports of memory %s.%s with async read feedback:\n", module, design->twines.unescaped_str(mem.memid));
|
||||
|
||||
// If a write port has a feedback path that we're about to bypass,
|
||||
// but also has priority over some other write port, the feedback
|
||||
|
|
@ -293,7 +293,7 @@ struct OptMemFeedbackWorker
|
|||
|
||||
for (auto cell : module->cells())
|
||||
{
|
||||
if (cell->type == ID($mux))
|
||||
if (cell->type == TW($mux))
|
||||
{
|
||||
RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(TW::A));
|
||||
RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(TW::B));
|
||||
|
|
@ -304,7 +304,7 @@ struct OptMemFeedbackWorker
|
|||
sigmap_xmux.add(cell->getPort(TW::Y), sig_a);
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($mux), ID($pmux)))
|
||||
if (cell->type.in(TW($mux), TW($pmux)))
|
||||
{
|
||||
std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(TW::Y));
|
||||
for (int i = 0; i < int(sig_y.size()); i++)
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@ struct OptMemWidenPass : public Pass {
|
|||
factor_log2 = port.wide_log2;
|
||||
if (factor_log2 == 0)
|
||||
continue;
|
||||
log("Widening base width of memory %s in module %s by factor %d.\n", mem.memid.unescape(), design->twines.str(module->meta_->name).c_str(), 1 << factor_log2);
|
||||
log("Widening base width of memory %s in module %s by factor %d.\n", design->twines.unescaped_str(mem.memid), design->twines.str(module->meta_->name).c_str(), 1 << factor_log2);
|
||||
total_count++;
|
||||
// The inits are too messy to expand one-by-one, for they may
|
||||
// collide with one another after expansion. Just hit it with
|
||||
|
|
|
|||
|
|
@ -121,18 +121,18 @@ struct OptMergeThreadWorker : public CellHasher
|
|||
const RTLIL::Cell *cell = module->cell_at(cell_index);
|
||||
if (!module->selected(cell))
|
||||
continue;
|
||||
if (cell->type.in(ID($meminit), ID($meminit_v2), ID($mem), ID($mem_v2))) {
|
||||
if (cell->type.in(TW($meminit), TW($meminit_v2), TW($mem), TW($mem_v2))) {
|
||||
// Ignore those for performance: meminit can have an excessively large port,
|
||||
// mem can have an excessively large parameter holding the init data
|
||||
continue;
|
||||
}
|
||||
if (cell->type == ID($scopeinfo))
|
||||
if (cell->type == TW($scopeinfo))
|
||||
continue;
|
||||
if (mode_keepdc && has_dont_care_initval(cell))
|
||||
continue;
|
||||
if (!cell->known())
|
||||
continue;
|
||||
if (!mode_share_all && !ct.cell_known(cell->type))
|
||||
if (!mode_share_all && !ct.cell_known(cell->type_impl))
|
||||
continue;
|
||||
|
||||
Hasher::hash_t h = hash_cell_function(cell, Hasher()).yield();
|
||||
|
|
@ -397,20 +397,20 @@ struct OptMergePass : public Pass {
|
|||
ct.setup_stdcells();
|
||||
ct.setup_stdcells_mem();
|
||||
if (mode_nomux) {
|
||||
ct.cell_types.erase(ID($mux));
|
||||
ct.cell_types.erase(ID($pmux));
|
||||
ct.cell_types.erase(TW($mux));
|
||||
ct.cell_types.erase(TW($pmux));
|
||||
}
|
||||
ct.cell_types.erase(ID($tribuf));
|
||||
ct.cell_types.erase(ID($_TBUF_));
|
||||
ct.cell_types.erase(ID($anyseq));
|
||||
ct.cell_types.erase(ID($anyconst));
|
||||
ct.cell_types.erase(ID($allseq));
|
||||
ct.cell_types.erase(ID($allconst));
|
||||
ct.cell_types.erase(TW($tribuf));
|
||||
ct.cell_types.erase(TW($_TBUF_));
|
||||
ct.cell_types.erase(TW($anyseq));
|
||||
ct.cell_types.erase(TW($anyconst));
|
||||
ct.cell_types.erase(TW($allseq));
|
||||
ct.cell_types.erase(TW($allconst));
|
||||
// Synthetic driver cells signorm creates for module ports — must
|
||||
// never be folded into one another, otherwise distinct ports collapse.
|
||||
ct.cell_types.erase(ID($input_port));
|
||||
ct.cell_types.erase(ID($output_port));
|
||||
ct.cell_types.erase(ID($public));
|
||||
ct.cell_types.erase(TW($input_port));
|
||||
ct.cell_types.erase(TW($output_port));
|
||||
ct.cell_types.erase(TW($public));
|
||||
|
||||
// patcher.patch uses connect_incremental + fanout queries.
|
||||
design->sigNormalize(true);
|
||||
|
|
|
|||
|
|
@ -91,21 +91,21 @@ struct CellHasher
|
|||
{
|
||||
// TODO: when implemented, use celltypes to match:
|
||||
// (builtin || stdcell) && (unary || binary) && symmetrical
|
||||
if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul),
|
||||
ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) {
|
||||
if (cell->type.in(TW($and), TW($or), TW($xor), TW($xnor), TW($add), TW($mul),
|
||||
TW($logic_and), TW($logic_or), TW($_AND_), TW($_OR_), TW($_XOR_))) {
|
||||
hashlib::commutative_hash comm;
|
||||
comm.eat(map_sig(cell->getPort(TW::A)));
|
||||
comm.eat(map_sig(cell->getPort(TW::B)));
|
||||
h = comm.hash_into(h);
|
||||
} else if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
|
||||
} else if (cell->type.in(TW($reduce_xor), TW($reduce_xnor))) {
|
||||
SigSpec a = map_sig(cell->getPort(TW::A));
|
||||
a.sort();
|
||||
h = a.hash_into(h);
|
||||
} else if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) {
|
||||
} else if (cell->type.in(TW($reduce_and), TW($reduce_or), TW($reduce_bool))) {
|
||||
SigSpec a = map_sig(cell->getPort(TW::A));
|
||||
a.sort_and_unify();
|
||||
h = a.hash_into(h);
|
||||
} else if (cell->type == ID($pmux)) {
|
||||
} else if (cell->type == TW($pmux)) {
|
||||
SigSpec sig_s = map_sig(cell->getPort(TW::S));
|
||||
SigSpec sig_b = map_sig(cell->getPort(TW::B));
|
||||
h = hash_pmux_in(sig_s, sig_b, h);
|
||||
|
|
@ -177,8 +177,8 @@ struct CellHasher
|
|||
}
|
||||
}
|
||||
|
||||
if (cell1->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul),
|
||||
ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) {
|
||||
if (cell1->type.in(TW($and), TW($or), TW($xor), TW($xnor), TW($add), TW($mul),
|
||||
TW($logic_and), TW($logic_or), TW($_AND_), TW($_OR_), TW($_XOR_))) {
|
||||
if (conn1.at(TW::A) < conn1.at(TW::B)) {
|
||||
std::swap(conn1[TW::A], conn1[TW::B]);
|
||||
}
|
||||
|
|
@ -186,15 +186,15 @@ struct CellHasher
|
|||
std::swap(conn2[TW::A], conn2[TW::B]);
|
||||
}
|
||||
} else
|
||||
if (cell1->type.in(ID($reduce_xor), ID($reduce_xnor))) {
|
||||
if (cell1->type.in(TW($reduce_xor), TW($reduce_xnor))) {
|
||||
conn1[TW::A].sort();
|
||||
conn2[TW::A].sort();
|
||||
} else
|
||||
if (cell1->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) {
|
||||
if (cell1->type.in(TW($reduce_and), TW($reduce_or), TW($reduce_bool))) {
|
||||
conn1[TW::A].sort_and_unify();
|
||||
conn2[TW::A].sort_and_unify();
|
||||
} else
|
||||
if (cell1->type == ID($pmux)) {
|
||||
if (cell1->type == TW($pmux)) {
|
||||
sort_pmux_conn(conn1);
|
||||
sort_pmux_conn(conn2);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -44,20 +44,20 @@ using MergeableTypes = StaticCellTypes::Categories::Category;
|
|||
// is intentionally not included, so $anyinit stays excluded
|
||||
static constexpr MergeableTypes build_mergeable_types(bool nomux) {
|
||||
auto c = StaticCellTypes::categories.is_known;
|
||||
c.set_id(ID($anyinit), false);
|
||||
c.set_id(ID($tribuf), false);
|
||||
c.set_id(ID($_TBUF_), false);
|
||||
c.set_id(ID($anyseq), false);
|
||||
c.set_id(ID($anyconst), false);
|
||||
c.set_id(ID($allseq), false);
|
||||
c.set_id(ID($allconst), false);
|
||||
c.set_id(ID($connect), false);
|
||||
c.set_id(ID($input_port), false);
|
||||
c.set_id(ID($output_port), false);
|
||||
c.set_id(ID($public), false);
|
||||
c.set_id(TW($anyinit), false);
|
||||
c.set_id(TW($tribuf), false);
|
||||
c.set_id(TW($_TBUF_), false);
|
||||
c.set_id(TW($anyseq), false);
|
||||
c.set_id(TW($anyconst), false);
|
||||
c.set_id(TW($allseq), false);
|
||||
c.set_id(TW($allconst), false);
|
||||
c.set_id(TW($connect), false);
|
||||
c.set_id(TW($input_port), false);
|
||||
c.set_id(TW($output_port), false);
|
||||
c.set_id(TW($public), false);
|
||||
if (nomux) {
|
||||
c.set_id(ID($mux), false);
|
||||
c.set_id(ID($pmux), false);
|
||||
c.set_id(TW($mux), false);
|
||||
c.set_id(TW($pmux), false);
|
||||
}
|
||||
return c;
|
||||
}
|
||||
|
|
@ -161,18 +161,18 @@ struct OptMergeIncWorker
|
|||
for (auto cell : module->cells()) {
|
||||
if (!design->selected(module, cell))
|
||||
continue;
|
||||
if (cell->type.in(ID($meminit), ID($meminit_v2), ID($mem), ID($mem_v2))) {
|
||||
if (cell->type.in(TW($meminit), TW($meminit_v2), TW($mem), TW($mem_v2))) {
|
||||
// Ignore those for performance: meminit can have an excessively large port,
|
||||
// mem can have an excessively large parameter holding the init data
|
||||
continue;
|
||||
}
|
||||
if (cell->type == ID($scopeinfo))
|
||||
if (cell->type == TW($scopeinfo))
|
||||
continue;
|
||||
if (mode_keepdc && hasher.has_dont_care_initval(cell))
|
||||
continue;
|
||||
if (!cell->known())
|
||||
continue;
|
||||
if (!mode_share_all && !ct(cell->type))
|
||||
if (!mode_share_all && !ct(cell->type_impl))
|
||||
continue;
|
||||
|
||||
cells.push_back(cell);
|
||||
|
|
@ -190,18 +190,18 @@ struct OptMergeIncWorker
|
|||
for (auto cell : module->dirty_cells(timestamp)) {
|
||||
if (!design->selected(module, cell))
|
||||
continue;
|
||||
if (cell->type.in(ID($meminit), ID($meminit_v2), ID($mem), ID($mem_v2))) {
|
||||
if (cell->type.in(TW($meminit), TW($meminit_v2), TW($mem), TW($mem_v2))) {
|
||||
// Ignore those for performance: meminit can have an excessively large port,
|
||||
// mem can have an excessively large parameter holding the init data
|
||||
continue;
|
||||
}
|
||||
if (cell->type == ID($scopeinfo))
|
||||
if (cell->type == TW($scopeinfo))
|
||||
continue;
|
||||
if (mode_keepdc && hasher.has_dont_care_initval(cell))
|
||||
continue;
|
||||
if (!cell->known())
|
||||
continue;
|
||||
if (!mode_share_all && !ct(cell->type))
|
||||
if (!mode_share_all && !ct(cell->type_impl))
|
||||
continue;
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -232,7 +232,7 @@ struct OptMuxtreeWorker
|
|||
|
||||
for (auto cell : module->cells())
|
||||
{
|
||||
if (cell->type.in(ID($mux), ID($pmux)))
|
||||
if (cell->type.in(TW($mux), TW($pmux)))
|
||||
track_mux(cell);
|
||||
else
|
||||
see_non_mux_cell(cell);
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ struct OptReduceWorker
|
|||
for (auto &bit : sig_a)
|
||||
{
|
||||
if (bit == RTLIL::State::S0) {
|
||||
if (cell->type == ID($reduce_and)) {
|
||||
if (cell->type == TW($reduce_and)) {
|
||||
new_sig_a_bits.clear();
|
||||
new_sig_a_bits.insert(RTLIL::State::S0);
|
||||
break;
|
||||
|
|
@ -58,7 +58,7 @@ struct OptReduceWorker
|
|||
continue;
|
||||
}
|
||||
if (bit == RTLIL::State::S1) {
|
||||
if (cell->type == ID($reduce_or)) {
|
||||
if (cell->type == TW($reduce_or)) {
|
||||
new_sig_a_bits.clear();
|
||||
new_sig_a_bits.insert(RTLIL::State::S1);
|
||||
break;
|
||||
|
|
@ -90,7 +90,7 @@ struct OptReduceWorker
|
|||
new_sig_a.sort_and_unify();
|
||||
|
||||
if (GetSize(new_sig_a) == 0)
|
||||
new_sig_a = (cell->type == ID($reduce_or)) ? State::S0 : State::S1;
|
||||
new_sig_a = (cell->type == TW($reduce_or)) ? State::S0 : State::S1;
|
||||
|
||||
if (new_sig_a != sig_a || sig_a.size() != cell->getPort(TW::A).size()) {
|
||||
log(" New input vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_a));
|
||||
|
|
@ -126,7 +126,7 @@ struct OptReduceWorker
|
|||
RTLIL::SigSpec this_s{this_s_bit};
|
||||
if (this_s.size() > 1)
|
||||
{
|
||||
RTLIL::Cell *reduce_or_cell = module->addCell(NEW_TWINE, ID($reduce_or));
|
||||
RTLIL::Cell *reduce_or_cell = module->addCell(NEW_TWINE, TW($reduce_or));
|
||||
reduce_or_cell->setPort(TW::A, this_s);
|
||||
reduce_or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
|
||||
reduce_or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(this_s.size());
|
||||
|
|
@ -151,7 +151,7 @@ struct OptReduceWorker
|
|||
return;
|
||||
}
|
||||
|
||||
if (new_sig_s.size() != sig_s.size() || (new_sig_s.size() == 1 && cell->type == ID($pmux))) {
|
||||
if (new_sig_s.size() != sig_s.size() || (new_sig_s.size() == 1 && cell->type == TW($pmux))) {
|
||||
log(" New ctrl vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_s));
|
||||
did_something = true;
|
||||
total_count++;
|
||||
|
|
@ -338,7 +338,7 @@ struct OptReduceWorker
|
|||
SigSpec sig_y = assign_map(cell->getPort(TW::Y));
|
||||
int width = GetSize(sig_y);
|
||||
|
||||
if (cell->type != ID($bmux))
|
||||
if (cell->type != TW($bmux))
|
||||
sig_b = assign_map(cell->getPort(TW::B));
|
||||
|
||||
RTLIL::SigSig old_sig_conn;
|
||||
|
|
@ -386,7 +386,7 @@ struct OptReduceWorker
|
|||
if (GetSize(swizzle) != width)
|
||||
{
|
||||
log(" Consolidated identical input bits for %s cell %s:\n", cell->type, cell->name);
|
||||
if (cell->type != ID($bmux)) {
|
||||
if (cell->type != TW($bmux)) {
|
||||
log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(TW::A)),
|
||||
log_signal(cell->getPort(TW::B)), log_signal(cell->getPort(TW::Y)));
|
||||
} else {
|
||||
|
|
@ -403,7 +403,7 @@ struct OptReduceWorker
|
|||
new_sig_a.append(sig_a[i+j]);
|
||||
cell->setPort(TW::A, new_sig_a);
|
||||
|
||||
if (cell->type != ID($bmux)) {
|
||||
if (cell->type != TW($bmux)) {
|
||||
SigSpec new_sig_b;
|
||||
for (int i = 0; i < GetSize(sig_b); i += width)
|
||||
for (int j: swizzle)
|
||||
|
|
@ -418,7 +418,7 @@ struct OptReduceWorker
|
|||
|
||||
cell->parameters[ID::WIDTH] = RTLIL::Const(GetSize(swizzle));
|
||||
|
||||
if (cell->type != ID($bmux)) {
|
||||
if (cell->type != TW($bmux)) {
|
||||
log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(TW::A)),
|
||||
log_signal(cell->getPort(TW::B)), log_signal(cell->getPort(TW::Y)));
|
||||
} else {
|
||||
|
|
@ -520,14 +520,14 @@ struct OptReduceWorker
|
|||
SigPool mem_wren_sigs;
|
||||
for (auto &cell_it : module->cells_) {
|
||||
RTLIL::Cell *cell = cell_it.second;
|
||||
if (cell->type.in(ID($mem), ID($mem_v2)))
|
||||
if (cell->type.in(TW($mem), TW($mem_v2)))
|
||||
mem_wren_sigs.add(assign_map(cell->getPort(TW::WR_EN)));
|
||||
if (cell->type.in(ID($memwr), ID($memwr_v2)))
|
||||
if (cell->type.in(TW($memwr), TW($memwr_v2)))
|
||||
mem_wren_sigs.add(assign_map(cell->getPort(TW::EN)));
|
||||
}
|
||||
for (auto &cell_it : module->cells_) {
|
||||
RTLIL::Cell *cell = cell_it.second;
|
||||
if (cell->type == ID($dff) && mem_wren_sigs.check_any(assign_map(cell->getPort(TW::Q))))
|
||||
if (cell->type == TW($dff) && mem_wren_sigs.check_any(assign_map(cell->getPort(TW::Q))))
|
||||
mem_wren_sigs.add(assign_map(cell->getPort(TW::D)));
|
||||
}
|
||||
|
||||
|
|
@ -536,7 +536,7 @@ struct OptReduceWorker
|
|||
keep_expanding_mem_wren_sigs = false;
|
||||
for (auto &cell_it : module->cells_) {
|
||||
RTLIL::Cell *cell = cell_it.second;
|
||||
if (cell->type == ID($mux) && mem_wren_sigs.check_any(assign_map(cell->getPort(TW::Y)))) {
|
||||
if (cell->type == TW($mux) && mem_wren_sigs.check_any(assign_map(cell->getPort(TW::Y)))) {
|
||||
if (!mem_wren_sigs.check_all(assign_map(cell->getPort(TW::A))) ||
|
||||
!mem_wren_sigs.check_all(assign_map(cell->getPort(TW::B))))
|
||||
keep_expanding_mem_wren_sigs = true;
|
||||
|
|
@ -553,7 +553,7 @@ struct OptReduceWorker
|
|||
// merge trees of reduce_* cells to one single cell and unify input vectors
|
||||
// (only handle reduce_and and reduce_or for various reasons)
|
||||
|
||||
const IdString type_list[] = { ID($reduce_or), ID($reduce_and) };
|
||||
const IdString type_list[] = { TW($reduce_or), TW($reduce_and) };
|
||||
for (auto type : type_list)
|
||||
{
|
||||
SigSet<RTLIL::Cell*> drivers;
|
||||
|
|
@ -577,13 +577,13 @@ struct OptReduceWorker
|
|||
|
||||
for (auto cell : module->selected_cells())
|
||||
{
|
||||
if (!cell->type.in(ID($mux), ID($pmux), ID($bmux), ID($demux)))
|
||||
if (!cell->type.in(TW($mux), TW($pmux), TW($bmux), TW($demux)))
|
||||
continue;
|
||||
|
||||
// this optimization is to aggressive for most coarse-grain applications.
|
||||
// but we always want it for multiplexers driving write enable ports.
|
||||
if (do_fine || mem_wren_sigs.check_any(assign_map(cell->getPort(TW::Y)))) {
|
||||
if (cell->type == ID($demux)) {
|
||||
if (cell->type == TW($demux)) {
|
||||
if (opt_demux_bits(cell))
|
||||
continue;
|
||||
} else {
|
||||
|
|
@ -592,11 +592,11 @@ struct OptReduceWorker
|
|||
}
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($mux), ID($pmux)))
|
||||
if (cell->type.in(TW($mux), TW($pmux)))
|
||||
opt_pmux(cell);
|
||||
else if (cell->type == ID($bmux))
|
||||
else if (cell->type == TW($bmux))
|
||||
opt_bmux(cell);
|
||||
else if (cell->type == ID($demux))
|
||||
else if (cell->type == TW($demux))
|
||||
opt_demux(cell);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -81,27 +81,27 @@ struct ExtSigSpec {
|
|||
bool operator==(const ExtSigSpec &other) const { return is_signed == other.is_signed && sign == other.sign && sig == other.sig && semantics == other.semantics; }
|
||||
};
|
||||
|
||||
#define FINE_BITWISE_OPS ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)
|
||||
#define FINE_BITWISE_OPS TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_), TW($_XOR_), TW($_XNOR_), TW($_ANDNOT_), TW($_ORNOT_)
|
||||
|
||||
#define BITWISE_OPS FINE_BITWISE_OPS, ID($and), ID($or), ID($xor), ID($xnor)
|
||||
#define BITWISE_OPS FINE_BITWISE_OPS, TW($and), TW($or), TW($xor), TW($xnor)
|
||||
|
||||
#define REDUCTION_OPS ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($reduce_nand)
|
||||
#define REDUCTION_OPS TW($reduce_and), TW($reduce_or), TW($reduce_xor), TW($reduce_xnor), TW($reduce_bool), TW($reduce_nand)
|
||||
|
||||
#define LOGICAL_OPS ID($logic_and), ID($logic_or)
|
||||
#define LOGICAL_OPS TW($logic_and), TW($logic_or)
|
||||
|
||||
#define SHIFT_OPS ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)
|
||||
#define SHIFT_OPS TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx)
|
||||
|
||||
#define RELATIONAL_OPS ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt)
|
||||
#define RELATIONAL_OPS TW($lt), TW($le), TW($eq), TW($ne), TW($eqx), TW($nex), TW($ge), TW($gt)
|
||||
|
||||
bool cell_supported(RTLIL::Cell *cell)
|
||||
{
|
||||
if (cell->type.in(ID($alu))) {
|
||||
if (cell->type.in(TW($alu))) {
|
||||
RTLIL::SigSpec sig_bi = cell->getPort(TW::BI);
|
||||
RTLIL::SigSpec sig_ci = cell->getPort(TW::CI);
|
||||
|
||||
if (sig_bi.is_fully_const() && sig_ci.is_fully_const() && sig_bi == sig_ci)
|
||||
return true;
|
||||
} else if (cell->type.in(LOGICAL_OPS, SHIFT_OPS, BITWISE_OPS, RELATIONAL_OPS, ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($concat))) {
|
||||
} else if (cell->type.in(LOGICAL_OPS, SHIFT_OPS, BITWISE_OPS, RELATIONAL_OPS, TW($add), TW($sub), TW($mul), TW($div), TW($mod), TW($divfloor), TW($modfloor), TW($concat))) {
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -113,7 +113,7 @@ std::map<IdString, IdString> mergeable_type_map;
|
|||
bool mergeable(RTLIL::Cell *a, RTLIL::Cell *b)
|
||||
{
|
||||
if (mergeable_type_map.empty()) {
|
||||
mergeable_type_map.insert({ID($sub), ID($add)});
|
||||
mergeable_type_map.insert({TW($sub), TW($add)});
|
||||
}
|
||||
auto a_type = a->type;
|
||||
if (mergeable_type_map.count(a_type))
|
||||
|
|
@ -128,10 +128,10 @@ bool mergeable(RTLIL::Cell *a, RTLIL::Cell *b)
|
|||
|
||||
TwineRef decode_port_semantics(RTLIL::Cell *cell, TwineRef port_name)
|
||||
{
|
||||
if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($concat), SHIFT_OPS) && port_name == TW::B)
|
||||
if (cell->type.in(TW($lt), TW($le), TW($ge), TW($gt), TW($div), TW($mod), TW($divfloor), TW($modfloor), TW($concat), SHIFT_OPS) && port_name == TW::B)
|
||||
return port_name;
|
||||
|
||||
if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
|
||||
if (cell->type.in(TW($_ANDNOT_), TW($_ORNOT_)))
|
||||
return port_name;
|
||||
|
||||
return Twine::Null;
|
||||
|
|
@ -139,9 +139,9 @@ TwineRef decode_port_semantics(RTLIL::Cell *cell, TwineRef port_name)
|
|||
|
||||
RTLIL::SigSpec decode_port_sign(RTLIL::Cell *cell, TwineRef port_name) {
|
||||
|
||||
if (cell->type == ID($alu) && port_name == TW::B)
|
||||
if (cell->type == TW($alu) && port_name == TW::B)
|
||||
return cell->getPort(TW::BI);
|
||||
else if (cell->type == ID($sub) && port_name == TW::B)
|
||||
else if (cell->type == TW($sub) && port_name == TW::B)
|
||||
return RTLIL::Const(1, 1);
|
||||
|
||||
return RTLIL::Const(0, 1);
|
||||
|
|
@ -247,7 +247,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
|
|||
mux_to_oper = module->Pmux(NEW_TWINE, shared_pmux_a, shared_pmux_b, shared_pmux_s);
|
||||
}
|
||||
|
||||
if (shared_op->type.in(ID($alu))) {
|
||||
if (shared_op->type.in(TW($alu))) {
|
||||
shared_op->setPort(TW::X, module->addWire(NEW_TWINE, GetSize(new_out)));
|
||||
shared_op->setPort(TW::CO, module->addWire(NEW_TWINE, GetSize(new_out)));
|
||||
}
|
||||
|
|
@ -365,7 +365,7 @@ struct OptSharePass : public Pass {
|
|||
dict<RTLIL::SigBit, int> bit_users;
|
||||
|
||||
for (auto cell : module->cells()) {
|
||||
if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
|
||||
if (cell->type.in(TW($input_port), TW($output_port), TW($public)))
|
||||
continue;
|
||||
for (auto conn : cell->connections())
|
||||
for (auto bit : conn.second)
|
||||
|
|
@ -386,7 +386,7 @@ struct OptSharePass : public Pass {
|
|||
continue;
|
||||
|
||||
bool skip = false;
|
||||
if (cell->type == ID($alu)) {
|
||||
if (cell->type == TW($alu)) {
|
||||
for (TwineRef port_name : {TW::X, TW::CO}) {
|
||||
for (auto outbit : sigmap(cell->getPort(port_name)))
|
||||
if (bit_users[outbit] > 1)
|
||||
|
|
@ -417,7 +417,7 @@ struct OptSharePass : public Pass {
|
|||
std::vector<merged_op_t> merged_ops;
|
||||
|
||||
for (auto mux : module->selected_cells()) {
|
||||
if (!mux->type.in(ID($mux), ID($_MUX_), ID($pmux)))
|
||||
if (!mux->type.in(TW($mux), TW($_MUX_), TW($pmux)))
|
||||
continue;
|
||||
|
||||
int mux_port_size = GetSize(mux->getPort(TW::A));
|
||||
|
|
@ -564,7 +564,7 @@ struct OptSharePass : public Pass {
|
|||
log(" Found cells that share an operand and can be merged by moving the %s %s in front "
|
||||
"of "
|
||||
"them:\n",
|
||||
shared.mux->type.unescape(), shared.mux);
|
||||
design->twines.unescaped_str(shared.mux->type), shared.mux);
|
||||
for (const auto& op : shared.ports)
|
||||
log(" %s\n", op.op);
|
||||
log("\n");
|
||||
|
|
|
|||
|
|
@ -54,17 +54,17 @@ struct OnehotDatabase
|
|||
vector<SigSpec> inputs;
|
||||
SigSpec output;
|
||||
|
||||
if (cell->type.in(ID($adff), ID($adffe), ID($dff), ID($dffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch), ID($ff)))
|
||||
if (cell->type.in(TW($adff), TW($adffe), TW($dff), TW($dffe), TW($sdff), TW($sdffe), TW($sdffce), TW($dlatch), TW($adlatch), TW($ff)))
|
||||
{
|
||||
output = cell->getPort(TW::Q);
|
||||
if (cell->type.in(ID($adff), ID($adffe), ID($adlatch)))
|
||||
if (cell->type.in(TW($adff), TW($adffe), TW($adlatch)))
|
||||
inputs.push_back(cell->getParam(ID::ARST_VALUE));
|
||||
if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce)))
|
||||
if (cell->type.in(TW($sdff), TW($sdffe), TW($sdffce)))
|
||||
inputs.push_back(cell->getParam(ID::SRST_VALUE));
|
||||
inputs.push_back(cell->getPort(TW::D));
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($mux), ID($pmux)))
|
||||
if (cell->type.in(TW($mux), TW($pmux)))
|
||||
{
|
||||
output = cell->getPort(TW::Y);
|
||||
inputs.push_back(cell->getPort(TW::A));
|
||||
|
|
@ -285,7 +285,7 @@ struct Pmux2ShiftxPass : public Pass {
|
|||
|
||||
for (auto cell : module->cells())
|
||||
{
|
||||
if (cell->type == ID($eq))
|
||||
if (cell->type == TW($eq))
|
||||
{
|
||||
dict<SigBit, State> bits;
|
||||
|
||||
|
|
@ -333,7 +333,7 @@ struct Pmux2ShiftxPass : public Pass {
|
|||
goto next_cell;
|
||||
}
|
||||
|
||||
if (cell->type == ID($logic_not))
|
||||
if (cell->type == TW($logic_not))
|
||||
{
|
||||
dict<SigBit, State> bits;
|
||||
|
||||
|
|
@ -359,10 +359,10 @@ struct Pmux2ShiftxPass : public Pass {
|
|||
|
||||
for (auto cell : module->selected_cells())
|
||||
{
|
||||
if (cell->type != ID($pmux))
|
||||
if (cell->type != TW($pmux))
|
||||
continue;
|
||||
|
||||
string src = cell->get_src_attribute();
|
||||
TwineRef src = cell->meta_->src;
|
||||
int width = cell->getParam(ID::WIDTH).as_int();
|
||||
int width_bits = ceil_log2(width);
|
||||
int extwidth = width;
|
||||
|
|
@ -777,7 +777,7 @@ struct OnehotPass : public Pass {
|
|||
|
||||
for (auto cell : module->selected_cells())
|
||||
{
|
||||
if (cell->type != ID($eq))
|
||||
if (cell->type != TW($eq))
|
||||
continue;
|
||||
|
||||
SigSpec A = sigmap(cell->getPort(TW::A));
|
||||
|
|
@ -851,7 +851,7 @@ struct OnehotPass : public Pass {
|
|||
}
|
||||
|
||||
RTLIL::Patch patcher(module, &sigmap);
|
||||
patcher.patch(cell, ID::Y, replacement);
|
||||
patcher.patch(cell, TW::Y, replacement);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -74,7 +74,7 @@ struct ShareWorker
|
|||
queue_bits.insert(modwalker.signal_outputs.begin(), modwalker.signal_outputs.end());
|
||||
|
||||
for (auto &it : module->cells_)
|
||||
if (!StaticCellTypes::Compat::internals_nomem_noff(it.second->type)) {
|
||||
if (!StaticCellTypes::Compat::internals_nomem_noff(it.second->type_impl)) {
|
||||
pool<RTLIL::SigBit> &bits = modwalker.cell_inputs[it.second];
|
||||
queue_bits.insert(bits.begin(), bits.end());
|
||||
}
|
||||
|
|
@ -88,13 +88,13 @@ struct ShareWorker
|
|||
queue_bits.clear();
|
||||
|
||||
for (auto &pbit : portbits) {
|
||||
if ((pbit.cell->type == ID($mux) || pbit.cell->type == ID($pmux)) && visited_cells.count(pbit.cell) == 0) {
|
||||
if ((pbit.cell->type == TW($mux) || pbit.cell->type == TW($pmux)) && visited_cells.count(pbit.cell) == 0) {
|
||||
pool<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->getPort(TW::S)).to_sigbit_pool();
|
||||
terminal_bits.insert(bits.begin(), bits.end());
|
||||
queue_bits.insert(bits.begin(), bits.end());
|
||||
visited_cells.insert(pbit.cell);
|
||||
}
|
||||
if (StaticCellTypes::Compat::internals_nomem_noff(pbit.cell->type) && visited_cells.count(pbit.cell) == 0) {
|
||||
if (StaticCellTypes::Compat::internals_nomem_noff(pbit.cell->type_impl) && visited_cells.count(pbit.cell) == 0) {
|
||||
pool<RTLIL::SigBit> &bits = modwalker.cell_inputs[pbit.cell];
|
||||
terminal_bits.insert(bits.begin(), bits.end());
|
||||
queue_bits.insert(bits.begin(), bits.end());
|
||||
|
|
@ -351,7 +351,7 @@ struct ShareWorker
|
|||
{
|
||||
for (auto cell : module->cells())
|
||||
{
|
||||
if (!design->selected(module, cell) || !modwalker.ct.cell_known(cell->type))
|
||||
if (!design->selected(module, cell) || !modwalker.ct.cell_known(cell->type_impl))
|
||||
continue;
|
||||
|
||||
for (auto &bit : modwalker.cell_outputs[cell])
|
||||
|
|
@ -362,7 +362,7 @@ struct ShareWorker
|
|||
not_a_muxed_cell:
|
||||
continue;
|
||||
|
||||
if (cell->type.in(ID($memrd), ID($memrd_v2))) {
|
||||
if (cell->type.in(TW($memrd), TW($memrd_v2))) {
|
||||
if (cell->parameters.at(ID::CLK_ENABLE).as_bool())
|
||||
continue;
|
||||
if (config.opt_aggressive || !modwalker.sigmap(cell->getPort(TW::ADDR)).is_fully_const())
|
||||
|
|
@ -370,19 +370,19 @@ struct ShareWorker
|
|||
continue;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
|
||||
if (cell->type.in(TW($mul), TW($div), TW($mod), TW($divfloor), TW($modfloor))) {
|
||||
if (config.opt_aggressive || cell->parameters.at(ID::Y_WIDTH).as_int() >= 4)
|
||||
shareable_cells.insert(cell);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
|
||||
if (cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr))) {
|
||||
if (config.opt_aggressive || cell->parameters.at(ID::Y_WIDTH).as_int() >= 8)
|
||||
shareable_cells.insert(cell);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (generic_ops(cell->type)) {
|
||||
if (generic_ops(cell->type_impl)) {
|
||||
if (config.opt_aggressive)
|
||||
shareable_cells.insert(cell);
|
||||
continue;
|
||||
|
|
@ -395,7 +395,7 @@ struct ShareWorker
|
|||
if (c1->type != c2->type)
|
||||
return false;
|
||||
|
||||
if (c1->type.in(ID($memrd), ID($memrd_v2)))
|
||||
if (c1->type.in(TW($memrd), TW($memrd_v2)))
|
||||
{
|
||||
if (c1->parameters.at(ID::MEMID).decode_string() != c2->parameters.at(ID::MEMID).decode_string())
|
||||
return false;
|
||||
|
|
@ -406,7 +406,7 @@ struct ShareWorker
|
|||
return true;
|
||||
}
|
||||
|
||||
if (config.generic_uni_ops(c1->type))
|
||||
if (config.generic_uni_ops(c1->type_impl))
|
||||
{
|
||||
if (!config.opt_aggressive)
|
||||
{
|
||||
|
|
@ -423,7 +423,7 @@ struct ShareWorker
|
|||
return true;
|
||||
}
|
||||
|
||||
if (config.generic_bin_ops(c1->type) || c1->type == ID($alu))
|
||||
if (config.generic_bin_ops(c1->type_impl) || c1->type == TW($alu))
|
||||
{
|
||||
if (!config.opt_aggressive)
|
||||
{
|
||||
|
|
@ -443,7 +443,7 @@ struct ShareWorker
|
|||
return true;
|
||||
}
|
||||
|
||||
if (config.generic_cbin_ops(c1->type))
|
||||
if (config.generic_cbin_ops(c1->type_impl))
|
||||
{
|
||||
if (!config.opt_aggressive)
|
||||
{
|
||||
|
|
@ -469,7 +469,7 @@ struct ShareWorker
|
|||
return true;
|
||||
}
|
||||
|
||||
if (c1->type == ID($macc))
|
||||
if (c1->type == TW($macc))
|
||||
{
|
||||
if (!config.opt_aggressive)
|
||||
if (share_macc(c1, c2) > 2 * min(bits_macc(c1), bits_macc(c2))) return false;
|
||||
|
|
@ -505,7 +505,7 @@ struct ShareWorker
|
|||
{
|
||||
log_assert(c1->type == c2->type);
|
||||
|
||||
if (config.generic_uni_ops(c1->type))
|
||||
if (config.generic_uni_ops(c1->type_impl))
|
||||
{
|
||||
if (c1->parameters.at(ID::A_SIGNED).as_bool() != c2->parameters.at(ID::A_SIGNED).as_bool())
|
||||
{
|
||||
|
|
@ -540,7 +540,7 @@ struct ShareWorker
|
|||
|
||||
RTLIL::Wire *y = module->addWire(NEW_TWINE, y_width);
|
||||
|
||||
RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type);
|
||||
RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type_impl);
|
||||
supercell->parameters[ID::A_SIGNED] = a_signed;
|
||||
supercell->parameters[ID::A_WIDTH] = a_width;
|
||||
supercell->parameters[ID::Y_WIDTH] = y_width;
|
||||
|
|
@ -554,11 +554,11 @@ struct ShareWorker
|
|||
return supercell;
|
||||
}
|
||||
|
||||
if (config.generic_bin_ops(c1->type) || config.generic_cbin_ops(c1->type) || c1->type == ID($alu))
|
||||
if (config.generic_bin_ops(c1->type_impl) || config.generic_cbin_ops(c1->type_impl) || c1->type_impl == TW($alu))
|
||||
{
|
||||
bool modified_src_cells = false;
|
||||
|
||||
if (config.generic_cbin_ops(c1->type))
|
||||
if (config.generic_cbin_ops(c1->type_impl))
|
||||
{
|
||||
int score_unflipped = max(c1->parameters.at(ID::A_WIDTH).as_int(), c2->parameters.at(ID::A_WIDTH).as_int()) +
|
||||
max(c1->parameters.at(ID::B_WIDTH).as_int(), c2->parameters.at(ID::B_WIDTH).as_int());
|
||||
|
|
@ -616,7 +616,7 @@ struct ShareWorker
|
|||
log_assert(a_signed == c2->parameters.at(ID::A_SIGNED).as_bool());
|
||||
log_assert(b_signed == c2->parameters.at(ID::B_SIGNED).as_bool());
|
||||
|
||||
if (c1->type == ID($shl) || c1->type == ID($shr) || c1->type == ID($sshl) || c1->type == ID($sshr))
|
||||
if (c1->type == TW($shl) || c1->type == TW($shr) || c1->type == TW($sshl) || c1->type == TW($sshr))
|
||||
b_signed = false;
|
||||
|
||||
RTLIL::SigSpec a1 = c1->getPort(TW::A);
|
||||
|
|
@ -631,7 +631,7 @@ struct ShareWorker
|
|||
int b_width = max(b1.size(), b2.size());
|
||||
int y_width = max(y1.size(), y2.size());
|
||||
|
||||
if (c1->type == ID($shr) && a_signed)
|
||||
if (c1->type == TW($shr) && a_signed)
|
||||
{
|
||||
a_width = max(y_width, a_width);
|
||||
|
||||
|
|
@ -657,10 +657,10 @@ struct ShareWorker
|
|||
supercell_aux.insert(module->addMux(NEW_TWINE, b2, b1, act, b));
|
||||
|
||||
RTLIL::Wire *y = module->addWire(NEW_TWINE, y_width);
|
||||
RTLIL::Wire *x = c1->type == ID($alu) ? module->addWire(NEW_TWINE, y_width) : nullptr;
|
||||
RTLIL::Wire *co = c1->type == ID($alu) ? module->addWire(NEW_TWINE, y_width) : nullptr;
|
||||
RTLIL::Wire *x = c1->type == TW($alu) ? module->addWire(NEW_TWINE, y_width) : nullptr;
|
||||
RTLIL::Wire *co = c1->type == TW($alu) ? module->addWire(NEW_TWINE, y_width) : nullptr;
|
||||
|
||||
RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type);
|
||||
RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type_impl);
|
||||
supercell->parameters[ID::A_SIGNED] = a_signed;
|
||||
supercell->parameters[ID::B_SIGNED] = b_signed;
|
||||
supercell->parameters[ID::A_WIDTH] = a_width;
|
||||
|
|
@ -669,7 +669,7 @@ struct ShareWorker
|
|||
supercell->setPort(TW::A, a);
|
||||
supercell->setPort(TW::B, b);
|
||||
supercell->setPort(TW::Y, y);
|
||||
if (c1->type == ID($alu)) {
|
||||
if (c1->type == TW($alu)) {
|
||||
RTLIL::Wire *ci = module->addWire(NEW_TWINE), *bi = module->addWire(NEW_TWINE);
|
||||
supercell_aux.insert(module->addMux(NEW_TWINE, c2->getPort(TW::CI), c1->getPort(TW::CI), act, ci));
|
||||
supercell_aux.insert(module->addMux(NEW_TWINE, c2->getPort(TW::BI), c1->getPort(TW::BI), act, bi));
|
||||
|
|
@ -682,7 +682,7 @@ struct ShareWorker
|
|||
|
||||
supercell_aux.insert(module->addPos(NEW_TWINE, y, y1));
|
||||
supercell_aux.insert(module->addPos(NEW_TWINE, y, y2));
|
||||
if (c1->type == ID($alu)) {
|
||||
if (c1->type == TW($alu)) {
|
||||
supercell_aux.insert(module->addPos(NEW_TWINE, co, c1->getPort(TW::CO)));
|
||||
supercell_aux.insert(module->addPos(NEW_TWINE, co, c2->getPort(TW::CO)));
|
||||
supercell_aux.insert(module->addPos(NEW_TWINE, x, c1->getPort(TW::X)));
|
||||
|
|
@ -693,16 +693,16 @@ struct ShareWorker
|
|||
return supercell;
|
||||
}
|
||||
|
||||
if (c1->type == ID($macc))
|
||||
if (c1->type == TW($macc))
|
||||
{
|
||||
RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type);
|
||||
RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type_impl);
|
||||
supercell_aux.insert(supercell);
|
||||
share_macc(c1, c2, act, supercell, &supercell_aux);
|
||||
supercell->check();
|
||||
return supercell;
|
||||
}
|
||||
|
||||
if (c1->type.in(ID($memrd), ID($memrd_v2)))
|
||||
if (c1->type.in(TW($memrd), TW($memrd_v2)))
|
||||
{
|
||||
RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1);
|
||||
RTLIL::SigSpec addr1 = c1->getPort(TW::ADDR);
|
||||
|
|
@ -744,7 +744,7 @@ struct ShareWorker
|
|||
modwalker.get_consumers(pbits, modwalker.cell_outputs[cell]);
|
||||
|
||||
for (auto &bit : pbits) {
|
||||
if ((bit.cell->type == ID($mux) || bit.cell->type == ID($pmux)) && bit.port == TW::S)
|
||||
if ((bit.cell->type == TW($mux) || bit.cell->type == TW($pmux)) && bit.port == TW::S)
|
||||
forbidden_controls_cache[cell].insert(bit.cell->getPort(TW::S).extract(bit.offset, 1));
|
||||
consumer_cells.insert(bit.cell);
|
||||
}
|
||||
|
|
@ -752,7 +752,7 @@ struct ShareWorker
|
|||
recursion_state.insert(cell);
|
||||
|
||||
for (auto c : consumer_cells)
|
||||
if (StaticCellTypes::Compat::internals_nomem_noff(c->type)) {
|
||||
if (StaticCellTypes::Compat::internals_nomem_noff(c->type_impl)) {
|
||||
const pool<RTLIL::SigBit> &bits = find_forbidden_controls(c);
|
||||
forbidden_controls_cache[cell].insert(bits.begin(), bits.end());
|
||||
}
|
||||
|
|
@ -891,8 +891,8 @@ struct ShareWorker
|
|||
return activation_patterns_cache.at(cell);
|
||||
}
|
||||
for (auto &pbit : modwalker.signal_consumers[bit]) {
|
||||
log_assert(StaticCellTypes::Compat::internals_nomem_noff(pbit.cell->type));
|
||||
if ((pbit.cell->type == ID($mux) || pbit.cell->type == ID($pmux)) && (pbit.port == TW::A || pbit.port == TW::B))
|
||||
log_assert(StaticCellTypes::Compat::internals_nomem_noff(pbit.cell->type_impl));
|
||||
if ((pbit.cell->type == TW($mux) || pbit.cell->type == TW($pmux)) && (pbit.port == TW::A || pbit.port == TW::B))
|
||||
driven_data_muxes.insert(pbit.cell);
|
||||
else
|
||||
driven_cells.insert(pbit.cell);
|
||||
|
|
@ -1095,9 +1095,9 @@ struct ShareWorker
|
|||
dict<RTLIL::SigBit, pool<RTLIL::Cell*>> bit_to_cells;
|
||||
|
||||
for (auto cell : module->cells())
|
||||
if (ct.cell_known(cell->type))
|
||||
if (ct.cell_known(cell->type_impl))
|
||||
for (auto &conn : cell->connections()) {
|
||||
if (ct.cell_output(cell->type, conn.first))
|
||||
if (ct.cell_output(cell->type_impl, conn.first))
|
||||
for (auto bit : topo_sigmap(conn.second)) {
|
||||
cell_to_bits[cell].insert(bit);
|
||||
topo_bit_drivers[bit].insert(cell);
|
||||
|
|
@ -1123,7 +1123,7 @@ struct ShareWorker
|
|||
for (auto &loop : toposort.loops) {
|
||||
log("### loop ###\n");
|
||||
for (auto &c : loop)
|
||||
log("%s (%s)\n", c, c->type.unescape());
|
||||
log("%s (%s)\n", c, design->twines.unescaped_str(c->type));
|
||||
}
|
||||
|
||||
return found_scc;
|
||||
|
|
@ -1167,13 +1167,13 @@ struct ShareWorker
|
|||
pool<RTLIL::Cell*> new_queue;
|
||||
|
||||
for (auto c : queue) {
|
||||
if (!ct.cell_known(c->type))
|
||||
if (!ct.cell_known(c->type_impl))
|
||||
continue;
|
||||
for (auto &conn : c->connections())
|
||||
if (ct.cell_input(c->type, conn.first))
|
||||
if (ct.cell_input(c->type_impl, conn.first))
|
||||
for (auto bit : conn.second)
|
||||
for (auto &pi : mi.query_ports(bit))
|
||||
if (ct.cell_known(pi.cell->type) && ct.cell_output(pi.cell->type, pi.port))
|
||||
if (ct.cell_known(pi.cell->type_impl) && ct.cell_output(pi.cell->type_impl, pi.port))
|
||||
new_queue.insert(pi.cell);
|
||||
covered.insert(c);
|
||||
}
|
||||
|
|
@ -1247,7 +1247,7 @@ struct ShareWorker
|
|||
RTLIL::Cell *cell = *shareable_cells.begin();
|
||||
shareable_cells.erase(cell);
|
||||
|
||||
log(" Analyzing resource sharing options for %s (%s):\n", cell, cell->type.unescape());
|
||||
log(" Analyzing resource sharing options for %s (%s):\n", cell, cell->type.unescaped());
|
||||
|
||||
const pool<ssc_pair_t> &cell_activation_patterns = find_cell_activation_patterns(cell, " ");
|
||||
RTLIL::SigSpec cell_activation_signals = bits_from_activation_patterns(cell_activation_patterns);
|
||||
|
|
@ -1280,7 +1280,7 @@ struct ShareWorker
|
|||
|
||||
for (auto other_cell : candidates)
|
||||
{
|
||||
log(" Analyzing resource sharing with %s (%s):\n", other_cell, other_cell->type.unescape());
|
||||
log(" Analyzing resource sharing with %s (%s):\n", other_cell, design->twines.unescaped_str(other_cell->type));
|
||||
|
||||
const pool<ssc_pair_t> &other_cell_activation_patterns = find_cell_activation_patterns(other_cell, " ");
|
||||
RTLIL::SigSpec other_cell_activation_signals = bits_from_activation_patterns(other_cell_activation_patterns);
|
||||
|
|
@ -1431,7 +1431,7 @@ struct ShareWorker
|
|||
log(" Activation signal for %s: %s\n", other_cell, log_signal(act));
|
||||
}
|
||||
|
||||
log(" New cell: %s (%s)\n", supercell, supercell->type.unescape());
|
||||
log(" New cell: %s (%s)\n", supercell, design->twines.unescaped_str(supercell->type));
|
||||
|
||||
cells_to_remove.insert(cell);
|
||||
cells_to_remove.insert(other_cell);
|
||||
|
|
@ -1478,7 +1478,7 @@ struct ShareWorker
|
|||
if (!cells_to_remove.empty()) {
|
||||
log("Removing %d cells in module %s:\n", GetSize(cells_to_remove), module);
|
||||
for (auto c : cells_to_remove) {
|
||||
log(" Removing cell %s (%s).\n", c, c->type.unescape());
|
||||
log(" Removing cell %s (%s).\n", c, design->twines.unescaped_str(c->type));
|
||||
remove_cell(c);
|
||||
}
|
||||
}
|
||||
|
|
@ -1532,45 +1532,45 @@ struct SharePass : public Pass {
|
|||
config.opt_aggressive = false;
|
||||
config.opt_fast = false;
|
||||
|
||||
config.generic_uni_ops.set_id(ID($not));
|
||||
// config.generic_uni_ops.set_id(ID($pos));
|
||||
config.generic_uni_ops.set_id(ID($neg));
|
||||
config.generic_uni_ops.set_id(TW($not));
|
||||
// config.generic_uni_ops.set_id(TW($pos));
|
||||
config.generic_uni_ops.set_id(TW($neg));
|
||||
|
||||
config.generic_cbin_ops.set_id(ID($and));
|
||||
config.generic_cbin_ops.set_id(ID($or));
|
||||
config.generic_cbin_ops.set_id(ID($xor));
|
||||
config.generic_cbin_ops.set_id(ID($xnor));
|
||||
config.generic_cbin_ops.set_id(TW($and));
|
||||
config.generic_cbin_ops.set_id(TW($or));
|
||||
config.generic_cbin_ops.set_id(TW($xor));
|
||||
config.generic_cbin_ops.set_id(TW($xnor));
|
||||
|
||||
config.generic_bin_ops.set_id(ID($shl));
|
||||
config.generic_bin_ops.set_id(ID($shr));
|
||||
config.generic_bin_ops.set_id(ID($sshl));
|
||||
config.generic_bin_ops.set_id(ID($sshr));
|
||||
config.generic_bin_ops.set_id(TW($shl));
|
||||
config.generic_bin_ops.set_id(TW($shr));
|
||||
config.generic_bin_ops.set_id(TW($sshl));
|
||||
config.generic_bin_ops.set_id(TW($sshr));
|
||||
|
||||
config.generic_bin_ops.set_id(ID($lt));
|
||||
config.generic_bin_ops.set_id(ID($le));
|
||||
config.generic_bin_ops.set_id(ID($eq));
|
||||
config.generic_bin_ops.set_id(ID($ne));
|
||||
config.generic_bin_ops.set_id(ID($eqx));
|
||||
config.generic_bin_ops.set_id(ID($nex));
|
||||
config.generic_bin_ops.set_id(ID($ge));
|
||||
config.generic_bin_ops.set_id(ID($gt));
|
||||
config.generic_bin_ops.set_id(TW($lt));
|
||||
config.generic_bin_ops.set_id(TW($le));
|
||||
config.generic_bin_ops.set_id(TW($eq));
|
||||
config.generic_bin_ops.set_id(TW($ne));
|
||||
config.generic_bin_ops.set_id(TW($eqx));
|
||||
config.generic_bin_ops.set_id(TW($nex));
|
||||
config.generic_bin_ops.set_id(TW($ge));
|
||||
config.generic_bin_ops.set_id(TW($gt));
|
||||
|
||||
config.generic_cbin_ops.set_id(ID($add));
|
||||
config.generic_cbin_ops.set_id(ID($mul));
|
||||
config.generic_cbin_ops.set_id(TW($add));
|
||||
config.generic_cbin_ops.set_id(TW($mul));
|
||||
|
||||
config.generic_bin_ops.set_id(ID($sub));
|
||||
config.generic_bin_ops.set_id(ID($div));
|
||||
config.generic_bin_ops.set_id(ID($mod));
|
||||
config.generic_bin_ops.set_id(ID($divfloor));
|
||||
config.generic_bin_ops.set_id(ID($modfloor));
|
||||
// config.generic_bin_ops.set_id(ID($pow));
|
||||
config.generic_bin_ops.set_id(TW($sub));
|
||||
config.generic_bin_ops.set_id(TW($div));
|
||||
config.generic_bin_ops.set_id(TW($mod));
|
||||
config.generic_bin_ops.set_id(TW($divfloor));
|
||||
config.generic_bin_ops.set_id(TW($modfloor));
|
||||
// config.generic_bin_ops.set_id(TW($pow));
|
||||
|
||||
config.generic_uni_ops.set_id(ID($logic_not));
|
||||
config.generic_cbin_ops.set_id(ID($logic_and));
|
||||
config.generic_cbin_ops.set_id(ID($logic_or));
|
||||
config.generic_uni_ops.set_id(TW($logic_not));
|
||||
config.generic_cbin_ops.set_id(TW($logic_and));
|
||||
config.generic_cbin_ops.set_id(TW($logic_or));
|
||||
|
||||
config.generic_other_ops.set_id(ID($alu));
|
||||
config.generic_other_ops.set_id(ID($macc));
|
||||
config.generic_other_ops.set_id(TW($alu));
|
||||
config.generic_other_ops.set_id(TW($macc));
|
||||
|
||||
log_header(design, "Executing SHARE pass (SAT-based resource sharing).\n");
|
||||
|
||||
|
|
|
|||
|
|
@ -29,21 +29,21 @@ PRIVATE_NAMESPACE_BEGIN
|
|||
|
||||
struct WreduceConfig
|
||||
{
|
||||
pool<IdString> supported_cell_types;
|
||||
pool<TwineRef> supported_cell_types;
|
||||
bool keepdc = false;
|
||||
bool mux_undef = false;
|
||||
|
||||
WreduceConfig()
|
||||
{
|
||||
supported_cell_types = pool<IdString>({
|
||||
ID($not), ID($pos), ID($neg),
|
||||
ID($and), ID($or), ID($xor), ID($xnor),
|
||||
ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),
|
||||
ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),
|
||||
ID($add), ID($sub), ID($mul), // ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow),
|
||||
ID($mux), ID($pmux),
|
||||
ID($dff), ID($dffe), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce),
|
||||
ID($dlatch), ID($adlatch),
|
||||
supported_cell_types = pool<TwineRef>({
|
||||
TW($not), TW($pos), TW($neg),
|
||||
TW($and), TW($or), TW($xor), TW($xnor),
|
||||
TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx),
|
||||
TW($lt), TW($le), TW($eq), TW($ne), TW($eqx), TW($nex), TW($ge), TW($gt),
|
||||
TW($add), TW($sub), TW($mul), // TW($div), TW($mod), TW($divfloor), TW($modfloor), TW($pow),
|
||||
TW($mux), TW($pmux),
|
||||
TW($dff), TW($dffe), TW($adff), TW($adffe), TW($sdff), TW($sdffe), TW($sdffce),
|
||||
TW($dlatch), TW($adlatch),
|
||||
});
|
||||
}
|
||||
};
|
||||
|
|
@ -104,14 +104,14 @@ struct WreduceWorker
|
|||
sig_removed.append(bits_removed[i]);
|
||||
|
||||
if (GetSize(bits_removed) == GetSize(sig_y)) {
|
||||
log("Removed cell %s.%s (%s).\n", module, cell, cell->type.unescape());
|
||||
log("Removed cell %s.%s (%s).\n", module, cell, cell->type.unescaped());
|
||||
module->connect(sig_y, sig_removed);
|
||||
module->remove(cell);
|
||||
return;
|
||||
}
|
||||
|
||||
log("Removed top %d bits (of %d) from mux cell %s.%s (%s).\n",
|
||||
GetSize(sig_removed), GetSize(sig_y), module, cell, cell->type.unescape());
|
||||
GetSize(sig_removed), GetSize(sig_y), module, cell, cell->type.unescaped());
|
||||
|
||||
int n_removed = GetSize(sig_removed);
|
||||
int n_kept = GetSize(sig_y) - GetSize(sig_removed);
|
||||
|
|
@ -211,13 +211,13 @@ struct WreduceWorker
|
|||
return;
|
||||
|
||||
if (GetSize(sig_q) == 0) {
|
||||
log("Removed cell %s.%s (%s).\n", module, cell, cell->type.unescape());
|
||||
log("Removed cell %s.%s (%s).\n", module, cell, cell->type.unescaped());
|
||||
module->remove(cell);
|
||||
return;
|
||||
}
|
||||
|
||||
log("Removed top %d bits (of %d) from FF cell %s.%s (%s).\n", width_before - GetSize(sig_q), width_before,
|
||||
module, cell, cell->type.unescape());
|
||||
module, cell, cell->type.unescaped());
|
||||
|
||||
for (auto bit : sig_d)
|
||||
work_queue_bits.insert(bit);
|
||||
|
|
@ -246,7 +246,7 @@ struct WreduceWorker
|
|||
auto &twines = cell->module->design->twines;
|
||||
SigSpec sig = mi.sigmap(cell->getPort(twines.add(Twine{stringf("\\%c", port)})));
|
||||
|
||||
if (port == 'B' && cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr)))
|
||||
if (port == 'B' && cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr)))
|
||||
port_signed = false;
|
||||
|
||||
int bits_removed = 0;
|
||||
|
|
@ -267,7 +267,7 @@ struct WreduceWorker
|
|||
|
||||
if (bits_removed) {
|
||||
log("Removed top %d bits (of %d) from port %c of cell %s.%s (%s).\n",
|
||||
bits_removed, GetSize(sig) + bits_removed, port, module, cell, cell->type.unescape());
|
||||
bits_removed, GetSize(sig) + bits_removed, port, module, cell, cell->type.unescaped());
|
||||
// SigSpec sig = mi.sigmap(cell->getPort(twines.add(Twine{stringf("\\%c", port)})));
|
||||
cell->setPort(twines.add(Twine{stringf("\\%c", port)}), sig);
|
||||
did_something = true;
|
||||
|
|
@ -291,13 +291,13 @@ struct WreduceWorker
|
|||
{
|
||||
bool did_something = false;
|
||||
|
||||
if (!config->supported_cell_types.count(cell->type))
|
||||
if (!config->supported_cell_types.count(cell->type_impl))
|
||||
return;
|
||||
|
||||
if (cell->type.in(ID($mux), ID($pmux)))
|
||||
if (cell->type.in(TW($mux), TW($pmux)))
|
||||
return run_cell_mux(cell);
|
||||
|
||||
if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch)))
|
||||
if (cell->type.in(TW($dff), TW($dffe), TW($adff), TW($adffe), TW($sdff), TW($sdffe), TW($sdffce), TW($dlatch), TW($adlatch)))
|
||||
return run_cell_dff(cell);
|
||||
|
||||
SigSpec sig = mi.sigmap(cell->getPort(TW::Y));
|
||||
|
|
@ -311,7 +311,7 @@ struct WreduceWorker
|
|||
int max_port_a_size = cell->hasPort(TW::A) ? GetSize(cell->getPort(TW::A)) : -1;
|
||||
int max_port_b_size = cell->hasPort(TW::B) ? GetSize(cell->getPort(TW::B)) : -1;
|
||||
|
||||
if (cell->type.in(ID($not), ID($pos), ID($neg), ID($and), ID($or), ID($xor), ID($add), ID($sub))) {
|
||||
if (cell->type.in(TW($not), TW($pos), TW($neg), TW($and), TW($or), TW($xor), TW($add), TW($sub))) {
|
||||
max_port_a_size = min(max_port_a_size, GetSize(sig));
|
||||
max_port_b_size = min(max_port_b_size, GetSize(sig));
|
||||
}
|
||||
|
|
@ -321,7 +321,7 @@ struct WreduceWorker
|
|||
|
||||
// For some operations if the output is no wider than either of the inputs
|
||||
// we are free to choose the signedness of the operands
|
||||
if (cell->type.in(ID($mul), ID($add), ID($sub)) &&
|
||||
if (cell->type.in(TW($mul), TW($add), TW($sub)) &&
|
||||
max_port_a_size == GetSize(sig) &&
|
||||
max_port_b_size == GetSize(sig)) {
|
||||
SigSpec sig_a = mi.sigmap(cell->getPort(TW::A)), sig_b = mi.sigmap(cell->getPort(TW::B));
|
||||
|
|
@ -331,7 +331,7 @@ struct WreduceWorker
|
|||
sig_b.extend_u0(max_port_b_size);
|
||||
|
||||
int signed_cost, unsigned_cost;
|
||||
if (cell->type == ID($mul)) {
|
||||
if (cell->type == TW($mul)) {
|
||||
signed_cost = reduced_opsize(sig_a, true) * reduced_opsize(sig_b, true);
|
||||
unsigned_cost = reduced_opsize(sig_a, false) * reduced_opsize(sig_b, false);
|
||||
} else {
|
||||
|
|
@ -341,7 +341,7 @@ struct WreduceWorker
|
|||
|
||||
if (!port_a_signed && !port_b_signed && signed_cost < unsigned_cost) {
|
||||
log("Converting cell %s.%s (%s) from unsigned to signed.\n",
|
||||
module, cell, cell->type.unescape());
|
||||
module, cell, cell->type.unescaped());
|
||||
cell->setParam(ID::A_SIGNED, 1);
|
||||
cell->setParam(ID::B_SIGNED, 1);
|
||||
port_a_signed = true;
|
||||
|
|
@ -349,7 +349,7 @@ struct WreduceWorker
|
|||
did_something = true;
|
||||
} else if (port_a_signed && port_b_signed && unsigned_cost < signed_cost) {
|
||||
log("Converting cell %s.%s (%s) from signed to unsigned.\n",
|
||||
module, cell, cell->type.unescape());
|
||||
module, cell, cell->type.unescaped());
|
||||
cell->setParam(ID::A_SIGNED, 0);
|
||||
cell->setParam(ID::B_SIGNED, 0);
|
||||
port_a_signed = false;
|
||||
|
|
@ -358,7 +358,7 @@ struct WreduceWorker
|
|||
}
|
||||
}
|
||||
|
||||
if (max_port_a_size >= 0 && cell->type != ID($shiftx))
|
||||
if (max_port_a_size >= 0 && cell->type != TW($shiftx))
|
||||
run_reduce_inport(cell, 'A', max_port_a_size, port_a_signed, did_something);
|
||||
|
||||
if (max_port_b_size >= 0)
|
||||
|
|
@ -369,7 +369,7 @@ struct WreduceWorker
|
|||
if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0 &&
|
||||
GetSize(sig_b) > 0 && sig_b[GetSize(sig_b)-1] == State::S0) {
|
||||
log("Converting cell %s.%s (%s) from signed to unsigned.\n",
|
||||
module, cell, cell->type.unescape());
|
||||
module, cell, cell->type.unescaped());
|
||||
cell->setParam(ID::A_SIGNED, 0);
|
||||
cell->setParam(ID::B_SIGNED, 0);
|
||||
port_a_signed = false;
|
||||
|
|
@ -382,7 +382,7 @@ struct WreduceWorker
|
|||
SigSpec sig_a = mi.sigmap(cell->getPort(TW::A));
|
||||
if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0) {
|
||||
log("Converting cell %s.%s (%s) from signed to unsigned.\n",
|
||||
module, cell, cell->type.unescape());
|
||||
module, cell, cell->type.unescaped());
|
||||
cell->setParam(ID::A_SIGNED, 0);
|
||||
port_a_signed = false;
|
||||
did_something = true;
|
||||
|
|
@ -393,7 +393,7 @@ struct WreduceWorker
|
|||
// Reduce size of port Y based on sizes for A and B and unused bits in Y
|
||||
|
||||
int bits_removed = 0;
|
||||
if (port_a_signed && cell->type == ID($shr)) {
|
||||
if (port_a_signed && cell->type == TW($shr)) {
|
||||
// do not reduce size of output on $shr cells with signed A inputs
|
||||
} else {
|
||||
while (GetSize(sig) > 0)
|
||||
|
|
@ -411,9 +411,9 @@ struct WreduceWorker
|
|||
}
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($pos), ID($add), ID($mul), ID($and), ID($or), ID($xor), ID($sub)))
|
||||
if (cell->type.in(TW($pos), TW($add), TW($mul), TW($and), TW($or), TW($xor), TW($sub)))
|
||||
{
|
||||
bool is_signed = cell->getParam(ID::A_SIGNED).as_bool() || cell->type == ID($sub);
|
||||
bool is_signed = cell->getParam(ID::A_SIGNED).as_bool() || cell->type == TW($sub);
|
||||
|
||||
int a_size = 0, b_size = 0;
|
||||
if (cell->hasPort(TW::A)) a_size = GetSize(cell->getPort(TW::A));
|
||||
|
|
@ -421,10 +421,10 @@ struct WreduceWorker
|
|||
|
||||
int max_y_size = max(a_size, b_size);
|
||||
|
||||
if (cell->type.in(ID($add), ID($sub)))
|
||||
if (cell->type.in(TW($add), TW($sub)))
|
||||
max_y_size++;
|
||||
|
||||
if (cell->type == ID($mul))
|
||||
if (cell->type == TW($mul))
|
||||
max_y_size = a_size + b_size;
|
||||
|
||||
max_y_size = std::max(max_y_size, 1);
|
||||
|
|
@ -441,14 +441,14 @@ struct WreduceWorker
|
|||
}
|
||||
|
||||
if (GetSize(sig) == 0) {
|
||||
log("Removed cell %s.%s (%s).\n", module, cell, cell->type.unescape());
|
||||
log("Removed cell %s.%s (%s).\n", module, cell, cell->type.unescaped());
|
||||
module->remove(cell);
|
||||
return;
|
||||
}
|
||||
|
||||
if (bits_removed) {
|
||||
log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n",
|
||||
bits_removed, GetSize(sig) + bits_removed, module, cell, cell->type.unescape());
|
||||
bits_removed, GetSize(sig) + bits_removed, module, cell, cell->type.unescaped());
|
||||
cell->setPort(TW::Y, sig);
|
||||
did_something = true;
|
||||
}
|
||||
|
|
@ -591,9 +591,9 @@ struct WreducePass : public Pass {
|
|||
|
||||
for (auto c : module->selected_cells())
|
||||
{
|
||||
if (c->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
|
||||
ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),
|
||||
ID($logic_not), ID($logic_and), ID($logic_or)) && GetSize(c->getPort(TW::Y)) > 1) {
|
||||
if (c->type.in(TW($reduce_and), TW($reduce_or), TW($reduce_xor), TW($reduce_xnor), TW($reduce_bool),
|
||||
TW($lt), TW($le), TW($eq), TW($ne), TW($eqx), TW($nex), TW($ge), TW($gt),
|
||||
TW($logic_not), TW($logic_and), TW($logic_or)) && GetSize(c->getPort(TW::Y)) > 1) {
|
||||
SigSpec sig = c->getPort(TW::Y);
|
||||
if (!sig.has_const()) {
|
||||
c->setPort(TW::Y, sig[0]);
|
||||
|
|
@ -603,7 +603,7 @@ struct WreducePass : public Pass {
|
|||
}
|
||||
}
|
||||
|
||||
if (c->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow)))
|
||||
if (c->type.in(TW($div), TW($mod), TW($divfloor), TW($modfloor), TW($pow)))
|
||||
{
|
||||
SigSpec A = c->getPort(TW::A);
|
||||
int original_a_width = GetSize(A);
|
||||
|
|
@ -616,7 +616,7 @@ struct WreducePass : public Pass {
|
|||
}
|
||||
if (original_a_width != GetSize(A)) {
|
||||
log("Removed top %d bits (of %d) from port A of cell %s.%s (%s).\n",
|
||||
original_a_width-GetSize(A), original_a_width, module, c, c->type.unescape());
|
||||
original_a_width-GetSize(A), original_a_width, module, c, design->twines.unescaped_str(c->type));
|
||||
c->setPort(TW::A, A);
|
||||
c->setParam(ID::A_WIDTH, GetSize(A));
|
||||
}
|
||||
|
|
@ -632,13 +632,13 @@ struct WreducePass : public Pass {
|
|||
}
|
||||
if (original_b_width != GetSize(B)) {
|
||||
log("Removed top %d bits (of %d) from port B of cell %s.%s (%s).\n",
|
||||
original_b_width-GetSize(B), original_b_width, module, c, c->type.unescape());
|
||||
original_b_width-GetSize(B), original_b_width, module, c, design->twines.unescaped_str(c->type));
|
||||
c->setPort(TW::B, B);
|
||||
c->setParam(ID::B_WIDTH, GetSize(B));
|
||||
}
|
||||
}
|
||||
|
||||
if (!opt_memx && c->type.in(ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2), ID($meminit), ID($meminit_v2))) {
|
||||
if (!opt_memx && c->type.in(TW($memrd), TW($memrd_v2), TW($memwr), TW($memwr_v2), TW($meminit), TW($meminit_v2))) {
|
||||
std::string memid_s = c->getParam(ID::MEMID).decode_string();
|
||||
TwineRef memid = design->twines.add(Twine{memid_s});
|
||||
RTLIL::Memory *mem = module->memories.at(memid);
|
||||
|
|
@ -648,7 +648,7 @@ struct WreducePass : public Pass {
|
|||
if (cur_addrbits > max_addrbits) {
|
||||
log("Removed top %d address bits (of %d) from memory %s port %s.%s (%s).\n",
|
||||
cur_addrbits-max_addrbits, cur_addrbits,
|
||||
c->type == ID($memrd) ? "read" : c->type == ID($memwr) ? "write" : "init",
|
||||
c->type == TW($memrd) ? "read" : c->type == TW($memwr) ? "write" : "init",
|
||||
module, c, memid_s);
|
||||
c->setParam(ID::ABITS, max_addrbits);
|
||||
c->setPort(TW::ADDR, c->getPort(TW::ADDR).extract(0, max_addrbits));
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ void reduce_chain(test_pmgen_pm &pm)
|
|||
if (ud.longest_chain.empty())
|
||||
return;
|
||||
|
||||
log("Found chain of length %d (%s):\n", GetSize(ud.longest_chain), st.first->type.unescape());
|
||||
log("Found chain of length %d (%s):\n", GetSize(ud.longest_chain), design->twines.unescaped_str(st.first->type));
|
||||
|
||||
SigSpec A;
|
||||
SigSpec Y = ud.longest_chain.front().first->getPort(TW::Y);
|
||||
|
|
@ -57,16 +57,16 @@ void reduce_chain(test_pmgen_pm &pm)
|
|||
|
||||
Cell *c;
|
||||
|
||||
if (last_cell->type == ID($_AND_))
|
||||
if (last_cell->type == TW($_AND_))
|
||||
c = pm.module->addReduceAnd(NEW_TWINE, A, Y);
|
||||
else if (last_cell->type == ID($_OR_))
|
||||
else if (last_cell->type == TW($_OR_))
|
||||
c = pm.module->addReduceOr(NEW_TWINE, A, Y);
|
||||
else if (last_cell->type == ID($_XOR_))
|
||||
else if (last_cell->type == TW($_XOR_))
|
||||
c = pm.module->addReduceXor(NEW_TWINE, A, Y);
|
||||
else
|
||||
log_abort();
|
||||
|
||||
log(" -> %s (%s)\n", c, c->type.unescape());
|
||||
log(" -> %s (%s)\n", c, design->twines.unescaped_str(c->type));
|
||||
}
|
||||
|
||||
void reduce_tree(test_pmgen_pm &pm)
|
||||
|
|
@ -81,21 +81,21 @@ void reduce_tree(test_pmgen_pm &pm)
|
|||
SigSpec Y = st.first->getPort(TW::Y);
|
||||
pm.autoremove(st.first);
|
||||
|
||||
log("Found %s tree with %d leaves for %s (%s).\n", st.first->type.unescape(),
|
||||
log("Found %s tree with %d leaves for %s (%s).\n", design->twines.unescaped_str(st.first->type),
|
||||
GetSize(A), log_signal(Y), st.first);
|
||||
|
||||
Cell *c;
|
||||
|
||||
if (st.first->type == ID($_AND_))
|
||||
if (st.first->type == TW($_AND_))
|
||||
c = pm.module->addReduceAnd(NEW_TWINE, A, Y);
|
||||
else if (st.first->type == ID($_OR_))
|
||||
else if (st.first->type == TW($_OR_))
|
||||
c = pm.module->addReduceOr(NEW_TWINE, A, Y);
|
||||
else if (st.first->type == ID($_XOR_))
|
||||
else if (st.first->type == TW($_XOR_))
|
||||
c = pm.module->addReduceXor(NEW_TWINE, A, Y);
|
||||
else
|
||||
log_abort();
|
||||
|
||||
log(" -> %s (%s)\n", c, c->type.unescape());
|
||||
log(" -> %s (%s)\n", c, design->twines.unescaped_str(c->type));
|
||||
}
|
||||
|
||||
void opt_eqpmux(test_pmgen_pm &pm)
|
||||
|
|
@ -113,7 +113,7 @@ void opt_eqpmux(test_pmgen_pm &pm)
|
|||
|
||||
pm.autoremove(st.pmux);
|
||||
Cell *c = pm.module->addMux(NEW_TWINE, NE, EQ, st.eq->getPort(TW::Y), Y);
|
||||
log(" -> %s (%s)\n", c, c->type.unescape());
|
||||
log(" -> %s (%s)\n", c, design->twines.unescaped_str(c->type));
|
||||
}
|
||||
|
||||
struct TestPmgenPass : public Pass {
|
||||
|
|
|
|||
|
|
@ -39,23 +39,23 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref,
|
|||
|
||||
for (auto cell : mod->cells())
|
||||
{
|
||||
if (cell->type == ID($reduce_or) && cell->getPort(TW::Y) == signal)
|
||||
if (cell->type == TW($reduce_or) && cell->getPort(TW::Y) == signal)
|
||||
return check_signal(mod, cell->getPort(TW::A), ref, polarity);
|
||||
|
||||
if (cell->type == ID($reduce_bool) && cell->getPort(TW::Y) == signal)
|
||||
if (cell->type == TW($reduce_bool) && cell->getPort(TW::Y) == signal)
|
||||
return check_signal(mod, cell->getPort(TW::A), ref, polarity);
|
||||
|
||||
if (cell->type == ID($logic_not) && cell->getPort(TW::Y) == signal) {
|
||||
if (cell->type == TW($logic_not) && cell->getPort(TW::Y) == signal) {
|
||||
polarity = !polarity;
|
||||
return check_signal(mod, cell->getPort(TW::A), ref, polarity);
|
||||
}
|
||||
|
||||
if (cell->type == ID($not) && cell->getPort(TW::Y) == signal) {
|
||||
if (cell->type == TW($not) && cell->getPort(TW::Y) == signal) {
|
||||
polarity = !polarity;
|
||||
return check_signal(mod, cell->getPort(TW::A), ref, polarity);
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($eq), ID($eqx)) && cell->getPort(TW::Y) == signal) {
|
||||
if (cell->type.in(TW($eq), TW($eqx)) && cell->getPort(TW::Y) == signal) {
|
||||
if (cell->getPort(TW::A).is_fully_const()) {
|
||||
if (!cell->getPort(TW::A).as_bool())
|
||||
polarity = !polarity;
|
||||
|
|
@ -68,7 +68,7 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref,
|
|||
}
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($ne), ID($nex)) && cell->getPort(TW::Y) == signal) {
|
||||
if (cell->type.in(TW($ne), TW($nex)) && cell->getPort(TW::Y) == signal) {
|
||||
if (cell->getPort(TW::A).is_fully_const()) {
|
||||
if (cell->getPort(TW::A).as_bool())
|
||||
polarity = !polarity;
|
||||
|
|
@ -215,7 +215,7 @@ void proc_arst(RTLIL::Module *mod, RTLIL::Process *proc, SigMap &assign_map)
|
|||
RTLIL::SigSpec en = apply_reset(mod, proc, sync, assign_map, root_sig, polarity, memwr.enable, memwr.enable);
|
||||
if (!en.is_fully_zero()) {
|
||||
log_error("Async reset %s causes memory write to %s.\n",
|
||||
log_signal(sync->signal), memwr.memid.unescape());
|
||||
log_signal(sync->signal), design->twines.unescaped_str(memwr.memid));
|
||||
}
|
||||
apply_reset(mod, proc, sync, assign_map, root_sig, polarity, memwr.address, memwr.address);
|
||||
apply_reset(mod, proc, sync, assign_map, root_sig, polarity, memwr.data, memwr.data);
|
||||
|
|
|
|||
|
|
@ -94,7 +94,7 @@ void gen_aldff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set
|
|||
std::stringstream sstr;
|
||||
sstr << "$procdff$" << (autoidx++);
|
||||
|
||||
RTLIL::Cell *cell = mod->addCell(Twine{sstr.str()}, ID($aldff));
|
||||
RTLIL::Cell *cell = mod->addCell(Twine{sstr.str()}, TW($aldff));
|
||||
cell->attributes = proc->attributes;
|
||||
|
||||
cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
|
||||
|
|
@ -116,7 +116,7 @@ void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RT
|
|||
std::stringstream sstr;
|
||||
sstr << "$procdff$" << (autoidx++);
|
||||
|
||||
RTLIL::Cell *cell = mod->addCell(Twine{sstr.str()}, clk.empty() ? ID($ff) : arst ? ID($adff) : ID($dff));
|
||||
RTLIL::Cell *cell = mod->addCell(Twine{sstr.str()}, clk.empty() ? TW($ff) : arst ? TW($adff) : TW($dff));
|
||||
cell->attributes = proc->attributes;
|
||||
|
||||
cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@ struct proc_dlatch_db_t
|
|||
|
||||
for (auto cell : module->cells())
|
||||
{
|
||||
if (cell->type.in(ID($mux), ID($pmux), ID($bwmux)))
|
||||
if (cell->type.in(TW($mux), TW($pmux), TW($bwmux)))
|
||||
{
|
||||
auto sig_y = sigmap(cell->getPort(TW::Y));
|
||||
for (int i = 0; i < GetSize(sig_y); i++)
|
||||
|
|
@ -185,8 +185,8 @@ struct proc_dlatch_db_t
|
|||
Cell *cell = it->second.first;
|
||||
int index = it->second.second;
|
||||
|
||||
log_assert(cell->type.in(ID($mux), ID($pmux), ID($bwmux)));
|
||||
bool is_bwmux = (cell->type == ID($bwmux));
|
||||
log_assert(cell->type.in(TW($mux), TW($pmux), TW($bwmux)));
|
||||
bool is_bwmux = (cell->type == TW($bwmux));
|
||||
SigSpec sig_a = sigmap(cell->getPort(TW::A));
|
||||
SigSpec sig_b = sigmap(cell->getPort(TW::B));
|
||||
SigSpec sig_s = sigmap(cell->getPort(TW::S));
|
||||
|
|
@ -328,7 +328,7 @@ struct proc_dlatch_db_t
|
|||
pool<Cell*> next_queue;
|
||||
|
||||
for (auto cell : queue) {
|
||||
if (cell->type.in(ID($mux), ID($pmux)))
|
||||
if (cell->type.in(TW($mux), TW($pmux)))
|
||||
fixup_mux(cell);
|
||||
for (auto bit : upstream_cell2net[cell])
|
||||
for (auto cell : upstream_net2cell[bit])
|
||||
|
|
@ -338,7 +338,7 @@ struct proc_dlatch_db_t
|
|||
|
||||
queue.clear();
|
||||
for (auto cell : next_queue) {
|
||||
if (!visited.count(cell) && ct.cell_known(cell->type))
|
||||
if (!visited.count(cell) && ct.cell_known(cell->type_impl))
|
||||
queue.insert(cell);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ void proc_memwr(RTLIL::Module *mod, RTLIL::Process *proc, dict<IdString, int> &n
|
|||
priority_mask.set(prev_port_ids[i], State::S1);
|
||||
prev_port_ids.push_back(port_id);
|
||||
|
||||
RTLIL::Cell *cell = mod->addCell(NEW_TWINE, ID($memwr_v2));
|
||||
RTLIL::Cell *cell = mod->addCell(NEW_TWINE, TW($memwr_v2));
|
||||
cell->attributes = memwr.attributes;
|
||||
cell->setParam(ID::MEMID, Const(memwr.memid.str()));
|
||||
cell->setParam(ID::ABITS, GetSize(memwr.address));
|
||||
|
|
@ -102,8 +102,8 @@ struct ProcMemWrPass : public Pass {
|
|||
for (auto mod : design->all_selected_modules()) {
|
||||
dict<IdString, int> next_port_id;
|
||||
for (auto cell : mod->cells()) {
|
||||
if (cell->type.in(ID($memwr), ID($memwr_v2))) {
|
||||
bool is_compat = cell->type == ID($memwr);
|
||||
if (cell->type.in(TW($memwr), TW($memwr_v2))) {
|
||||
bool is_compat = cell->type == TW($memwr);
|
||||
IdString memid = cell->parameters.at(ID::MEMID).decode_string();
|
||||
int port_id = cell->parameters.at(is_compat ? ID::PRIORITY : ID::PORTID).as_int();
|
||||
if (port_id >= next_port_id[memid])
|
||||
|
|
|
|||
|
|
@ -178,7 +178,7 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
|
|||
else
|
||||
{
|
||||
// create compare cell
|
||||
RTLIL::Cell *eq_cell = mod->addCell(Twine{stringf("%s_CMP%d", sstr.str(), cmp_wire->width)}, ifxmode ? ID($eqx) : ID($eq));
|
||||
RTLIL::Cell *eq_cell = mod->addCell(Twine{stringf("%s_CMP%d", sstr.str(), cmp_wire->width)}, ifxmode ? TW($eqx) : TW($eq));
|
||||
apply_attrs(eq_cell, sw, cs);
|
||||
|
||||
eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
|
||||
|
|
@ -204,7 +204,7 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
|
|||
ctrl_wire = mod->addWire(Twine{sstr.str() + "_CTRL"});
|
||||
|
||||
// reduce cmp vector to one logic signal
|
||||
RTLIL::Cell *any_cell = mod->addCell(Twine{sstr.str() + "_ANY"}, ID($reduce_or));
|
||||
RTLIL::Cell *any_cell = mod->addCell(Twine{sstr.str() + "_ANY"}, TW($reduce_or));
|
||||
apply_attrs(any_cell, sw, cs);
|
||||
|
||||
any_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
|
||||
|
|
@ -239,7 +239,7 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
|
|||
RTLIL::Wire *result_wire = mod->addWire(Twine{sstr.str() + "_Y"}, when_signal.size());
|
||||
|
||||
// create the multiplexer itself
|
||||
RTLIL::Cell *mux_cell = mod->addCell(Twine{sstr.str()}, ID($mux));
|
||||
RTLIL::Cell *mux_cell = mod->addCell(Twine{sstr.str()}, TW($mux));
|
||||
apply_attrs(mux_cell, sw, cs);
|
||||
|
||||
mux_cell->parameters[ID::WIDTH] = RTLIL::Const(when_signal.size());
|
||||
|
|
|
|||
|
|
@ -54,10 +54,10 @@ struct AssertpmuxWorker
|
|||
|
||||
for (auto cell : module->cells())
|
||||
{
|
||||
if (cell->type.in(ID($mux), ID($pmux)))
|
||||
if (cell->type.in(TW($mux), TW($pmux)))
|
||||
{
|
||||
int width = cell->getParam(ID::WIDTH).as_int();
|
||||
int numports = cell->type == ID($mux) ? 2 : cell->getParam(ID::S_WIDTH).as_int() + 1;
|
||||
int numports = cell->type == TW($mux) ? 2 : cell->getParam(ID::S_WIDTH).as_int() + 1;
|
||||
|
||||
SigSpec sig_a = sigmap(cell->getPort(TW::A));
|
||||
SigSpec sig_b = sigmap(cell->getPort(TW::B));
|
||||
|
|
@ -234,7 +234,7 @@ struct AssertpmuxPass : public Pass {
|
|||
vector<Cell*> pmux_cells;
|
||||
|
||||
for (auto cell : module->selected_cells())
|
||||
if (cell->type == ID($pmux))
|
||||
if (cell->type == TW($pmux))
|
||||
pmux_cells.push_back(cell);
|
||||
|
||||
for (auto cell : pmux_cells)
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
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Add table
Add a link
Reference in a new issue