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Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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kernel/yosys.cc
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@ -964,7 +964,7 @@ static char *readline_obj_generator(const char *text, int state)
RTLIL::Module *module = design->module(design->selected_active_module);
for (auto w : module->wires())
if (w->name.unescape().compare(0, len, text) == 0)
if (design->twines.unescaped_str(w->meta_->name).compare(0, len, text) == 0)
obj_names.push_back(strdup(w->name.unescape().c_str()));
for (auto &it : module->memories) {