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This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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26
kernel/timinginfo.h
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@ -29,15 +29,15 @@ struct TimingInfo
{
struct NameBit
{
RTLIL::IdString name;
TwineRef name;
int offset;
NameBit() : offset(0) {}
NameBit(const RTLIL::IdString name, int offset) : name(name), offset(offset) {}
explicit NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {}
NameBit(TwineRef name, int offset) : name(name), offset(offset) {}
explicit NameBit(const RTLIL::SigBit &b) : name(b.wire->meta_->name), offset(b.offset) {}
bool operator==(const NameBit& nb) const { return nb.name == name && nb.offset == offset; }
bool operator!=(const NameBit& nb) const { return !operator==(nb); }
std::optional<SigBit> get_connection(RTLIL::Cell *cell) {
TwineRef port_name = cell->module->design->twines.lookup(name.str());
TwineRef port_name = name;
if (!cell->hasPort(port_name))
return {};
auto &port = cell->getPort(port_name);
@ -71,7 +71,7 @@ struct TimingInfo
bool has_inputs;
};
dict<RTLIL::IdString, ModuleTiming> data;
dict<TwineRef, ModuleTiming> data;
TimingInfo()
{
@ -93,12 +93,12 @@ struct TimingInfo
const ModuleTiming& setup_module(RTLIL::Module *module)
{
auto r = data.insert(RTLIL::IdString(module->design->twines.str(module->meta_->name)));
auto r = data.insert(module->meta_->name);
log_assert(r.second);
auto &t = r.first->second;
for (auto cell : module->cells()) {
if (cell->type == ID($specify2)) {
if (cell->type == TW($specify2)) {
auto en = cell->getPort(TW::EN);
if (en.is_fully_const() && !en.as_bool())
continue;
@ -136,7 +136,7 @@ struct TimingInfo
}
}
}
else if (cell->type == ID($specify3)) {
else if (cell->type == TW($specify3)) {
auto src = cell->getPort(TW::SRC).as_bit();
auto dst = cell->getPort(TW::DST);
if (!src.wire || !src.wire->port_input)
@ -160,9 +160,9 @@ struct TimingInfo
}
}
}
else if (cell->type == ID($specrule)) {
else if (cell->type == TW($specrule)) {
IdString type = cell->getParam(ID::TYPE).decode_string();
if (type != ID($setup) && type != ID($setuphold))
if (type != TW($setup) && type != TW($setuphold))
continue;
auto src = cell->getPort(TW::SRC);
auto dst = cell->getPort(TW::DST).as_bit();
@ -198,10 +198,10 @@ struct TimingInfo
return t;
}
decltype(data)::const_iterator find(RTLIL::IdString module_name) const { return data.find(module_name); }
decltype(data)::const_iterator find(TwineRef module_name) const { return data.find(module_name); }
decltype(data)::const_iterator end() const { return data.end(); }
int count(RTLIL::IdString module_name) const { return data.count(module_name); }
const ModuleTiming& at(RTLIL::IdString module_name) const { return data.at(module_name); }
int count(TwineRef module_name) const { return data.count(module_name); }
const ModuleTiming& at(TwineRef module_name) const { return data.at(module_name); }
};
YOSYS_NAMESPACE_END