mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-18 21:25:47 +00:00
WIP
This commit is contained in:
parent
afdae7b87e
commit
c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
|
|
@ -138,11 +138,11 @@ struct Macc
|
|||
|
||||
void from_cell(RTLIL::Cell *cell)
|
||||
{
|
||||
if (cell->type == ID($macc)) {
|
||||
if (cell->type == TW($macc)) {
|
||||
from_cell_v1(cell);
|
||||
return;
|
||||
}
|
||||
log_assert(cell->type == ID($macc_v2));
|
||||
log_assert(cell->type == TW($macc_v2));
|
||||
|
||||
RTLIL::SigSpec port_a = cell->getPort(TW::A);
|
||||
RTLIL::SigSpec port_b = cell->getPort(TW::B);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue