mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-15 11:45:41 +00:00
WIP
This commit is contained in:
Emil J. Tywoniak
parent
afdae7b87e
commit
c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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@ -67,7 +67,7 @@ const char *fn_to_string(Fn fn) {
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log_error("fn_to_string: unknown Functional::Fn value %d", (int)fn);
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}
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vector<IRInput const*> IR::inputs(IdString kind) const {
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vector<IRInput const*> IR::inputs(TwineRef kind) const {
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vector<IRInput const*> ret;
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for (const auto &[name, input] : _inputs)
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if(input.kind == kind)
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@ -75,7 +75,7 @@ vector<IRInput const*> IR::inputs(IdString kind) const {
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return ret;
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}
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vector<IROutput const*> IR::outputs(IdString kind) const {
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vector<IROutput const*> IR::outputs(TwineRef kind) const {
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vector<IROutput const*> ret;
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for (const auto &[name, output] : _outputs)
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if(output.kind == kind)
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@ -83,7 +83,7 @@ vector<IROutput const*> IR::outputs(IdString kind) const {
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return ret;
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}
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vector<IRState const*> IR::states(IdString kind) const {
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vector<IRState const*> IR::states(TwineRef kind) const {
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vector<IRState const*> ret;
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for (const auto &[name, state] : _states)
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if(state.kind == kind)
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@ -136,7 +136,7 @@ struct PrintVisitor : DefaultVisitor<std::string> {
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std::string Node::to_string()
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{
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return to_string([](Node n) { return n.name().unescape(); });
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return to_string([](Node n) { return design->twines.unescaped_str(n.name()); });
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}
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std::string Node::to_string(std::function<std::string(Node)> np)
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@ -253,87 +253,87 @@ public:
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int y_width = parameters.at(ID(Y_WIDTH), Const(-1)).as_int();
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bool a_signed = parameters.at(ID(A_SIGNED), Const(0)).as_bool();
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bool b_signed = parameters.at(ID(B_SIGNED), Const(0)).as_bool();
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if(cellType.in(ID($add), ID($sub), ID($and), ID($or), ID($xor), ID($xnor), ID($mul))){
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if(cellType.in(TW($add), TW($sub), TW($and), TW($or), TW($xor), TW($xnor), TW($mul))){
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bool is_signed = a_signed && b_signed;
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Node a = factory.extend(inputs.at(TW::A), y_width, is_signed);
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Node b = factory.extend(inputs.at(TW::B), y_width, is_signed);
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if(cellType == ID($add))
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if(cellType == TW($add))
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return factory.add(a, b);
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else if(cellType == ID($sub))
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else if(cellType == TW($sub))
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return factory.sub(a, b);
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else if(cellType == ID($mul))
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else if(cellType == TW($mul))
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return factory.mul(a, b);
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else if(cellType == ID($and))
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else if(cellType == TW($and))
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return factory.bitwise_and(a, b);
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else if(cellType == ID($or))
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else if(cellType == TW($or))
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return factory.bitwise_or(a, b);
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else if(cellType == ID($xor))
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else if(cellType == TW($xor))
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return factory.bitwise_xor(a, b);
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else if(cellType == ID($xnor))
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else if(cellType == TW($xnor))
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return factory.bitwise_not(factory.bitwise_xor(a, b));
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else
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log_abort();
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}else if(cellType.in(ID($eq), ID($ne), ID($eqx), ID($nex), ID($le), ID($lt), ID($ge), ID($gt))){
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}else if(cellType.in(TW($eq), TW($ne), TW($eqx), TW($nex), TW($le), TW($lt), TW($ge), TW($gt))){
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bool is_signed = a_signed && b_signed;
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int width = max(a_width, b_width);
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Node a = factory.extend(inputs.at(TW::A), width, is_signed);
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Node b = factory.extend(inputs.at(TW::B), width, is_signed);
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if(cellType.in(ID($eq), ID($eqx)))
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if(cellType.in(TW($eq), TW($eqx)))
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return factory.extend(factory.equal(a, b), y_width, false);
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else if(cellType.in(ID($ne), ID($nex)))
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else if(cellType.in(TW($ne), TW($nex)))
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return factory.extend(factory.not_equal(a, b), y_width, false);
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else if(cellType == ID($lt))
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else if(cellType == TW($lt))
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return factory.extend(is_signed ? factory.signed_greater_than(b, a) : factory.unsigned_greater_than(b, a), y_width, false);
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else if(cellType == ID($le))
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else if(cellType == TW($le))
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return factory.extend(is_signed ? factory.signed_greater_equal(b, a) : factory.unsigned_greater_equal(b, a), y_width, false);
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else if(cellType == ID($gt))
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else if(cellType == TW($gt))
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return factory.extend(is_signed ? factory.signed_greater_than(a, b) : factory.unsigned_greater_than(a, b), y_width, false);
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else if(cellType == ID($ge))
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else if(cellType == TW($ge))
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return factory.extend(is_signed ? factory.signed_greater_equal(a, b) : factory.unsigned_greater_equal(a, b), y_width, false);
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else
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log_abort();
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}else if(cellType.in(ID($logic_or), ID($logic_and))){
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}else if(cellType.in(TW($logic_or), TW($logic_and))){
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Node a = factory.reduce_or(inputs.at(TW::A));
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Node b = factory.reduce_or(inputs.at(TW::B));
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Node y = cellType == ID($logic_and) ? factory.bitwise_and(a, b) : factory.bitwise_or(a, b);
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Node y = cellType == TW($logic_and) ? factory.bitwise_and(a, b) : factory.bitwise_or(a, b);
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return factory.extend(y, y_width, false);
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}else if(cellType == ID($not)){
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}else if(cellType == TW($not)){
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Node a = factory.extend(inputs.at(TW::A), y_width, a_signed);
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return factory.bitwise_not(a);
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}else if(cellType == ID($pos)){
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}else if(cellType == TW($pos)){
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return factory.extend(inputs.at(TW::A), y_width, a_signed);
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}else if(cellType == ID($neg)){
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}else if(cellType == TW($neg)){
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Node a = factory.extend(inputs.at(TW::A), y_width, a_signed);
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return factory.unary_minus(a);
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}else if(cellType == ID($logic_not)){
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}else if(cellType == TW($logic_not)){
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Node a = factory.reduce_or(inputs.at(TW::A));
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Node y = factory.bitwise_not(a);
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return factory.extend(y, y_width, false);
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}else if(cellType.in(ID($reduce_or), ID($reduce_bool))){
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}else if(cellType.in(TW($reduce_or), TW($reduce_bool))){
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Node a = factory.reduce_or(inputs.at(TW::A));
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return factory.extend(a, y_width, false);
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}else if(cellType == ID($reduce_and)){
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}else if(cellType == TW($reduce_and)){
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Node a = factory.reduce_and(inputs.at(TW::A));
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return factory.extend(a, y_width, false);
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}else if(cellType.in(ID($reduce_xor), ID($reduce_xnor))){
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}else if(cellType.in(TW($reduce_xor), TW($reduce_xnor))){
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Node a = factory.reduce_xor(inputs.at(TW::A));
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Node y = cellType == ID($reduce_xnor) ? factory.bitwise_not(a) : a;
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Node y = cellType == TW($reduce_xnor) ? factory.bitwise_not(a) : a;
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return factory.extend(y, y_width, false);
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}else if(cellType == ID($shl) || cellType == ID($sshl)){
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}else if(cellType == TW($shl) || cellType == TW($sshl)){
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Node a = factory.extend(inputs.at(TW::A), y_width, a_signed);
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Node b = inputs.at(TW::B);
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return logical_shift_left(a, b);
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}else if(cellType == ID($shr) || cellType == ID($sshr)){
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}else if(cellType == TW($shr) || cellType == TW($sshr)){
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int width = max(a_width, y_width);
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Node a = factory.extend(inputs.at(TW::A), width, a_signed);
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Node b = inputs.at(TW::B);
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Node y = a_signed && cellType == ID($sshr) ?
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Node y = a_signed && cellType == TW($sshr) ?
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arithmetic_shift_right(a, b) :
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logical_shift_right(a, b);
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return factory.extend(y, y_width, a_signed);
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}else if(cellType == ID($shiftx) || cellType == ID($shift)){
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}else if(cellType == TW($shiftx) || cellType == TW($shift)){
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int width = max(a_width, y_width);
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Node a = factory.extend(inputs.at(TW::A), width, cellType == ID($shift) && a_signed);
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Node a = factory.extend(inputs.at(TW::A), width, cellType == TW($shift) && a_signed);
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Node b = inputs.at(TW::B);
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Node shr = logical_shift_right(a, b);
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if(b_signed) {
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@ -343,35 +343,35 @@ public:
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} else {
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return factory.extend(shr, y_width, false);
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}
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}else if(cellType == ID($mux)){
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}else if(cellType == TW($mux)){
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return factory.mux(inputs.at(TW::A), inputs.at(TW::B), inputs.at(TW::S));
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}else if(cellType == ID($pmux)){
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}else if(cellType == TW($pmux)){
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return handle_pmux(inputs.at(TW::A), inputs.at(TW::B), inputs.at(TW::S));
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}else if(cellType == ID($concat)){
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}else if(cellType == TW($concat)){
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Node a = inputs.at(TW::A);
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Node b = inputs.at(TW::B);
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return factory.concat(a, b);
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}else if(cellType == ID($slice)){
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}else if(cellType == TW($slice)){
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int offset = parameters.at(ID(OFFSET)).as_int();
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Node a = inputs.at(TW::A);
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return factory.slice(a, offset, y_width);
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}else if(cellType.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
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}else if(cellType.in(TW($div), TW($mod), TW($divfloor), TW($modfloor))) {
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int width = max(a_width, b_width);
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bool is_signed = a_signed && b_signed;
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Node a = factory.extend(inputs.at(TW::A), width, is_signed);
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Node b = factory.extend(inputs.at(TW::B), width, is_signed);
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if(is_signed) {
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if(cellType == ID($div)) {
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if(cellType == TW($div)) {
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// divide absolute values, then flip the sign if input signs differ
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// but extend the width first, to handle the case (most negative value) / (-1)
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Node abs_y = factory.unsigned_div(abs(a), abs(b));
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Node out_sign = factory.not_equal(sign(a), sign(b));
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return neg_if(factory.extend(abs_y, y_width, false), out_sign);
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} else if(cellType == ID($mod)) {
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} else if(cellType == TW($mod)) {
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// similar to division but output sign == divisor sign
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Node abs_y = factory.unsigned_mod(abs(a), abs(b));
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return neg_if(factory.extend(abs_y, y_width, false), sign(a));
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} else if(cellType == ID($divfloor)) {
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} else if(cellType == TW($divfloor)) {
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// if b is negative, flip both signs so that b is positive
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Node b_sign = sign(b);
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Node a1 = neg_if(a, b_sign);
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@ -385,7 +385,7 @@ public:
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Node y1 = factory.unsigned_div(a2, b1);
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Node y2 = factory.extend(y1, y_width, false);
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return factory.mux(y2, factory.bitwise_not(y2), a1_sign);
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} else if(cellType == ID($modfloor)) {
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} else if(cellType == TW($modfloor)) {
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// calculate |a| % |b| and then subtract from |b| if input signs differ and the remainder is non-zero
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Node abs_b = abs(b);
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Node abs_y = factory.unsigned_mod(abs(a), abs_b);
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@ -397,34 +397,34 @@ public:
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} else
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log_error("unhandled cell in CellSimplifier %s\n", cellType);
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} else {
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if(cellType.in(ID($mod), ID($modfloor)))
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if(cellType.in(TW($mod), TW($modfloor)))
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return factory.extend(factory.unsigned_mod(a, b), y_width, false);
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else
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return factory.extend(factory.unsigned_div(a, b), y_width, false);
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}
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} else if(cellType == ID($pow)) {
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} else if(cellType == TW($pow)) {
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return handle_pow(inputs.at(TW::A), inputs.at(TW::B), y_width, a_signed && b_signed);
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} else if (cellType == ID($lut)) {
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} else if (cellType == TW($lut)) {
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int width = parameters.at(ID(WIDTH)).as_int();
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Const lut_table = parameters.at(ID(LUT));
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lut_table.extu(1 << width);
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return handle_bmux(factory.constant(lut_table), inputs.at(TW::A), 0, 1, width);
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} else if (cellType == ID($bwmux)) {
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} else if (cellType == TW($bwmux)) {
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Node a = inputs.at(TW::A);
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Node b = inputs.at(TW::B);
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Node s = inputs.at(TW::S);
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return factory.bitwise_or(
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factory.bitwise_and(a, factory.bitwise_not(s)),
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factory.bitwise_and(b, s));
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} else if (cellType == ID($bweqx)) {
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} else if (cellType == TW($bweqx)) {
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Node a = inputs.at(TW::A);
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Node b = inputs.at(TW::B);
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return factory.bitwise_not(factory.bitwise_xor(a, b));
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} else if(cellType == ID($bmux)) {
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} else if(cellType == TW($bmux)) {
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int width = parameters.at(ID(WIDTH)).as_int();
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int s_width = parameters.at(ID(S_WIDTH)).as_int();
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return handle_bmux(inputs.at(TW::A), inputs.at(TW::S), 0, width, s_width);
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} else if(cellType == ID($demux)) {
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} else if(cellType == TW($demux)) {
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int width = parameters.at(ID(WIDTH)).as_int();
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int s_width = parameters.at(ID(S_WIDTH)).as_int();
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int y_width = width << s_width;
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@ -433,31 +433,31 @@ public:
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Node s = factory.extend(inputs.at(TW::S), b_width, false);
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Node b = factory.mul(s, factory.constant(Const(width, b_width)));
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return factory.logical_shift_left(a, b);
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} else if(cellType == ID($fa)) {
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} else if(cellType == TW($fa)) {
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return handle_fa(inputs.at(TW::A), inputs.at(TW::B), inputs.at(TW::C));
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} else if(cellType == ID($lcu)) {
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} else if(cellType == TW($lcu)) {
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return handle_lcu(inputs.at(TW::P), inputs.at(TW::G), inputs.at(TW::CI));
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} else if(cellType == ID($alu)) {
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} else if(cellType == TW($alu)) {
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return handle_alu(inputs.at(TW::A), inputs.at(TW::B), y_width, a_signed && b_signed, inputs.at(TW::CI), inputs.at(TW::BI));
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} else if(cellType.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) {
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} else if(cellType.in(TW($assert), TW($assume), TW($live), TW($fair), TW($cover))) {
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Node a = factory.mux(factory.constant(Const(State::S1, 1)), inputs.at(TW::A), inputs.at(TW::EN));
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auto &output = factory.add_output(cellName, cellType, Sort(1));
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output.set_value(a);
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return {};
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} else if(cellType.in(ID($anyconst), ID($allconst), ID($anyseq), ID($allseq))) {
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} else if(cellType.in(TW($anyconst), TW($allconst), TW($anyseq), TW($allseq))) {
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int width = parameters.at(ID(WIDTH)).as_int();
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auto &input = factory.add_input(cellName, cellType, Sort(width));
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return factory.value(input);
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} else if(cellType == ID($initstate)) {
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if(factory.ir().has_state(ID($initstate), ID($state)))
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return factory.value(factory.ir().state(ID($initstate)));
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} else if(cellType == TW($initstate)) {
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if(factory.ir().has_state(TW($initstate), TW($state)))
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return factory.value(factory.ir().state(TW($initstate)));
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else {
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auto &state = factory.add_state(ID($initstate), ID($state), Sort(1));
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auto &state = factory.add_state(TW($initstate), TW($state), Sort(1));
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state.set_initial_value(RTLIL::Const(State::S1, 1));
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state.set_next_value(factory.constant(RTLIL::Const(State::S0, 1)));
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return factory.value(state);
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}
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} else if(cellType == ID($check)) {
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} else if(cellType == TW($check)) {
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log_error("The design contains a $check cell `%s'. This is not supported by the functional backend. Call `chformal -lower' to avoid this error.\n", cellName);
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} else {
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log_error("`%s' cells are not supported by the functional backend\n", cellType);
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@ -495,7 +495,7 @@ class FunctionalIRConstruction {
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queue.emplace_back(cell);
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std::optional<Node> rv;
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for(auto const &[name, sigspec] : cell->connections())
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if(driver_map.celltypes.cell_output(cell->type, name)) {
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if(driver_map.celltypes.cell_output(cell->type.ref(), name)) {
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auto node = factory.create_pending(sigspec.size());
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factory.suggest_name(node, cell->name.str() + "$" + cell->module->design->twines.str(name));
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cell_outputs.emplace({cell, name}, node);
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@ -515,17 +515,17 @@ public:
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{
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driver_map.add(module);
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for (auto cell : module->cells()) {
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if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover), ID($check)))
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if (cell->type.in(TW($assert), TW($assume), TW($live), TW($fair), TW($cover), TW($check)))
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queue.emplace_back(cell);
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}
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// we are relying here on unsorted pools iterating last-in-first-out
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for (auto riter = module->ports.rbegin(); riter != module->ports.rend(); ++riter) {
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auto *wire = module->wire(*riter);
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if (wire && wire->port_input) {
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factory.add_input(wire->name, ID($input), Sort(wire->width));
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factory.add_input(wire->name, TW($input), Sort(wire->width));
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}
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if (wire && wire->port_output) {
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auto &output = factory.add_output(wire->name, ID($output), Sort(wire->width));
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auto &output = factory.add_output(wire->name, TW($output), Sort(wire->width));
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output.set_value(enqueue(DriveChunk(DriveChunkWire(wire, 0, wire->width))));
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}
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}
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@ -565,14 +565,14 @@ private:
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// - Since wr port j can only have priority over wr port i if j > i, if we do writes in
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// ascending index order the result will obey the priorty relation.
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vector<Node> read_results;
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auto &state = factory.add_state(mem->cell->name, ID($state), Sort(ceil_log2(mem->size), mem->width));
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auto &state = factory.add_state(mem->cell->name, TW($state), Sort(ceil_log2(mem->size), mem->width));
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||||
state.set_initial_value(MemContents(mem));
|
||||
Node node = factory.value(state);
|
||||
for (size_t i = 0; i < mem->wr_ports.size(); i++) {
|
||||
const auto &wr = mem->wr_ports[i];
|
||||
if (wr.clk_enable)
|
||||
log_error("Write port %zd of memory %s.%s is clocked. This is not supported by the functional backend. "
|
||||
"Call async2sync or clk2fflogic to avoid this error.\n", i, mem->module, mem->memid.unescape());
|
||||
"Call async2sync or clk2fflogic to avoid this error.\n", i, mem->module, design->twines.unescaped_str(mem->memid));
|
||||
Node en = enqueue(driver_map(DriveSpec(wr.en)));
|
||||
Node addr = enqueue(driver_map(DriveSpec(wr.addr)));
|
||||
Node new_data = enqueue(driver_map(DriveSpec(wr.data)));
|
||||
|
|
@ -582,12 +582,12 @@ private:
|
|||
}
|
||||
if (mem->rd_ports.empty())
|
||||
log_error("Memory %s.%s has no read ports. This is not supported by the functional backend. "
|
||||
"Call opt_clean to remove it.", mem->module, mem->memid.unescape());
|
||||
"Call opt_clean to remove it.", mem->module, design->twines.unescaped_str(mem->memid));
|
||||
for (size_t i = 0; i < mem->rd_ports.size(); i++) {
|
||||
const auto &rd = mem->rd_ports[i];
|
||||
if (rd.clk_enable)
|
||||
log_error("Read port %zd of memory %s.%s is clocked. This is not supported by the functional backend. "
|
||||
"Call memory_nordff to avoid this error.\n", i, mem->module, mem->memid.unescape());
|
||||
"Call memory_nordff to avoid this error.\n", i, mem->module, design->twines.unescaped_str(mem->memid));
|
||||
Node addr = enqueue(driver_map(DriveSpec(rd.addr)));
|
||||
read_results.push_back(factory.memory_read(node, addr));
|
||||
}
|
||||
|
|
@ -609,8 +609,8 @@ private:
|
|||
FfData ff(&ff_initvals, cell);
|
||||
if (!ff.has_gclk)
|
||||
log_error("The design contains a %s flip-flop at %s. This is not supported by the functional backend. "
|
||||
"Call async2sync or clk2fflogic to avoid this error.\n", cell->type.unescape(), cell);
|
||||
auto &state = factory.add_state(ff.name, ID($state), Sort(ff.width));
|
||||
"Call async2sync or clk2fflogic to avoid this error.\n", cell->type.unescaped(), cell);
|
||||
auto &state = factory.add_state(ff.name, TW($state), Sort(ff.width));
|
||||
Node q_value = factory.value(state);
|
||||
factory.suggest_name(q_value, ff.name);
|
||||
factory.update_pending(cell_outputs.at({cell, TW::Q}), q_value);
|
||||
|
|
@ -621,9 +621,9 @@ private:
|
|||
TwineRef output_name; // for the single output case
|
||||
int n_outputs = 0;
|
||||
for(auto const &[name, sigspec] : cell->connections()) {
|
||||
if(driver_map.celltypes.cell_input(cell->type, name) && sigspec.size() > 0)
|
||||
if(driver_map.celltypes.cell_input(cell->type.ref(), name) && sigspec.size() > 0)
|
||||
connections.insert({ name, enqueue(DriveChunkPort(cell, {name, sigspec})) });
|
||||
if(driver_map.celltypes.cell_output(cell->type, name)) {
|
||||
if(driver_map.celltypes.cell_output(cell->type.ref(), name)) {
|
||||
output_name = name;
|
||||
n_outputs++;
|
||||
}
|
||||
|
|
@ -677,7 +677,7 @@ public:
|
|||
factory.update_pending(pending, node);
|
||||
} else {
|
||||
DriveSpec driver = driver_map(DriveSpec(wire_chunk));
|
||||
check_undriven(driver, wire_chunk.wire->name.unescape());
|
||||
check_undriven(driver, design->twines.unescaped_str(wire_chunk.wire->name));
|
||||
Node node = enqueue(driver);
|
||||
factory.suggest_name(node, wire_chunk.wire->name);
|
||||
factory.update_pending(pending, node);
|
||||
|
|
@ -690,7 +690,7 @@ public:
|
|||
} else if (chunk.is_port()) {
|
||||
DriveChunkPort port_chunk = chunk.port();
|
||||
if (port_chunk.is_whole()) {
|
||||
if (driver_map.celltypes.cell_output(port_chunk.cell->type, port_chunk.port)) {
|
||||
if (driver_map.celltypes.cell_output(port_chunk.cell->type.ref(), port_chunk.port)) {
|
||||
Node node = enqueue_cell(port_chunk.cell, port_chunk.port);
|
||||
factory.update_pending(pending, node);
|
||||
} else {
|
||||
|
|
@ -745,7 +745,7 @@ void IR::topological_sort() {
|
|||
log_warning("Combinational loop:\n");
|
||||
for (int *i = begin; i != end; ++i) {
|
||||
Node node(_graph[*i]);
|
||||
log("- %s = %s\n", node.name().unescape(), node.to_string());
|
||||
log("- %s = %s\n", design->twines.unescaped_str(node.name()), node.to_string());
|
||||
}
|
||||
log("\n");
|
||||
scc = true;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue