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This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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22
kernel/consteval.h
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@ -49,10 +49,10 @@ struct ConstEval
ct.static_cell_types = StaticCellTypes::Compat::nomem_noff;
for (auto &it : module->cells_) {
if (!ct.cell_known(it.second->type))
if (!ct.cell_known(it.second->type_impl))
continue;
for (auto &it2 : it.second->connections())
if (ct.cell_output(it.second->type, it2.first))
if (ct.cell_output(it.second->type_impl, it2.first))
sig2driver.insert(assign_map(it2.second), it.second);
}
}
@ -93,7 +93,7 @@ struct ConstEval
bool eval(RTLIL::Cell *cell, RTLIL::SigSpec &undef)
{
if (cell->type == ID($lcu))
if (cell->type == TW($lcu))
{
RTLIL::SigSpec sig_p = cell->getPort(TW::P);
RTLIL::SigSpec sig_g = cell->getPort(TW::G);
@ -147,7 +147,7 @@ struct ConstEval
if (cell->hasPort(TW::B))
sig_b = cell->getPort(TW::B);
if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_NMUX_)))
if (cell->type.in(TW($mux), TW($pmux), TW($_MUX_), TW($_NMUX_)))
{
std::vector<RTLIL::SigSpec> y_candidates;
int count_set_s_bits = 0;
@ -176,7 +176,7 @@ struct ConstEval
for (auto &yc : y_candidates) {
if (!eval(yc, undef, cell))
return false;
if (cell->type == ID($_NMUX_))
if (cell->type == TW($_NMUX_))
y_values.push_back(RTLIL::const_not(yc.as_const(), Const(), false, false, GetSize(yc)));
else
y_values.push_back(yc.as_const());
@ -199,7 +199,7 @@ struct ConstEval
else
set(sig_y, y_values.front());
}
else if (cell->type == ID($bmux))
else if (cell->type == TW($bmux))
{
if (!eval(sig_s, undef, cell))
return false;
@ -217,7 +217,7 @@ struct ConstEval
set(sig_y, const_bmux(sig_a.as_const(), sig_s.as_const()));
}
}
else if (cell->type == ID($demux))
else if (cell->type == TW($demux))
{
if (!eval(sig_a, undef, cell))
return false;
@ -229,7 +229,7 @@ struct ConstEval
set(sig_y, const_demux(sig_a.as_const(), sig_s.as_const()));
}
}
else if (cell->type == ID($fa))
else if (cell->type == TW($fa))
{
RTLIL::SigSpec sig_c = cell->getPort(TW::C);
RTLIL::SigSpec sig_x = cell->getPort(TW::X);
@ -258,7 +258,7 @@ struct ConstEval
set(sig_y, val_y);
set(sig_x, val_x);
}
else if (cell->type == ID($alu))
else if (cell->type == TW($alu))
{
bool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();
bool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();
@ -314,7 +314,7 @@ struct ConstEval
}
}
}
else if (cell->type.in(ID($macc), ID($macc_v2)))
else if (cell->type.in(TW($macc), TW($macc_v2)))
{
Macc macc;
macc.from_cell(cell);
@ -336,7 +336,7 @@ struct ConstEval
{
RTLIL::SigSpec sig_c, sig_d;
if (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) {
if (cell->type.in(TW($_AOI3_), TW($_OAI3_), TW($_AOI4_), TW($_OAI4_))) {
if (cell->hasPort(TW::C))
sig_c = cell->getPort(TW::C);
if (cell->hasPort(TW::D))