mirror of
https://github.com/YosysHQ/yosys
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WIP
This commit is contained in:
Emil J. Tywoniak
parent
afdae7b87e
commit
c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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@ -27,6 +27,7 @@
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*/
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#include "kernel/log.h"
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#include "kernel/twine.h"
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#include "kernel/utils.h"
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#include "kernel/binding.h"
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#include "libs/sha1/sha1.h"
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@ -43,13 +44,13 @@ using namespace AST;
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using namespace AST_INTERNAL;
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// helper function for creating RTLIL code for unary operations
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static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
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static RTLIL::SigSpec uniop2rtlil(AstNode *that, TwineRef type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
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{
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IdString name = stringf("%s$%s:%d$%d", type, RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line, autoidx++);
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RTLIL::Cell *cell = current_module->addCell(Twine{name.str()}, type);
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set_src_attr(cell, that);
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RTLIL::Wire *wire = current_module->addWire(Twine{cell->name.str() + "_Y"}, result_width);
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RTLIL::Wire *wire = current_module->addWire(Twine{Twine::Suffix{cell->meta_->name, "_Y"}}, result_width);
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set_src_attr(wire, that);
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wire->is_signed = that->is_signed;
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@ -78,7 +79,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
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}
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IdString name = stringf("$extend$%s:%d$%d", RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line, autoidx++);
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RTLIL::Cell *cell = current_module->addCell(Twine{name.str()}, ID($pos));
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RTLIL::Cell *cell = current_module->addCell(Twine{name.str()}, TW::$pos);
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set_src_attr(cell, that);
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RTLIL::Wire *wire = current_module->addWire(Twine{cell->name.str() + "_Y"}, width);
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@ -102,13 +103,13 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
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}
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// helper function for creating RTLIL code for binary operations
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static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
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static RTLIL::SigSpec binop2rtlil(AstNode *that, TwineRef type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
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{
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IdString name = stringf("%s$%s:%d$%d", type, RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line, autoidx++);
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RTLIL::Cell *cell = current_module->addCell(Twine{name.str()}, type);
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set_src_attr(cell, that);
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RTLIL::Wire *wire = current_module->addWire(Twine{cell->name.str() + "_Y"}, result_width);
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RTLIL::Wire *wire = current_module->addWire(Twine{Twine::Suffix{cell->meta_->name, "_Y"}}, result_width);
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set_src_attr(wire, that);
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wire->is_signed = that->is_signed;
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@ -140,7 +141,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
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std::stringstream sstr;
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sstr << "$ternary$" << RTLIL::encode_filename(*that->location.begin.filename) << ":" << that->location.begin.line << "$" << (autoidx++);
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RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, ID($mux));
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RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, TW::$mux);
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set_src_attr(cell, that);
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RTLIL::Wire *wire = current_module->addWire(Twine{cell->name.str() + "_Y"}, left.size());
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@ -837,7 +838,7 @@ struct AST_INTERNAL::ProcessGenerator
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}
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RTLIL::Const polarity = polarity_builder.build();
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RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, ID($print));
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RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, TW::$print);
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set_src_attr(cell, ast);
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cell->setParam(ID::TRG_WIDTH, triggers.size());
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cell->setParam(ID::TRG_ENABLE, (always->type == AST_INITIAL) || !triggers.empty());
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@ -935,7 +936,7 @@ struct AST_INTERNAL::ProcessGenerator
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}
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RTLIL::Const polarity = polarity_builder.build();
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RTLIL::Cell *cell = current_module->addCell(Twine{cellname.str()}, ID($check));
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RTLIL::Cell *cell = current_module->addCell(Twine{cellname.str()}, TW::$check);
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set_src_attr(cell, ast);
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cell->set_bool_attribute(ID(keep));
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for (auto &attr : ast->attributes) {
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@ -1443,7 +1444,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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// Clifford's Device (http://www.clifford.at/cfun/cliffdev/). In this
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// cases this variable is used to hold the type of the cell that should
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// be instantiated for this type of AST node.
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IdString type_name;
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TwineRef type_name;
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switch (type)
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{
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@ -1735,7 +1736,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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}
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if (GetSize(shift_val) >= 32)
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fake_ast->children[1]->is_signed = true;
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RTLIL::SigSpec sig = binop2rtlil(fake_ast.get(), ID($shiftx), width, fake_ast->children[0]->genRTLIL(), shift_val);
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RTLIL::SigSpec sig = binop2rtlil(fake_ast.get(), TW($shiftx), width, fake_ast->children[0]->genRTLIL(), shift_val);
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return sig;
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} else {
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chunk.width = children[0]->range_left - children[0]->range_right + 1;
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@ -1841,9 +1842,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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input_error("Assignment pattern is only supported for whole unpacked array assignments.\n");
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// generate cells for unary operations: $not, $pos, $neg
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if (0) { case AST_BIT_NOT: type_name = ID($not); }
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if (0) { case AST_POS: type_name = ID($pos); }
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if (0) { case AST_NEG: type_name = ID($neg); }
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if (0) { case AST_BIT_NOT: type_name = TW($not); }
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if (0) { case AST_POS: type_name = TW($pos); }
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if (0) { case AST_NEG: type_name = TW($neg); }
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{
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RTLIL::SigSpec arg = children[0]->genRTLIL(width_hint, sign_hint);
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is_signed = children[0]->is_signed;
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@ -1856,10 +1857,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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}
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// generate cells for binary operations: $and, $or, $xor, $xnor
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if (0) { case AST_BIT_AND: type_name = ID($and); }
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if (0) { case AST_BIT_OR: type_name = ID($or); }
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if (0) { case AST_BIT_XOR: type_name = ID($xor); }
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if (0) { case AST_BIT_XNOR: type_name = ID($xnor); }
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if (0) { case AST_BIT_AND: type_name = TW($and); }
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if (0) { case AST_BIT_OR: type_name = TW($or); }
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if (0) { case AST_BIT_XOR: type_name = TW($xor); }
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if (0) { case AST_BIT_XNOR: type_name = TW($xnor); }
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{
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if (width_hint < 0)
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detectSignWidth(width_hint, sign_hint);
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@ -1873,10 +1874,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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}
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// generate cells for unary operations: $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor
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if (0) { case AST_REDUCE_AND: type_name = ID($reduce_and); }
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if (0) { case AST_REDUCE_OR: type_name = ID($reduce_or); }
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if (0) { case AST_REDUCE_XOR: type_name = ID($reduce_xor); }
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if (0) { case AST_REDUCE_XNOR: type_name = ID($reduce_xnor); }
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if (0) { case AST_REDUCE_AND: type_name = TW($reduce_and); }
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if (0) { case AST_REDUCE_OR: type_name = TW($reduce_or); }
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if (0) { case AST_REDUCE_XOR: type_name = TW($reduce_xor); }
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if (0) { case AST_REDUCE_XNOR: type_name = TW($reduce_xnor); }
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{
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RTLIL::SigSpec arg = children[0]->genRTLIL();
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RTLIL::SigSpec sig = uniop2rtlil(this, type_name, max(width_hint, 1), arg);
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@ -1885,7 +1886,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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// generate cells for unary operations: $reduce_bool
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// (this is actually just an $reduce_or, but for clarity a different cell type is used)
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if (0) { case AST_REDUCE_BOOL: type_name = ID($reduce_bool); }
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if (0) { case AST_REDUCE_BOOL: type_name = TW($reduce_bool); }
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{
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RTLIL::SigSpec arg = children[0]->genRTLIL();
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RTLIL::SigSpec sig = arg.size() > 1 ? uniop2rtlil(this, type_name, max(width_hint, 1), arg) : arg;
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@ -1893,12 +1894,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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}
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// generate cells for binary operations: $shl, $shr, $sshl, $sshr
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if (0) { case AST_SHIFT_LEFT: type_name = ID($shl); }
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if (0) { case AST_SHIFT_RIGHT: type_name = ID($shr); }
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if (0) { case AST_SHIFT_SLEFT: type_name = ID($sshl); }
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if (0) { case AST_SHIFT_SRIGHT: type_name = ID($sshr); }
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if (0) { case AST_SHIFTX: type_name = ID($shiftx); }
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if (0) { case AST_SHIFT: type_name = ID($shift); }
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if (0) { case AST_SHIFT_LEFT: type_name = TW($shl); }
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if (0) { case AST_SHIFT_RIGHT: type_name = TW($shr); }
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if (0) { case AST_SHIFT_SLEFT: type_name = TW($sshl); }
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if (0) { case AST_SHIFT_SRIGHT: type_name = TW($sshr); }
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if (0) { case AST_SHIFTX: type_name = TW($shiftx); }
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if (0) { case AST_SHIFT: type_name = TW($shift); }
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{
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if (width_hint < 0)
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detectSignWidth(width_hint, sign_hint);
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@ -1923,19 +1924,19 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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int width = width_hint > 0 ? width_hint : left.size();
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is_signed = children[0]->is_signed;
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if (!flag_noopt && left.is_fully_const() && left.as_int() == 2 && !right_signed)
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return binop2rtlil(this, ID($shl), width, RTLIL::SigSpec(1, left.size()), right);
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return binop2rtlil(this, ID($pow), width, left, right);
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return binop2rtlil(this, TW($shl), width, RTLIL::SigSpec(1, left.size()), right);
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return binop2rtlil(this, TW($pow), width, left, right);
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}
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// generate cells for binary operations: $lt, $le, $eq, $ne, $ge, $gt
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if (0) { case AST_LT: type_name = ID($lt); }
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if (0) { case AST_LE: type_name = ID($le); }
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if (0) { case AST_EQ: type_name = ID($eq); }
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if (0) { case AST_NE: type_name = ID($ne); }
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if (0) { case AST_EQX: type_name = ID($eqx); }
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if (0) { case AST_NEX: type_name = ID($nex); }
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if (0) { case AST_GE: type_name = ID($ge); }
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if (0) { case AST_GT: type_name = ID($gt); }
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if (0) { case AST_LT: type_name = TW($lt); }
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if (0) { case AST_LE: type_name = TW($le); }
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if (0) { case AST_EQ: type_name = TW($eq); }
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if (0) { case AST_NE: type_name = TW($ne); }
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if (0) { case AST_EQX: type_name = TW($eqx); }
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if (0) { case AST_NEX: type_name = TW($nex); }
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if (0) { case AST_GE: type_name = TW($ge); }
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if (0) { case AST_GT: type_name = TW($gt); }
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{
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int width = max(width_hint, 1);
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width_hint = -1, sign_hint = true;
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@ -1948,11 +1949,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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}
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// generate cells for binary operations: $add, $sub, $mul, $div, $mod
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if (0) { case AST_ADD: type_name = ID($add); }
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if (0) { case AST_SUB: type_name = ID($sub); }
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if (0) { case AST_MUL: type_name = ID($mul); }
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if (0) { case AST_DIV: type_name = ID($div); }
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if (0) { case AST_MOD: type_name = ID($mod); }
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if (0) { case AST_ADD: type_name = TW($add); }
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if (0) { case AST_SUB: type_name = TW($sub); }
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if (0) { case AST_MUL: type_name = TW($mul); }
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if (0) { case AST_DIV: type_name = TW($div); }
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if (0) { case AST_MOD: type_name = TW($mod); }
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{
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if (width_hint < 0)
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detectSignWidth(width_hint, sign_hint);
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@ -1978,8 +1979,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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}
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// generate cells for binary operations: $logic_and, $logic_or
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if (0) { case AST_LOGIC_AND: type_name = ID($logic_and); }
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if (0) { case AST_LOGIC_OR: type_name = ID($logic_or); }
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if (0) { case AST_LOGIC_AND: type_name = TW($logic_and); }
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if (0) { case AST_LOGIC_OR: type_name = TW($logic_or); }
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{
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RTLIL::SigSpec left = children[0]->genRTLIL();
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RTLIL::SigSpec right = children[1]->genRTLIL();
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@ -1990,7 +1991,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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case AST_LOGIC_NOT:
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{
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RTLIL::SigSpec arg = children[0]->genRTLIL();
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return uniop2rtlil(this, ID($logic_not), max(width_hint, 1), arg);
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return uniop2rtlil(this, TW($logic_not), max(width_hint, 1), arg);
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}
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// generate multiplexer for ternary operator (aka ?:-operator)
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@ -2021,7 +2022,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);
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if (cond.size() > 1)
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cond = uniop2rtlil(this, ID($reduce_bool), 1, cond, false);
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cond = uniop2rtlil(this, TW($reduce_bool), 1, cond, false);
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int width = max(val1.size(), val2.size());
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log_assert(is_signed == children[1]->is_signed);
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@ -2043,7 +2044,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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std::stringstream sstr;
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sstr << "$memrd$" << str << "$" << RTLIL::encode_filename(*location.begin.filename) << ":" << location.begin.line << "$" << (autoidx++);
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RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, ID($memrd));
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RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, TW::$memrd);
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set_src_attr(cell, this);
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RTLIL::Wire *wire = current_module->addWire(Twine{cell->name.str() + "_DATA"}, current_module->memories[current_module->design->twines.lookup(str)]->width);
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@ -2083,7 +2084,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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SigSpec en_sig = children[2]->genRTLIL();
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RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, ID($meminit_v2));
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RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, TW::$meminit_v2);
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set_src_attr(cell, this);
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int mem_width, mem_size, addr_bits;
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@ -2133,7 +2134,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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if (GetSize(check) != 1)
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check = current_module->ReduceBool(NEW_TWINE, check);
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RTLIL::Cell *cell = current_module->addCell(Twine{cellname.str()}, ID($check));
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RTLIL::Cell *cell = current_module->addCell(Twine{cellname.str()}, TW::$check);
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set_src_attr(cell, this);
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for (auto &attr : attributes) {
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if (attr.second->type != AST_CONSTANT)
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@ -2185,7 +2186,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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RTLIL::IdString id = str;
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check_unique_id(current_module, id, this, "cell");
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RTLIL::Cell *cell = current_module->addCell(Twine{id.str()}, "");
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RTLIL::Cell *cell = current_module->addCell(Twine{id.str()}, Twine::Null);
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set_src_attr(cell, this);
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for (auto it = children.begin(); it != children.end(); it++) {
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@ -2202,10 +2203,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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const auto* value = child->children[0].get();
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if (value->type == AST_REALVALUE)
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log_file_warning(*location.begin.filename, location.begin.line, "Replacing floating point parameter %s.%s = %f with string.\n",
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cell, paraname.unescape(), value->realvalue);
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cell, design->twines.unescaped_str(paraname), value->realvalue);
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else if (value->type != AST_CONSTANT)
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input_error("Parameter %s.%s with non-constant value!\n",
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cell, paraname.unescape());
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cell, design->twines.unescaped_str(paraname));
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cell->parameters[paraname] = value->asParaConst();
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continue;
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}
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@ -2260,7 +2261,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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input_error("Attribute `%s' with non-constant value.\n", attr.first);
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cell->attributes[attr.first] = attr.second->asAttrConst();
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}
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if (cell->type == ID($specify2)) {
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if (cell->type == TW($specify2)) {
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int src_width = GetSize(cell->getPort(TW::SRC));
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int dst_width = GetSize(cell->getPort(TW::DST));
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bool full = cell->getParam(ID::FULL).as_bool();
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@ -2269,7 +2270,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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cell->setParam(ID::SRC_WIDTH, Const(src_width));
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cell->setParam(ID::DST_WIDTH, Const(dst_width));
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}
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else if (cell->type == ID($specify3)) {
|
||||
else if (cell->type == TW($specify3)) {
|
||||
int dat_width = GetSize(cell->getPort(TW::DAT));
|
||||
int dst_width = GetSize(cell->getPort(TW::DST));
|
||||
if (dat_width != dst_width)
|
||||
|
|
@ -2278,7 +2279,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
cell->setParam(ID::SRC_WIDTH, Const(src_width));
|
||||
cell->setParam(ID::DST_WIDTH, Const(dst_width));
|
||||
}
|
||||
else if (cell->type == ID($specrule)) {
|
||||
else if (cell->type == TW($specrule)) {
|
||||
int src_width = GetSize(cell->getPort(TW::SRC));
|
||||
int dst_width = GetSize(cell->getPort(TW::DST));
|
||||
cell->setParam(ID::SRC_WIDTH, Const(src_width));
|
||||
|
|
@ -2356,7 +2357,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
if (width <= 0)
|
||||
input_error("Failed to detect width of %s!\n", RTLIL::unescape_id(str));
|
||||
|
||||
Cell *cell = current_module->addCell(Twine{myid}, str.substr(1));
|
||||
TwineRef _type = current_module->design->twines.add(Twine{str.substr(1)});
|
||||
Cell *cell = current_module->addCell(Twine{myid}, _type);
|
||||
set_src_attr(cell, this);
|
||||
cell->parameters[ID::WIDTH] = width;
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue