mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-20 06:05:50 +00:00
WIP
This commit is contained in:
Emil J. Tywoniak
parent
afdae7b87e
commit
c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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@ -82,7 +82,7 @@ const char *make_id(IdString id)
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if (namecache.count(id) != 0)
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return namecache.at(id).c_str();
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string new_id = id.unescape();
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string new_id = design->twines.unescaped_str(id);
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for (int i = 0; i < GetSize(new_id); i++)
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{
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@ -599,7 +599,7 @@ struct FirrtlWorker
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string y_id = make_id(cell->name);
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std::string cellFileinfo = getFileinfo(cell);
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if (cell->type.in(ID($not), ID($logic_not), ID($_NOT_), ID($neg), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_bool), ID($reduce_xnor)))
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if (cell->type.in(TW($not), TW($logic_not), TW($_NOT_), TW($neg), TW($reduce_and), TW($reduce_or), TW($reduce_xor), TW($reduce_bool), TW($reduce_xnor)))
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{
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string a_expr = make_expr(cell->getPort(TW::A));
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wire_decls.push_back(stringf("%swire %s: UInt<%d> %s\n", indent, y_id, y_width, cellFileinfo));
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@ -609,29 +609,29 @@ struct FirrtlWorker
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}
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// Don't use the results of logical operations (a single bit) to control padding
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if (!(cell->type.in(ID($eq), ID($eqx), ID($gt), ID($ge), ID($lt), ID($le), ID($ne), ID($nex), ID($reduce_bool), ID($logic_not)) && y_width == 1) ) {
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if (!(cell->type.in(TW($eq), TW($eqx), TW($gt), TW($ge), TW($lt), TW($le), TW($ne), TW($nex), TW($reduce_bool), TW($logic_not)) && y_width == 1) ) {
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a_expr = stringf("pad(%s, %d)", a_expr, y_width);
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}
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// Assume the FIRRTL width is a single bit.
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firrtl_width = 1;
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if (cell->type.in(ID($not), ID($_NOT_))) primop = "not";
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else if (cell->type == ID($neg)) {
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if (cell->type.in(TW($not), TW($_NOT_))) primop = "not";
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else if (cell->type == TW($neg)) {
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primop = "neg";
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firrtl_is_signed = true; // Result of "neg" is signed (an SInt).
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firrtl_width = a_width;
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} else if (cell->type == ID($logic_not)) {
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} else if (cell->type == TW($logic_not)) {
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primop = "eq";
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a_expr = stringf("%s, UInt(0)", a_expr);
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}
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else if (cell->type == ID($reduce_and)) primop = "andr";
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else if (cell->type == ID($reduce_or)) primop = "orr";
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else if (cell->type == ID($reduce_xor)) primop = "xorr";
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else if (cell->type == ID($reduce_xnor)) {
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else if (cell->type == TW($reduce_and)) primop = "andr";
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else if (cell->type == TW($reduce_or)) primop = "orr";
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else if (cell->type == TW($reduce_xor)) primop = "xorr";
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else if (cell->type == TW($reduce_xnor)) {
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primop = "not";
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a_expr = stringf("xorr(%s)", a_expr);
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}
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else if (cell->type == ID($reduce_bool)) {
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else if (cell->type == TW($reduce_bool)) {
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primop = "neq";
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// Use the sign of the a_expr and its width as the type (UInt/SInt) and width of the comparand.
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a_expr = stringf("%s, %cInt<%d>(0)", a_expr, a_signed ? 'S' : 'U', a_width);
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@ -647,9 +647,9 @@ struct FirrtlWorker
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continue;
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}
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if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($xor), ID($_XOR_), ID($xnor), ID($and), ID($_AND_), ID($or), ID($_OR_), ID($eq), ID($eqx),
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ID($gt), ID($ge), ID($lt), ID($le), ID($ne), ID($nex), ID($shr), ID($sshr), ID($sshl), ID($shl),
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ID($logic_and), ID($logic_or), ID($pow)))
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if (cell->type.in(TW($add), TW($sub), TW($mul), TW($div), TW($mod), TW($xor), TW($_XOR_), TW($xnor), TW($and), TW($_AND_), TW($or), TW($_OR_), TW($eq), TW($eqx),
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TW($gt), TW($ge), TW($lt), TW($le), TW($ne), TW($nex), TW($shr), TW($sshr), TW($sshl), TW($shl),
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TW($logic_and), TW($logic_or), TW($pow)))
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{
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string a_expr = make_expr(cell->getPort(TW::A));
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string b_expr = make_expr(cell->getPort(TW::B));
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@ -666,7 +666,7 @@ struct FirrtlWorker
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}
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// Shift amount is always unsigned, and needn't be padded to result width,
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// otherwise, we need to cast the b_expr appropriately
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if (b_signed && !cell->type.in(ID($shr), ID($sshr), ID($shl), ID($sshl), ID($pow))) {
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if (b_signed && !cell->type.in(TW($shr), TW($sshr), TW($shl), TW($sshl), TW($pow))) {
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b_expr = "asSInt(" + b_expr + ")";
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// Expand the "B" operand to the result width
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if (b_width < y_width) {
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@ -677,7 +677,7 @@ struct FirrtlWorker
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// For the arithmetic ops, expand operand widths to result widths befor performing the operation.
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// This corresponds (according to iverilog) to what verilog compilers implement.
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if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($xor), ID($_XOR_), ID($xnor), ID($and), ID($_AND_), ID($or), ID($_OR_)))
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if (cell->type.in(TW($add), TW($sub), TW($mul), TW($div), TW($mod), TW($xor), TW($_XOR_), TW($xnor), TW($and), TW($_AND_), TW($or), TW($_OR_)))
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{
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if (a_width < y_width) {
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a_expr = stringf("pad(%s, %d)", a_expr, y_width);
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@ -692,79 +692,79 @@ struct FirrtlWorker
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firrtl_width = a_width;
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auto a_sig = cell->getPort(TW::A);
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if (cell->type == ID($add)) {
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if (cell->type == TW($add)) {
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primop = "add";
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firrtl_is_signed = a_signed | b_signed;
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firrtl_width = max(a_width, b_width);
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} else if (cell->type == ID($sub)) {
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} else if (cell->type == TW($sub)) {
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primop = "sub";
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firrtl_is_signed = true;
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int a_widthInc = (!a_signed && b_signed) ? 2 : (a_signed && !b_signed) ? 1 : 0;
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int b_widthInc = (a_signed && !b_signed) ? 2 : (!a_signed && b_signed) ? 1 : 0;
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firrtl_width = max(a_width + a_widthInc, b_width + b_widthInc);
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} else if (cell->type == ID($mul)) {
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} else if (cell->type == TW($mul)) {
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primop = "mul";
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firrtl_is_signed = a_signed | b_signed;
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firrtl_width = a_width + b_width;
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} else if (cell->type == ID($div)) {
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} else if (cell->type == TW($div)) {
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primop = "div";
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firrtl_is_signed = a_signed | b_signed;
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firrtl_width = a_width;
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} else if (cell->type == ID($mod)) {
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} else if (cell->type == TW($mod)) {
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// "rem" = truncating modulo
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primop = "rem";
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firrtl_width = min(a_width, b_width);
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} else if (cell->type.in(ID($and), ID($_AND_))) {
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} else if (cell->type.in(TW($and), TW($_AND_))) {
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primop = "and";
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always_uint = true;
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firrtl_width = max(a_width, b_width);
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}
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else if (cell->type.in(ID($or), ID($_OR_))) {
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else if (cell->type.in(TW($or), TW($_OR_))) {
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primop = "or";
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always_uint = true;
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firrtl_width = max(a_width, b_width);
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}
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else if (cell->type.in(ID($xor), ID($_XOR_))) {
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else if (cell->type.in(TW($xor), TW($_XOR_))) {
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primop = "xor";
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always_uint = true;
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firrtl_width = max(a_width, b_width);
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}
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else if (cell->type == ID($xnor)) {
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else if (cell->type == TW($xnor)) {
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primop = "xnor";
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always_uint = true;
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firrtl_width = max(a_width, b_width);
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}
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else if ((cell->type == ID($eq)) || (cell->type == ID($eqx))) {
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else if ((cell->type == TW($eq)) || (cell->type == TW($eqx))) {
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primop = "eq";
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always_uint = true;
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firrtl_width = 1;
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}
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else if ((cell->type == ID($ne)) || (cell->type == ID($nex))) {
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else if ((cell->type == TW($ne)) || (cell->type == TW($nex))) {
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primop = "neq";
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always_uint = true;
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firrtl_width = 1;
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}
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else if (cell->type == ID($gt)) {
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else if (cell->type == TW($gt)) {
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primop = "gt";
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always_uint = true;
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firrtl_width = 1;
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}
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else if (cell->type == ID($ge)) {
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else if (cell->type == TW($ge)) {
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primop = "geq";
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always_uint = true;
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firrtl_width = 1;
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}
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else if (cell->type == ID($lt)) {
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else if (cell->type == TW($lt)) {
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primop = "lt";
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always_uint = true;
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firrtl_width = 1;
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}
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else if (cell->type == ID($le)) {
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else if (cell->type == TW($le)) {
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primop = "leq";
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always_uint = true;
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firrtl_width = 1;
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}
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else if ((cell->type == ID($shl)) || (cell->type == ID($sshl))) {
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else if ((cell->type == TW($shl)) || (cell->type == TW($sshl))) {
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// FIRRTL will widen the result (y) by the amount of the shift.
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// We'll need to offset this by extracting the un-widened portion as Verilog would do.
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extract_y_bits = true;
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@ -782,7 +782,7 @@ struct FirrtlWorker
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firrtl_width = a_width + (1 << b_width) - 1;
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}
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}
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else if ((cell->type == ID($shr)) || (cell->type == ID($sshr))) {
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else if ((cell->type == TW($shr)) || (cell->type == TW($sshr))) {
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// We don't need to extract a specific range of bits.
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extract_y_bits = false;
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// Is the shift amount constant?
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@ -799,26 +799,26 @@ struct FirrtlWorker
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// We'll need to do some special fixups if the source (and thus result) is signed.
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if (firrtl_is_signed) {
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// If this is a "logical" shift right, pretend the source is unsigned.
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if (cell->type == ID($shr)) {
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if (cell->type == TW($shr)) {
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a_expr = "asUInt(" + a_expr + ")";
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}
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}
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}
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else if ((cell->type == ID($logic_and))) {
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else if ((cell->type == TW($logic_and))) {
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primop = "and";
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a_expr = "neq(" + a_expr + ", UInt(0))";
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b_expr = "neq(" + b_expr + ", UInt(0))";
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always_uint = true;
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firrtl_width = 1;
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}
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else if ((cell->type == ID($logic_or))) {
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else if ((cell->type == TW($logic_or))) {
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primop = "or";
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a_expr = "neq(" + a_expr + ", UInt(0))";
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b_expr = "neq(" + b_expr + ", UInt(0))";
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always_uint = true;
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firrtl_width = 1;
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}
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else if ((cell->type == ID($pow))) {
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else if ((cell->type == TW($pow))) {
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if (a_sig.is_fully_const() && a_sig.as_int() == 2) {
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// We'll convert this to a shift. To simplify things, change the a_expr to "1"
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// so we can use b_expr directly as a shift amount.
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@ -878,7 +878,7 @@ struct FirrtlWorker
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continue;
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}
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if (cell->type.in(ID($mux), ID($_MUX_)))
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if (cell->type.in(TW($mux), TW($_MUX_)))
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{
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auto it = cell->parameters.find(ID::WIDTH);
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int width = it == cell->parameters.end()? 1 : it->second.as_int();
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@ -901,7 +901,7 @@ struct FirrtlWorker
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continue;
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}
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if (cell->type.in(ID($dff)))
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if (cell->type.in(TW($dff)))
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{
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bool clkpol = cell->parameters.at(ID::CLK_POLARITY).as_bool();
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if (clkpol == false)
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@ -919,7 +919,7 @@ struct FirrtlWorker
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continue;
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}
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if (cell->type == ID($shiftx)) {
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if (cell->type == TW($shiftx)) {
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// assign y = a[b +: y_width];
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// We'll extract the correct bits as part of the primop.
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@ -940,7 +940,7 @@ struct FirrtlWorker
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register_reverse_wire_map(y_id, cell->getPort(TW::Y));
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continue;
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}
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if (cell->type == ID($shift)) {
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if (cell->type == TW($shift)) {
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// assign y = a >> b;
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// where b may be negative
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@ -966,7 +966,7 @@ struct FirrtlWorker
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register_reverse_wire_map(y_id, cell->getPort(TW::Y));
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continue;
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}
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if (cell->type == ID($pos)) {
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if (cell->type == TW($pos)) {
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// assign y = a;
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// printCell(cell);
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string a_expr = make_expr(cell->getPort(TW::A));
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@ -981,9 +981,9 @@ struct FirrtlWorker
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continue;
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}
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if (cell->type == ID($scopeinfo))
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if (cell->type == TW($scopeinfo))
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continue;
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log_error("Cell type not supported: %s (%s.%s)\n", cell->type.unescape(), module, cell);
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log_error("Cell type not supported: %s (%s.%s)\n", cell->type.unescaped(), module, cell);
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}
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for (auto &mem : memories) {
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@ -991,10 +991,10 @@ struct FirrtlWorker
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Const init_data = mem.get_init_data();
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if (!init_data.is_fully_undef())
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log_error("Memory with initialization data: %s.%s\n", module, mem.memid.unescape());
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log_error("Memory with initialization data: %s.%s\n", module, design->twines.unescaped_str(mem.memid));
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if (mem.start_offset != 0)
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log_error("Memory with nonzero offset: %s.%s\n", module, mem.memid.unescape());
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log_error("Memory with nonzero offset: %s.%s\n", module, design->twines.unescaped_str(mem.memid));
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for (int i = 0; i < GetSize(mem.rd_ports); i++)
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{
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@ -1002,7 +1002,7 @@ struct FirrtlWorker
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string port_name(stringf("%s.r%d", mem_id, i));
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if (port.clk_enable)
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log_error("Clocked read port %d on memory %s.%s.\n", i, module, mem.memid.unescape());
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log_error("Clocked read port %d on memory %s.%s.\n", i, module, design->twines.unescaped_str(mem.memid));
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std::ostringstream rpe;
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@ -1023,12 +1023,12 @@ struct FirrtlWorker
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string port_name(stringf("%s.w%d", mem_id, i));
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if (!port.clk_enable)
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log_error("Unclocked write port %d on memory %s.%s.\n", i, module, mem.memid.unescape());
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log_error("Unclocked write port %d on memory %s.%s.\n", i, module, design->twines.unescaped_str(mem.memid));
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if (!port.clk_polarity)
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log_error("Negedge write port %d on memory %s.%s.\n", i, module, mem.memid.unescape());
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log_error("Negedge write port %d on memory %s.%s.\n", i, module, design->twines.unescaped_str(mem.memid));
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for (int i = 1; i < GetSize(port.en); i++)
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if (port.en[0] != port.en[i])
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log_error("Complex write enable on port %d on memory %s.%s.\n", i, module, mem.memid.unescape());
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log_error("Complex write enable on port %d on memory %s.%s.\n", i, module, design->twines.unescaped_str(mem.memid));
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std::ostringstream wpe;
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