mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-17 20:55:45 +00:00
WIP
This commit is contained in:
Emil J. Tywoniak
parent
afdae7b87e
commit
c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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@ -119,7 +119,7 @@ struct BtorWorker
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template<typename T>
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string getinfo(T *obj, bool srcsym = false)
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{
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string infostr = obj->name.unescape();
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string infostr = design->twines.unescaped_str(obj->name);
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if (!srcsym && !print_internal_names && infostr[0] == '$') return "";
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if (obj->has_attribute(ID::src)) {
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string src = module && module->design ? module->design->get_src_attribute(obj) : std::string();
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@ -147,7 +147,7 @@ struct BtorWorker
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string getinfo(Mem *mem, bool srcsym = false)
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{
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string infostr = mem->memid.unescape();
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string infostr = design->twines.unescaped_str(mem->memid);
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if (!srcsym && !print_internal_names && infostr[0] == '$') return "";
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if (mem->has_attribute(ID::src)) {
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string src = module && module->design ? module->design->get_src_attribute(mem) : std::string();
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@ -280,24 +280,24 @@ struct BtorWorker
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cell_recursion_guard.insert(cell);
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btorf_push(cell->module->design->twines.str(cell->meta_->name));
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if (cell->type.in(ID($add), ID($sub), ID($mul), ID($and), ID($or), ID($xor), ID($xnor), ID($shl), ID($sshl), ID($shr), ID($sshr), ID($shift), ID($shiftx),
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ID($concat), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_)))
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if (cell->type.in(TW($add), TW($sub), TW($mul), TW($and), TW($or), TW($xor), TW($xnor), TW($shl), TW($sshl), TW($shr), TW($sshr), TW($shift), TW($shiftx),
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TW($concat), TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_), TW($_XOR_), TW($_XNOR_)))
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{
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string btor_op;
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if (cell->type == ID($add)) btor_op = "add";
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if (cell->type == ID($sub)) btor_op = "sub";
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if (cell->type == ID($mul)) btor_op = "mul";
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if (cell->type.in(ID($shl), ID($sshl))) btor_op = "sll";
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if (cell->type == ID($shr)) btor_op = "srl";
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if (cell->type == ID($sshr)) btor_op = "sra";
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if (cell->type.in(ID($shift), ID($shiftx))) btor_op = "shift";
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if (cell->type.in(ID($and), ID($_AND_))) btor_op = "and";
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if (cell->type.in(ID($or), ID($_OR_))) btor_op = "or";
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if (cell->type.in(ID($xor), ID($_XOR_))) btor_op = "xor";
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if (cell->type == ID($concat)) btor_op = "concat";
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if (cell->type == ID($_NAND_)) btor_op = "nand";
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if (cell->type == ID($_NOR_)) btor_op = "nor";
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if (cell->type.in(ID($xnor), ID($_XNOR_))) btor_op = "xnor";
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if (cell->type == TW($add)) btor_op = "add";
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if (cell->type == TW($sub)) btor_op = "sub";
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if (cell->type == TW($mul)) btor_op = "mul";
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if (cell->type.in(TW($shl), TW($sshl))) btor_op = "sll";
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if (cell->type == TW($shr)) btor_op = "srl";
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if (cell->type == TW($sshr)) btor_op = "sra";
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if (cell->type.in(TW($shift), TW($shiftx))) btor_op = "shift";
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if (cell->type.in(TW($and), TW($_AND_))) btor_op = "and";
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if (cell->type.in(TW($or), TW($_OR_))) btor_op = "or";
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if (cell->type.in(TW($xor), TW($_XOR_))) btor_op = "xor";
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if (cell->type == TW($concat)) btor_op = "concat";
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if (cell->type == TW($_NAND_)) btor_op = "nand";
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if (cell->type == TW($_NOR_)) btor_op = "nor";
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if (cell->type.in(TW($xnor), TW($_XNOR_))) btor_op = "xnor";
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log_assert(!btor_op.empty());
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int width_ay = std::max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::Y)));
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@ -309,17 +309,17 @@ struct BtorWorker
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if (btor_op == "shift" && !b_signed)
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btor_op = "srl";
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if (cell->type.in(ID($shl), ID($sshl), ID($shr), ID($sshr)))
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if (cell->type.in(TW($shl), TW($sshl), TW($shr), TW($sshr)))
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b_signed = false;
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if (cell->type == ID($sshr) && !a_signed)
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if (cell->type == TW($sshr) && !a_signed)
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btor_op = "srl";
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int sid = get_bv_sid(width);
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int nid;
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int nid_a;
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if (cell->type.in(ID($shl), ID($shr), ID($shift), ID($shiftx)) && a_signed && width_ay < width) {
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if (cell->type.in(TW($shl), TW($shr), TW($shift), TW($shiftx)) && a_signed && width_ay < width) {
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// sign-extend A up to the width of Y
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int nid_a_padded = get_sig_nid(cell->getPort(TW::A), width_ay, a_signed);
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@ -371,17 +371,17 @@ struct BtorWorker
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goto okay;
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}
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if (cell->type.in(ID($div), ID($mod), ID($modfloor)))
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if (cell->type.in(TW($div), TW($mod), TW($modfloor)))
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{
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bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
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bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
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string btor_op;
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if (cell->type == ID($div)) btor_op = "div";
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if (cell->type == TW($div)) btor_op = "div";
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// "rem" = truncating modulo
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if (cell->type == ID($mod)) btor_op = "rem";
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if (cell->type == TW($mod)) btor_op = "rem";
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// "mod" = flooring modulo
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if (cell->type == ID($modfloor)) {
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if (cell->type == TW($modfloor)) {
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// "umod" doesn't exist because it's the same as "urem"
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btor_op = a_signed || b_signed ? "mod" : "rem";
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}
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@ -411,7 +411,7 @@ struct BtorWorker
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goto okay;
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}
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if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
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if (cell->type.in(TW($_ANDNOT_), TW($_ORNOT_)))
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{
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int sid = get_bv_sid(1);
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int nid_a = get_sig_nid(cell->getPort(TW::A));
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@ -420,12 +420,12 @@ struct BtorWorker
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int nid1 = next_nid++;
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int nid2 = next_nid++;
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if (cell->type == ID($_ANDNOT_)) {
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if (cell->type == TW($_ANDNOT_)) {
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btorf("%d not %d %d\n", nid1, sid, nid_b);
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btorf("%d and %d %d %d%s\n", nid2, sid, nid_a, nid1, getinfo(cell));
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}
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if (cell->type == ID($_ORNOT_)) {
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if (cell->type == TW($_ORNOT_)) {
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btorf("%d not %d %d\n", nid1, sid, nid_b);
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btorf("%d or %d %d %d%s\n", nid2, sid, nid_a, nid1, getinfo(cell));
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}
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@ -435,7 +435,7 @@ struct BtorWorker
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goto okay;
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}
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if (cell->type.in(ID($_OAI3_), ID($_AOI3_)))
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if (cell->type.in(TW($_OAI3_), TW($_AOI3_)))
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{
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int sid = get_bv_sid(1);
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int nid_a = get_sig_nid(cell->getPort(TW::A));
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@ -446,13 +446,13 @@ struct BtorWorker
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int nid2 = next_nid++;
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int nid3 = next_nid++;
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if (cell->type == ID($_OAI3_)) {
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if (cell->type == TW($_OAI3_)) {
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btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
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btorf("%d and %d %d %d\n", nid2, sid, nid1, nid_c);
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btorf("%d not %d %d%s\n", nid3, sid, nid2, getinfo(cell));
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}
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if (cell->type == ID($_AOI3_)) {
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if (cell->type == TW($_AOI3_)) {
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btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
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btorf("%d or %d %d %d\n", nid2, sid, nid1, nid_c);
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btorf("%d not %d %d%s\n", nid3, sid, nid2, getinfo(cell));
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@ -463,7 +463,7 @@ struct BtorWorker
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goto okay;
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}
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if (cell->type.in(ID($_OAI4_), ID($_AOI4_)))
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if (cell->type.in(TW($_OAI4_), TW($_AOI4_)))
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{
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int sid = get_bv_sid(1);
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int nid_a = get_sig_nid(cell->getPort(TW::A));
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@ -476,14 +476,14 @@ struct BtorWorker
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int nid3 = next_nid++;
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int nid4 = next_nid++;
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if (cell->type == ID($_OAI4_)) {
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if (cell->type == TW($_OAI4_)) {
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btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
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btorf("%d or %d %d %d\n", nid2, sid, nid_c, nid_d);
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btorf("%d and %d %d %d\n", nid3, sid, nid1, nid2);
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btorf("%d not %d %d%s\n", nid4, sid, nid3, getinfo(cell));
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}
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if (cell->type == ID($_AOI4_)) {
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if (cell->type == TW($_AOI4_)) {
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btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
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btorf("%d and %d %d %d\n", nid2, sid, nid_c, nid_d);
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btorf("%d or %d %d %d\n", nid3, sid, nid1, nid2);
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@ -495,15 +495,15 @@ struct BtorWorker
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goto okay;
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}
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if (cell->type.in(ID($lt), ID($le), ID($eq), ID($eqx), ID($ne), ID($nex), ID($ge), ID($gt)))
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if (cell->type.in(TW($lt), TW($le), TW($eq), TW($eqx), TW($ne), TW($nex), TW($ge), TW($gt)))
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{
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string btor_op;
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if (cell->type == ID($lt)) btor_op = "lt";
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if (cell->type == ID($le)) btor_op = "lte";
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if (cell->type.in(ID($eq), ID($eqx))) btor_op = "eq";
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if (cell->type.in(ID($ne), ID($nex))) btor_op = "neq";
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if (cell->type == ID($ge)) btor_op = "gte";
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if (cell->type == ID($gt)) btor_op = "gt";
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if (cell->type == TW($lt)) btor_op = "lt";
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if (cell->type == TW($le)) btor_op = "lte";
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if (cell->type.in(TW($eq), TW($eqx))) btor_op = "eq";
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if (cell->type.in(TW($ne), TW($nex))) btor_op = "neq";
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if (cell->type == TW($ge)) btor_op = "gte";
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if (cell->type == TW($gt)) btor_op = "gt";
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log_assert(!btor_op.empty());
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int width = 1;
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@ -518,7 +518,7 @@ struct BtorWorker
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int nid_b = get_sig_nid(cell->getPort(TW::B), width, b_signed);
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int nid = next_nid++;
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if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt))) {
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if (cell->type.in(TW($lt), TW($le), TW($ge), TW($gt))) {
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btorf("%d %c%s %d %d %d%s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op, sid, nid_a, nid_b, getinfo(cell));
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} else {
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btorf("%d %s %d %d %d%s\n", nid, btor_op, sid, nid_a, nid_b, getinfo(cell));
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@ -537,11 +537,11 @@ struct BtorWorker
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goto okay;
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}
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if (cell->type.in(ID($not), ID($neg), ID($_NOT_), ID($pos), ID($buf), ID($_BUF_)))
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if (cell->type.in(TW($not), TW($neg), TW($_NOT_), TW($pos), TW($buf), TW($_BUF_)))
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{
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string btor_op;
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if (cell->type.in(ID($not), ID($_NOT_))) btor_op = "not";
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if (cell->type == ID($neg)) btor_op = "neg";
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if (cell->type.in(TW($not), TW($_NOT_))) btor_op = "not";
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if (cell->type == TW($neg)) btor_op = "neg";
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int width = std::max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::Y)));
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@ -551,7 +551,7 @@ struct BtorWorker
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// the $pos/$buf cells just pass through, all other cells need an actual operation applied
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int nid = nid_a;
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if (!cell->type.in(ID($pos), ID($buf), ID($_BUF_)))
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if (!cell->type.in(TW($pos), TW($buf), TW($_BUF_)))
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{
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log_assert(!btor_op.empty());
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int sid = get_bv_sid(width);
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@ -570,12 +570,12 @@ struct BtorWorker
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goto okay;
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}
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if (cell->type.in(ID($logic_and), ID($logic_or), ID($logic_not)))
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if (cell->type.in(TW($logic_and), TW($logic_or), TW($logic_not)))
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{
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string btor_op;
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if (cell->type == ID($logic_and)) btor_op = "and";
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if (cell->type == ID($logic_or)) btor_op = "or";
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if (cell->type == ID($logic_not)) btor_op = "not";
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if (cell->type == TW($logic_and)) btor_op = "and";
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if (cell->type == TW($logic_or)) btor_op = "or";
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if (cell->type == TW($logic_not)) btor_op = "not";
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log_assert(!btor_op.empty());
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int sid = get_bv_sid(1);
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@ -614,12 +614,12 @@ struct BtorWorker
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goto okay;
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}
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if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($reduce_xor), ID($reduce_xnor)))
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if (cell->type.in(TW($reduce_and), TW($reduce_or), TW($reduce_bool), TW($reduce_xor), TW($reduce_xnor)))
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{
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string btor_op;
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if (cell->type == ID($reduce_and)) btor_op = "redand";
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if (cell->type.in(ID($reduce_or), ID($reduce_bool))) btor_op = "redor";
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if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) btor_op = "redxor";
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if (cell->type == TW($reduce_and)) btor_op = "redand";
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if (cell->type.in(TW($reduce_or), TW($reduce_bool))) btor_op = "redor";
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if (cell->type.in(TW($reduce_xor), TW($reduce_xnor))) btor_op = "redxor";
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log_assert(!btor_op.empty());
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int sid = get_bv_sid(1);
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@ -627,7 +627,7 @@ struct BtorWorker
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int nid = next_nid++;
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if (cell->type == ID($reduce_xnor)) {
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if (cell->type == TW($reduce_xnor)) {
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int nid2 = next_nid++;
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btorf("%d %s %d %d%s\n", nid, btor_op, sid, nid_a, getinfo(cell));
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btorf("%d not %d %d\n", nid2, sid, nid);
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@ -650,7 +650,7 @@ struct BtorWorker
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goto okay;
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}
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if (cell->type.in(ID($mux), ID($_MUX_), ID($_NMUX_)))
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if (cell->type.in(TW($mux), TW($_MUX_), TW($_NMUX_)))
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{
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SigSpec sig_a = sigmap(cell->getPort(TW::A));
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SigSpec sig_b = sigmap(cell->getPort(TW::B));
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@ -664,7 +664,7 @@ struct BtorWorker
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int sid = get_bv_sid(GetSize(sig_y));
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int nid = next_nid++;
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if (cell->type == ID($_NMUX_)) {
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if (cell->type == TW($_NMUX_)) {
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int tmp = nid;
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nid = next_nid++;
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btorf("%d ite %d %d %d %d\n", tmp, sid, nid_s, nid_b, nid_a);
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@ -677,7 +677,7 @@ struct BtorWorker
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goto okay;
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}
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if (cell->type == ID($pmux))
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if (cell->type == TW($pmux))
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{
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SigSpec sig_a = sigmap(cell->getPort(TW::A));
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SigSpec sig_b = sigmap(cell->getPort(TW::B));
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@ -703,21 +703,21 @@ struct BtorWorker
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goto okay;
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}
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if (cell->type.in(ID($dff), ID($ff), ID($anyinit), ID($_DFF_P_), ID($_DFF_N), ID($_FF_)))
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if (cell->type.in(TW($dff), TW($ff), TW($anyinit), TW($_DFF_P_), TW($_DFF_N), TW($_FF_)))
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{
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SigSpec sig_d = sigmap(cell->getPort(TW::D));
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SigSpec sig_q = sigmap(cell->getPort(TW::Q));
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if ((!info_filename.empty() || ywmap_json.active()) && cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_)))
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if ((!info_filename.empty() || ywmap_json.active()) && cell->type.in(TW($dff), TW($_DFF_P_), TW($_DFF_N_)))
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{
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SigSpec sig_c = sigmap(cell->getPort(cell->type == ID($dff) ? TW::CLK : TW::C));
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SigSpec sig_c = sigmap(cell->getPort(cell->type == TW($dff) ? TW::CLK : TW::C));
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int nid = get_sig_nid(sig_c);
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bool negedge = false;
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if (cell->type == ID($_DFF_N_))
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if (cell->type == TW($_DFF_N_))
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negedge = true;
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if (cell->type == ID($dff) && !cell->getParam(ID::CLK_POLARITY).as_bool())
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if (cell->type == TW($dff) && !cell->getParam(ID::CLK_POLARITY).as_bool())
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negedge = true;
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if (!info_filename.empty())
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@ -756,7 +756,7 @@ struct BtorWorker
|
|||
if (symbol.empty() || (!print_internal_names && symbol[0] == '$'))
|
||||
btorf("%d state %d\n", nid, sid);
|
||||
else
|
||||
btorf("%d state %d %s\n", nid, sid, symbol.unescape());
|
||||
btorf("%d state %d %s\n", nid, sid, design->twines.unescaped_str(symbol));
|
||||
|
||||
if (cell->get_bool_attribute(ID(clk2fflogic)))
|
||||
ywmap_state(cell->getPort(TW::D)); // For a clk2fflogic FF the named signal is the D input not the Q output
|
||||
|
|
@ -775,7 +775,7 @@ struct BtorWorker
|
|||
goto okay;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($anyconst), ID($anyseq)))
|
||||
if (cell->type.in(TW($anyconst), TW($anyseq)))
|
||||
{
|
||||
SigSpec sig_y = sigmap(cell->getPort(TW::Y));
|
||||
|
||||
|
|
@ -786,7 +786,7 @@ struct BtorWorker
|
|||
|
||||
ywmap_state(sig_y);
|
||||
|
||||
if (cell->type == ID($anyconst)) {
|
||||
if (cell->type == TW($anyconst)) {
|
||||
int nid2 = next_nid++;
|
||||
btorf("%d next %d %d %d\n", nid2, sid, nid, nid);
|
||||
}
|
||||
|
|
@ -795,7 +795,7 @@ struct BtorWorker
|
|||
goto okay;
|
||||
}
|
||||
|
||||
if (cell->type == ID($initstate))
|
||||
if (cell->type == TW($initstate))
|
||||
{
|
||||
SigSpec sig_y = sigmap(cell->getPort(TW::Y));
|
||||
|
||||
|
|
@ -834,12 +834,12 @@ struct BtorWorker
|
|||
|
||||
if (asyncwr && syncwr)
|
||||
log_error("Memory %s.%s has mixed async/sync write ports.\n",
|
||||
module, mem->memid.unescape());
|
||||
module, design->twines.unescaped_str(mem->memid));
|
||||
|
||||
for (auto &port : mem->rd_ports) {
|
||||
if (port.clk_enable)
|
||||
log_error("Memory %s.%s has sync read ports. Please use memory_nordff to convert them first.\n",
|
||||
module, mem->memid.unescape());
|
||||
module, design->twines.unescaped_str(mem->memid));
|
||||
}
|
||||
|
||||
int data_sid = get_bv_sid(mem->width);
|
||||
|
|
@ -901,7 +901,7 @@ struct BtorWorker
|
|||
if (mem->memid[0] == '$')
|
||||
btorf("%d state %d\n", nid, sid);
|
||||
else
|
||||
btorf("%d state %d %s\n", nid, sid, mem->memid.unescape());
|
||||
btorf("%d state %d %s\n", nid, sid, design->twines.unescaped_str(mem->memid));
|
||||
|
||||
ywmap_state(cell);
|
||||
|
||||
|
|
@ -976,15 +976,15 @@ struct BtorWorker
|
|||
goto okay;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($dffe), ID($sdff), ID($sdffe), ID($sdffce)) || cell->type.str().substr(0, 6) == "$_SDFF" || (cell->type.str().substr(0, 6) == "$_DFFE" && cell->type.str().size() == 10)) {
|
||||
if (cell->type.in(TW($dffe), TW($sdff), TW($sdffe), TW($sdffce)) || cell->type.str().substr(0, 6) == "$_SDFF" || (cell->type.str().substr(0, 6) == "$_DFFE" && cell->type.str().size() == 10)) {
|
||||
log_error("Unsupported cell type %s for cell %s.%s -- please run `dffunmap` before `write_btor`.\n",
|
||||
cell->type.unescape(), module, cell);
|
||||
}
|
||||
if (cell->type.in(ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($dffsr), ID($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF" || cell->type.str().substr(0, 7) == "$_ALDFF") {
|
||||
if (cell->type.in(TW($adff), TW($adffe), TW($aldff), TW($aldffe), TW($dffsr), TW($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF" || cell->type.str().substr(0, 7) == "$_ALDFF") {
|
||||
log_error("Unsupported cell type %s for cell %s.%s -- please run `async2sync; dffunmap` or `clk2fflogic` before `write_btor`.\n",
|
||||
cell->type.unescape(), module, cell);
|
||||
}
|
||||
if (cell->type.in(ID($sr), ID($dlatch), ID($adlatch), ID($dlatchsr)) || cell->type.str().substr(0, 8) == "$_DLATCH" || cell->type.str().substr(0, 5) == "$_SR_") {
|
||||
if (cell->type.in(TW($sr), TW($dlatch), TW($adlatch), TW($dlatchsr)) || cell->type.str().substr(0, 8) == "$_DLATCH" || cell->type.str().substr(0, 5) == "$_SR_") {
|
||||
log_error("Unsupported cell type %s for cell %s.%s -- please run `clk2fflogic` before `write_btor`.\n",
|
||||
cell->type.unescape(), module, cell);
|
||||
}
|
||||
|
|
@ -1296,7 +1296,7 @@ struct BtorWorker
|
|||
|
||||
for (auto cell : module->cells())
|
||||
{
|
||||
if (cell->type == ID($assume))
|
||||
if (cell->type == TW($assume))
|
||||
{
|
||||
btorf_push(cell->module->design->twines.str(cell->meta_->name));
|
||||
|
||||
|
|
@ -1316,7 +1316,7 @@ struct BtorWorker
|
|||
btorf_pop(cell->module->design->twines.str(cell->meta_->name));
|
||||
}
|
||||
|
||||
if (cell->type == ID($assert))
|
||||
if (cell->type == TW($assert))
|
||||
{
|
||||
btorf_push(cell->module->design->twines.str(cell->meta_->name));
|
||||
|
||||
|
|
@ -1345,7 +1345,7 @@ struct BtorWorker
|
|||
btorf_pop(cell->module->design->twines.str(cell->meta_->name));
|
||||
}
|
||||
|
||||
if (cell->type == ID($cover) && cover_mode)
|
||||
if (cell->type == TW($cover) && cover_mode)
|
||||
{
|
||||
btorf_push(cell->module->design->twines.str(cell->meta_->name));
|
||||
|
||||
|
|
@ -1417,7 +1417,7 @@ struct BtorWorker
|
|||
int nid = it.first;
|
||||
Mem *mem = it.second;
|
||||
|
||||
btorf_push(stringf("next %s", mem->memid.unescape()));
|
||||
btorf_push(stringf("next %s", design->twines.unescaped_str(mem->memid)));
|
||||
|
||||
int abits = ceil_log2(mem->size);
|
||||
|
||||
|
|
@ -1465,7 +1465,7 @@ struct BtorWorker
|
|||
int nid2 = next_nid++;
|
||||
btorf("%d next %d %d %d%s\n", nid2, sid, nid, nid_head, getinfo(mem));
|
||||
|
||||
btorf_pop(stringf("next %s", mem->memid.unescape()));
|
||||
btorf_pop(stringf("next %s", design->twines.unescaped_str(mem->memid)));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue