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This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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112
backends/aiger2/aiger.cc
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@ -32,21 +32,21 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
#define BITWISE_OPS ID($buf), ID($not), ID($mux), ID($and), ID($or), ID($xor), ID($xnor), ID($fa), \
ID($bwmux)
#define BITWISE_OPS TW($buf), TW($not), TW($mux), TW($and), TW($or), TW($xor), TW($xnor), TW($fa), \
TW($bwmux)
#define REDUCE_OPS ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool)
#define REDUCE_OPS TW($reduce_and), TW($reduce_or), TW($reduce_xor), TW($reduce_xnor), TW($reduce_bool)
#define LOGIC_OPS ID($logic_and), ID($logic_or), ID($logic_not)
#define LOGIC_OPS TW($logic_and), TW($logic_or), TW($logic_not)
#define GATE_OPS ID($_BUF_), ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), \
ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($_MUX_), ID($_NMUX_), \
ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_)
#define GATE_OPS TW($_BUF_), TW($_NOT_), TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_), \
TW($_XOR_), TW($_XNOR_), TW($_ANDNOT_), TW($_ORNOT_), TW($_MUX_), TW($_NMUX_), \
TW($_AOI3_), TW($_OAI3_), TW($_AOI4_), TW($_OAI4_)
#define CMP_OPS ID($eq), ID($ne), ID($lt), ID($le), ID($ge), ID($gt)
#define CMP_OPS TW($eq), TW($ne), TW($lt), TW($le), TW($ge), TW($gt)
// TODO
//#define ARITH_OPS ID($add), ID($sub), ID($neg)
//#define ARITH_OPS TW($add), TW($sub), TW($neg)
static constexpr auto known_ops = []() constexpr {
StaticCellTypes::Categories::Category c{};
@ -60,7 +60,7 @@ static constexpr auto known_ops = []() constexpr {
c.set_id(id);
for (auto id : {CMP_OPS})
c.set_id(id);
for (auto id : {ID($pos), ID($pmux), ID($bmux)})
for (auto id : {TW($pos), TW($pmux), TW($bmux)})
c.set_id(id);
return c;
}();
@ -109,7 +109,7 @@ struct Index {
int pos = index_wires(info, m);
for (auto cell : m->cells()) {
if (known_ops(cell->type) || cell->type.in(ID($scopeinfo), ID($specify2), ID($specify3), ID($input_port), ID($output_port), ID($public)))
if (known_ops(cell->type) || cell->type.in(TW($scopeinfo), TW($specify2), TW($specify3), TW($input_port), TW($output_port), TW($public)))
continue;
Module *submodule = m->design->module(cell->type);
@ -128,7 +128,7 @@ struct Index {
// can't bail at this point. If they are hit by a traversal
// (which can only really happen with $tribuf not
// $connect), we can still detect this as an error later.
if (cell->type == ID($connect) || (cell->type == ID($tribuf) && cell->has_attribute(ID(aiger2_zbuf))))
if (cell->type == TW($connect) || (cell->type == TW($tribuf) && cell->has_attribute(ID(aiger2_zbuf))))
continue;
if (!submodule || submodule->get_blackbox_attribute())
log_error("Unsupported cell type: %s (%s in %s)\n",
@ -292,18 +292,18 @@ struct Index {
aport.extend_u0(width, asigned);
bport.extend_u0(width, bsigned);
if (cell->type.in(ID($eq), ID($ne))) {
if (cell->type.in(TW($eq), TW($ne))) {
int carry = CTRUE;
for (int i = 0; i < width; i++) {
Lit a = visit(cursor, aport[i]);
Lit b = visit(cursor, bport[i]);
carry = AND(carry, XNOR(a, b));
}
return (cell->type == ID($eq)) ? carry : /* $ne */ NOT(carry);
} else if (cell->type.in(ID($lt), ID($le), ID($gt), ID($ge))) {
if (cell->type.in(ID($gt), ID($ge)))
return (cell->type == TW($eq)) ? carry : /* $ne */ NOT(carry);
} else if (cell->type.in(TW($lt), TW($le), TW($gt), TW($ge))) {
if (cell->type.in(TW($gt), TW($ge)))
std::swap(aport, bport);
int carry = cell->type.in(ID($le), ID($ge)) ? CFALSE : CTRUE;
int carry = cell->type.in(TW($le), TW($ge)) ? CFALSE : CTRUE;
Lit a = Writer::EMPTY_LIT;
Lit b = Writer::EMPTY_LIT;
// TODO: this might not be the most economic structure; revisit at a later date
@ -317,28 +317,28 @@ struct Index {
} else {
log_abort();
}
} else if (cell->type.in(REDUCE_OPS, ID($logic_not))) {
} else if (cell->type.in(REDUCE_OPS, TW($logic_not))) {
SigSpec inport = cell->getPort(TW::A);
std::vector<Lit> lits;
for (int i = 0; i < inport.size(); i++) {
Lit lit = visit(cursor, inport[i]);
if (cell->type.in(ID($reduce_and), ID($reduce_xor), ID($reduce_xnor))) {
if (cell->type.in(TW($reduce_and), TW($reduce_xor), TW($reduce_xnor))) {
lits.push_back(lit);
} else if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not))) {
} else if (cell->type.in(TW($reduce_or), TW($reduce_bool), TW($logic_not))) {
lits.push_back(NOT(lit));
} else {
log_abort();
}
}
Lit acc = REDUCE(lits, cell->type.in(ID($reduce_xor), ID($reduce_xnor)));
Lit acc = REDUCE(lits, cell->type.in(TW($reduce_xor), TW($reduce_xnor)));
if (!cell->type.in(ID($reduce_xnor), ID($reduce_or), ID($reduce_bool)))
if (!cell->type.in(TW($reduce_xnor), TW($reduce_or), TW($reduce_bool)))
return acc;
else
return NOT(acc);
} else if (cell->type.in(ID($logic_and), ID($logic_or))) {
} else if (cell->type.in(TW($logic_and), TW($logic_or))) {
SigSpec aport = cell->getPort(TW::A);
SigSpec bport = cell->getPort(TW::B);
@ -356,13 +356,13 @@ struct Index {
b = OR(b, l);
}
if (cell->type == ID($logic_and))
if (cell->type == TW($logic_and))
return AND(a, b);
else if (cell->type == ID($logic_or))
else if (cell->type == TW($logic_or))
return OR(a, b);
else
log_abort();
} else if (cell->type.in(BITWISE_OPS, GATE_OPS, ID($pos))) {
} else if (cell->type.in(BITWISE_OPS, GATE_OPS, TW($pos))) {
SigSpec aport = cell->getPort(TW::A);
Lit a;
if (obit < aport.size()) {
@ -374,9 +374,9 @@ struct Index {
a = CFALSE;
}
if (cell->type.in(ID($buf), ID($pos), ID($_BUF_))) {
if (cell->type.in(TW($buf), TW($pos), TW($_BUF_))) {
return a;
} else if (cell->type.in(ID($not), ID($_NOT_))) {
} else if (cell->type.in(TW($not), TW($_NOT_))) {
return NOT(a);
} else {
SigSpec bport = cell->getPort(TW::B);
@ -390,32 +390,32 @@ struct Index {
b = CFALSE;
}
if (cell->type.in(ID($and), ID($_AND_))) {
if (cell->type.in(TW($and), TW($_AND_))) {
return AND(a, b);
} else if (cell->type.in(ID($_NAND_))) {
} else if (cell->type.in(TW($_NAND_))) {
return NOT(AND(a, b));
} else if (cell->type.in(ID($or), ID($_OR_))) {
} else if (cell->type.in(TW($or), TW($_OR_))) {
return OR(a, b);
} else if (cell->type.in(ID($_NOR_))) {
} else if (cell->type.in(TW($_NOR_))) {
return NOT(OR(a, b));
} else if (cell->type.in(ID($xor), ID($_XOR_))) {
} else if (cell->type.in(TW($xor), TW($_XOR_))) {
return XOR(a, b);
} else if (cell->type.in(ID($xnor), ID($_XNOR_))) {
} else if (cell->type.in(TW($xnor), TW($_XNOR_))) {
return XNOR(a, b);
} else if (cell->type.in(ID($_ANDNOT_))) {
} else if (cell->type.in(TW($_ANDNOT_))) {
return AND(a, NOT(b));
} else if (cell->type.in(ID($_ORNOT_))) {
} else if (cell->type.in(TW($_ORNOT_))) {
return OR(a, NOT(b));
} else if (cell->type.in(ID($mux), ID($_MUX_))) {
} else if (cell->type.in(TW($mux), TW($_MUX_))) {
Lit s = visit(cursor, cell->getPort(TW::S));
return MUX(a, b, s);
} else if (cell->type.in(ID($bwmux))) {
} else if (cell->type.in(TW($bwmux))) {
Lit s = visit(cursor, cell->getPort(TW::S)[obit]);
return MUX(a, b, s);
} else if (cell->type.in(ID($_NMUX_))) {
} else if (cell->type.in(TW($_NMUX_))) {
Lit s = visit(cursor, cell->getPort(TW::S)[obit]);
return NOT(MUX(a, b, s));
} else if (cell->type.in(ID($fa))) {
} else if (cell->type.in(TW($fa))) {
Lit c = visit(cursor, cell->getPort(TW::C)[obit]);
Lit ab = XOR(a, b);
if (oport == TW::Y) {
@ -425,16 +425,16 @@ struct Index {
Lit c_and_ab = AND(c, ab);
return OR(a_and_b, c_and_ab);
}
} else if (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) {
} else if (cell->type.in(TW($_AOI3_), TW($_OAI3_), TW($_AOI4_), TW($_OAI4_))) {
Lit c, d;
c = visit(cursor, cell->getPort(TW::C)[obit]);
if (/* 4 input types */ cell->type.in(ID($_AOI4_), ID($_OAI4_)))
if (/* 4 input types */ cell->type.in(TW($_AOI4_), TW($_OAI4_)))
d = visit(cursor, cell->getPort(TW::D)[obit]);
else
d = cell->type == ID($_AOI3_) ? CTRUE : CFALSE;
d = cell->type == TW($_AOI3_) ? CTRUE : CFALSE;
if (/* aoi */ cell->type.in(ID($_AOI3_), ID($_AOI4_))) {
if (/* aoi */ cell->type.in(TW($_AOI3_), TW($_AOI4_))) {
Lit a_and_b = AND(a, b);
Lit c_and_d = AND(c, d);
return NOT(OR(a_and_b, c_and_d));
@ -447,7 +447,7 @@ struct Index {
log_abort();
}
}
} else if (cell->type == ID($pmux)) {
} else if (cell->type == TW($pmux)) {
SigSpec aport = cell->getPort(TW::A);
SigSpec bport = cell->getPort(TW::B);
SigSpec sport = cell->getPort(TW::S);
@ -468,7 +468,7 @@ struct Index {
Lit reduce_bar = NOT(REDUCE(bar));
return OR(reduce_sels_and_a, reduce_bar);
} else if (cell->type == ID($bmux)) {
} else if (cell->type == TW($bmux)) {
SigSpec aport = cell->getPort(TW::A);
SigSpec sport = cell->getPort(TW::S);
int width = cell->getParam(ID::WIDTH).as_int();
@ -537,7 +537,7 @@ struct Index {
Design *design = index.design;
auto &minfo = leaf_minfo(index);
if (!minfo.suboffsets.count(cell))
log_error("Reached unsupported cell %s (%s in %s)\n", cell->type.unescape(), cell, cell->module);
log_error("Reached unsupported cell %s (%s in %s)\n", cell->type.unescaped(), cell, cell->module);
Module *def = design->module(cell->type);
log_assert(def);
levels.push_back(Level(index.modules.at(def), cell));
@ -660,7 +660,7 @@ struct Index {
auto &port = instance->getPort(portname);
if (bit.offset >= port.size())
log_error("Bit %d of input port %s on instance %s of %s unconnected\n",
bit.offset, design->twines.str(portname).c_str(), instance, instance->type.unescape());
bit.offset, design->twines.str(portname).c_str(), instance, design->twines.unescaped_str(instance->type));
ret = visit(cursor, port[bit.offset]);
}
cursor.enter(*this, instance);
@ -845,7 +845,7 @@ struct AigerWriter : Index<AigerWriter, unsigned int, 0, 1> {
char buf[32];
snprintf(buf, sizeof(buf), "o%d ", i);
f->write(buf, strlen(buf));
std::string name = bit.wire->name.unescape();
std::string name = design->twines.unescaped_str(bit.wire->name);
f->write(name.data(), name.size());
f->put('\n');
}
@ -858,7 +858,7 @@ struct AigerWriter : Index<AigerWriter, unsigned int, 0, 1> {
char buf[32];
snprintf(buf, sizeof(buf), "i%d ", i);
f->write(buf, strlen(buf));
std::string name = bit.wire->name.unescape();
std::string name = design->twines.unescaped_str(bit.wire->name);
f->write(name.data(), name.size());
f->put('\n');
}
@ -1090,7 +1090,7 @@ struct XAigerWriter : AigerWriter {
for (auto box : minfo.found_blackboxes) {
log_debug(" - %s.%s (type %s): ", cursor.path(),
box,
box->type.unescape());
design->twines.unescaped_str(box->type));
Module *box_module = design->module(box->type), *box_derived;
@ -1159,7 +1159,7 @@ struct XAigerWriter : AigerWriter {
} else {
// FIXME: hierarchical path
log_warning("connection on port %s[%d] of instance %s (type %s) missing, using 1'bx\n",
design->twines.str(port_id).c_str(), i, box, box->type.unescape());
design->twines.str(port_id).c_str(), i, box, design->twines.unescaped_str(box->type));
bit = RTLIL::Sx;
}
@ -1194,7 +1194,7 @@ struct XAigerWriter : AigerWriter {
} else {
// FIXME: hierarchical path
log_warning("connection on port %s[%d] of instance %s (type %s) missing\n",
design->twines.str(port_id).c_str(), i, box, box->type.unescape());
design->twines.str(port_id).c_str(), i, box, design->twines.unescaped_str(box->type));
pad_pi();
continue;
}
@ -1211,7 +1211,7 @@ struct XAigerWriter : AigerWriter {
holes_wb->setPort(port_id, w);
} else {
log_error("Ambiguous port direction on %s/%s\n",
box->type.unescape(), design->twines.str(port_id).c_str());
design->twines.unescaped_str(box->type), design->twines.str(port_id).c_str());
}
}
}
@ -1406,7 +1406,7 @@ struct Aiger2Backend : Backend {
continue;
if (known_ops(cell.type))
continue;
std::string name = cell.type.unescape();
std::string name = design->twines.unescaped_str(cell.type);
if (col + name.size() + 2 > 72) {
log("\n ");
col = 0;
@ -1428,7 +1428,7 @@ struct Aiger2Backend : Backend {
continue;
if (known_ops(cell.type))
continue;
std::string name = cell.type.unescape();
std::string name = design->twines.unescaped_str(cell.type);
if (col + name.size() + 2 > 72) {
log("\n ");
col = 0;