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https://github.com/YosysHQ/yosys
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WIP
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parent
afdae7b87e
commit
c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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@ -187,11 +187,11 @@ struct XAigerWriter
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TimingInfo timing;
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for (auto cell : module->cells()) {
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if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
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if (cell->type.in(TW($input_port), TW($output_port), TW($public)))
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continue;
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if (!cell->has_keep_attr()) {
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if (cell->type == ID($_NOT_))
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if (cell->type == TW($_NOT_))
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{
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SigBit A = sigmap(cell->getPort(TW::A).as_bit());
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SigBit Y = sigmap(cell->getPort(TW::Y).as_bit());
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@ -201,7 +201,7 @@ struct XAigerWriter
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continue;
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}
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if (cell->type == ID($_AND_))
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if (cell->type == TW($_AND_))
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{
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SigBit A = sigmap(cell->getPort(TW::A).as_bit());
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SigBit B = sigmap(cell->getPort(TW::B).as_bit());
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@ -213,7 +213,7 @@ struct XAigerWriter
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continue;
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}
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if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep))
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if (dff_mode && cell->type.in(TW($_DFF_N_), TW($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep))
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{
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SigBit D = sigmap(cell->getPort(TW::D).as_bit());
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SigBit Q = sigmap(cell->getPort(TW::Q).as_bit());
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@ -224,7 +224,7 @@ struct XAigerWriter
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continue;
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}
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if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
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if (cell->type.in(TW($specify2), TW($specify3), TW($specrule)))
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continue;
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}
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@ -248,12 +248,12 @@ struct XAigerWriter
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continue;
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}
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auto inst_name_id = RTLIL::IdString(design->twines.str(inst_module->meta_->name));
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auto inst_name_id = inst_module->meta_->name;
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if (!timing.count(inst_name_id))
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timing.setup_module(inst_module);
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for (auto &i : timing.at(inst_name_id).arrival) {
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auto port_name_ref = design->twines.add(Twine{i.first.name.str()});
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auto port_name_ref = i.first.name;
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if (!cell->hasPort(port_name_ref))
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continue;
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@ -273,7 +273,7 @@ struct XAigerWriter
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if (ys_debug(1)) {
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static pool<std::pair<IdString,TimingInfo::NameBit>> seen;
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if (seen.emplace(inst_name_id, i.first).second) log("%s.%s[%d] abc9_arrival = %d\n",
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cell->type.unescape(), i.first.name.unescape(), offset, d);
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cell->type.unescape(), design->twines.unescaped_str(i.first.name), offset, d);
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}
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#endif
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arrival_times[rhs[offset]] = d;
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@ -308,7 +308,7 @@ struct XAigerWriter
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}
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}
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//log_warning("Unsupported cell type: %s (%s)\n", cell->type.unescape(), cell);
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//log_warning("Unsupported cell type: %s (%s)\n", cell->type.unescaped(), cell);
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}
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dict<IdString, std::vector<TwineRef>> box_ports;
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