mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-20 06:05:50 +00:00
Code Activity

WIP

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
Download patch file Download diff file Expand all files Collapse all files

32
backends/aiger/aiger.cc
View file

@ -221,7 +221,7 @@ struct AigerWriter
for (auto cell : module->cells())
{
if (cell->type == ID($_NOT_))
if (cell->type == TW($_NOT_))
{
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit Y = sigmap(cell->getPort(TW::Y).as_bit());
@ -231,7 +231,7 @@ struct AigerWriter
continue;
}
if (cell->type.in(ID($_FF_), ID($_DFF_N_), ID($_DFF_P_)))
if (cell->type.in(TW($_FF_), TW($_DFF_N_), TW($_DFF_P_)))
{
SigBit D = sigmap(cell->getPort(TW::D).as_bit());
SigBit Q = sigmap(cell->getPort(TW::Q).as_bit());
@ -239,14 +239,14 @@ struct AigerWriter
undriven_bits.erase(Q);
ff_map[Q] = D;
if (cell->type != ID($_FF_)) {
if (cell->type != TW($_FF_)) {
auto sig_clk = sigmap(cell->getPort(TW::C).as_bit());
ywmap_clocks[sig_clk] |= cell->type == ID($_DFF_N_) ? 2 : 1;
ywmap_clocks[sig_clk] |= cell->type == TW($_DFF_N_) ? 2 : 1;
}
continue;
}
if (cell->type == ID($anyinit))
if (cell->type == TW($anyinit))
{
auto sig_d = sigmap(cell->getPort(TW::D));
auto sig_q = sigmap(cell->getPort(TW::Q));
@ -257,7 +257,7 @@ struct AigerWriter
continue;
}
if (cell->type == ID($_AND_))
if (cell->type == TW($_AND_))
{
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit B = sigmap(cell->getPort(TW::B).as_bit());
@ -269,7 +269,7 @@ struct AigerWriter
continue;
}
if (cell->type == ID($initstate))
if (cell->type == TW($initstate))
{
SigBit Y = sigmap(cell->getPort(TW::Y).as_bit());
undriven_bits.erase(Y);
@ -277,7 +277,7 @@ struct AigerWriter
continue;
}
if (cell->type == ID($assert))
if (cell->type == TW($assert))
{
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit EN = sigmap(cell->getPort(TW::EN).as_bit());
@ -288,7 +288,7 @@ struct AigerWriter
continue;
}
if (cell->type == ID($assume))
if (cell->type == TW($assume))
{
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit EN = sigmap(cell->getPort(TW::EN).as_bit());
@ -299,7 +299,7 @@ struct AigerWriter
continue;
}
if (cell->type == ID($live))
if (cell->type == TW($live))
{
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit EN = sigmap(cell->getPort(TW::EN).as_bit());
@ -309,7 +309,7 @@ struct AigerWriter
continue;
}
if (cell->type == ID($fair))
if (cell->type == TW($fair))
{
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit EN = sigmap(cell->getPort(TW::EN).as_bit());
@ -319,7 +319,7 @@ struct AigerWriter
continue;
}
if (cell->type == ID($anyconst))
if (cell->type == TW($anyconst))
{
for (auto bit : sigmap(cell->getPort(TW::Y))) {
undriven_bits.erase(bit);
@ -328,7 +328,7 @@ struct AigerWriter
continue;
}
if (cell->type == ID($anyseq))
if (cell->type == TW($anyseq))
{
for (auto bit : sigmap(cell->getPort(TW::Y))) {
undriven_bits.erase(bit);
@ -337,7 +337,7 @@ struct AigerWriter
continue;
}
if (cell->type.in(ID($scopeinfo), ID($input_port), ID($output_port), ID($public)))
if (cell->type.in(TW($scopeinfo), TW($input_port), TW($output_port), TW($public)))
continue;
log_error("Unsupported cell type: %s (%s)\n", cell->type.unescape(), cell);
@ -773,10 +773,10 @@ struct AigerWriter
for (auto cell : module->cells())
{
if (cell->type.in(ID($_FF_), ID($_DFF_N_), ID($_DFF_P_), ID($anyinit), ID($anyconst), ID($anyseq)))
if (cell->type.in(TW($_FF_), TW($_DFF_N_), TW($_DFF_P_), TW($anyinit), TW($anyconst), TW($anyseq)))
{
// Use sig_q to get the FF output name, but sig to lookup aiger bits
auto sig_qy = cell->getPort(cell->type.in(ID($anyconst), ID($anyseq)) ? TW::Y : TW::Q);
auto sig_qy = cell->getPort(cell->type.in(TW($anyconst), TW($anyseq)) ? TW::Y : TW::Q);
SigSpec sig = sigmap(sig_qy);
if (cell->get_bool_attribute(ID(clk2fflogic)))