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This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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32
backends/aiger/aiger.cc
View file

@ -221,7 +221,7 @@ struct AigerWriter
for (auto cell : module->cells())
{
if (cell->type == ID($_NOT_))
if (cell->type == TW($_NOT_))
{
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit Y = sigmap(cell->getPort(TW::Y).as_bit());
@ -231,7 +231,7 @@ struct AigerWriter
continue;
}
if (cell->type.in(ID($_FF_), ID($_DFF_N_), ID($_DFF_P_)))
if (cell->type.in(TW($_FF_), TW($_DFF_N_), TW($_DFF_P_)))
{
SigBit D = sigmap(cell->getPort(TW::D).as_bit());
SigBit Q = sigmap(cell->getPort(TW::Q).as_bit());
@ -239,14 +239,14 @@ struct AigerWriter
undriven_bits.erase(Q);
ff_map[Q] = D;
if (cell->type != ID($_FF_)) {
if (cell->type != TW($_FF_)) {
auto sig_clk = sigmap(cell->getPort(TW::C).as_bit());
ywmap_clocks[sig_clk] |= cell->type == ID($_DFF_N_) ? 2 : 1;
ywmap_clocks[sig_clk] |= cell->type == TW($_DFF_N_) ? 2 : 1;
}
continue;
}
if (cell->type == ID($anyinit))
if (cell->type == TW($anyinit))
{
auto sig_d = sigmap(cell->getPort(TW::D));
auto sig_q = sigmap(cell->getPort(TW::Q));
@ -257,7 +257,7 @@ struct AigerWriter
continue;
}
if (cell->type == ID($_AND_))
if (cell->type == TW($_AND_))
{
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit B = sigmap(cell->getPort(TW::B).as_bit());
@ -269,7 +269,7 @@ struct AigerWriter
continue;
}
if (cell->type == ID($initstate))
if (cell->type == TW($initstate))
{
SigBit Y = sigmap(cell->getPort(TW::Y).as_bit());
undriven_bits.erase(Y);
@ -277,7 +277,7 @@ struct AigerWriter
continue;
}
if (cell->type == ID($assert))
if (cell->type == TW($assert))
{
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit EN = sigmap(cell->getPort(TW::EN).as_bit());
@ -288,7 +288,7 @@ struct AigerWriter
continue;
}
if (cell->type == ID($assume))
if (cell->type == TW($assume))
{
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit EN = sigmap(cell->getPort(TW::EN).as_bit());
@ -299,7 +299,7 @@ struct AigerWriter
continue;
}
if (cell->type == ID($live))
if (cell->type == TW($live))
{
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit EN = sigmap(cell->getPort(TW::EN).as_bit());
@ -309,7 +309,7 @@ struct AigerWriter
continue;
}
if (cell->type == ID($fair))
if (cell->type == TW($fair))
{
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit EN = sigmap(cell->getPort(TW::EN).as_bit());
@ -319,7 +319,7 @@ struct AigerWriter
continue;
}
if (cell->type == ID($anyconst))
if (cell->type == TW($anyconst))
{
for (auto bit : sigmap(cell->getPort(TW::Y))) {
undriven_bits.erase(bit);
@ -328,7 +328,7 @@ struct AigerWriter
continue;
}
if (cell->type == ID($anyseq))
if (cell->type == TW($anyseq))
{
for (auto bit : sigmap(cell->getPort(TW::Y))) {
undriven_bits.erase(bit);
@ -337,7 +337,7 @@ struct AigerWriter
continue;
}
if (cell->type.in(ID($scopeinfo), ID($input_port), ID($output_port), ID($public)))
if (cell->type.in(TW($scopeinfo), TW($input_port), TW($output_port), TW($public)))
continue;
log_error("Unsupported cell type: %s (%s)\n", cell->type.unescape(), cell);
@ -773,10 +773,10 @@ struct AigerWriter
for (auto cell : module->cells())
{
if (cell->type.in(ID($_FF_), ID($_DFF_N_), ID($_DFF_P_), ID($anyinit), ID($anyconst), ID($anyseq)))
if (cell->type.in(TW($_FF_), TW($_DFF_N_), TW($_DFF_P_), TW($anyinit), TW($anyconst), TW($anyseq)))
{
// Use sig_q to get the FF output name, but sig to lookup aiger bits
auto sig_qy = cell->getPort(cell->type.in(ID($anyconst), ID($anyseq)) ? TW::Y : TW::Q);
auto sig_qy = cell->getPort(cell->type.in(TW($anyconst), TW($anyseq)) ? TW::Y : TW::Q);
SigSpec sig = sigmap(sig_qy);
if (cell->get_bool_attribute(ID(clk2fflogic)))

18
backends/aiger/xaiger.cc
View file

@ -187,11 +187,11 @@ struct XAigerWriter
TimingInfo timing;
for (auto cell : module->cells()) {
if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
if (cell->type.in(TW($input_port), TW($output_port), TW($public)))
continue;
if (!cell->has_keep_attr()) {
if (cell->type == ID($_NOT_))
if (cell->type == TW($_NOT_))
{
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit Y = sigmap(cell->getPort(TW::Y).as_bit());
@ -201,7 +201,7 @@ struct XAigerWriter
continue;
}
if (cell->type == ID($_AND_))
if (cell->type == TW($_AND_))
{
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit B = sigmap(cell->getPort(TW::B).as_bit());
@ -213,7 +213,7 @@ struct XAigerWriter
continue;
}
if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep))
if (dff_mode && cell->type.in(TW($_DFF_N_), TW($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep))
{
SigBit D = sigmap(cell->getPort(TW::D).as_bit());
SigBit Q = sigmap(cell->getPort(TW::Q).as_bit());
@ -224,7 +224,7 @@ struct XAigerWriter
continue;
}
if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
if (cell->type.in(TW($specify2), TW($specify3), TW($specrule)))
continue;
}
@ -248,12 +248,12 @@ struct XAigerWriter
continue;
}
auto inst_name_id = RTLIL::IdString(design->twines.str(inst_module->meta_->name));
auto inst_name_id = inst_module->meta_->name;
if (!timing.count(inst_name_id))
timing.setup_module(inst_module);
for (auto &i : timing.at(inst_name_id).arrival) {
auto port_name_ref = design->twines.add(Twine{i.first.name.str()});
auto port_name_ref = i.first.name;
if (!cell->hasPort(port_name_ref))
continue;
@ -273,7 +273,7 @@ struct XAigerWriter
if (ys_debug(1)) {
static pool<std::pair<IdString,TimingInfo::NameBit>> seen;
if (seen.emplace(inst_name_id, i.first).second) log("%s.%s[%d] abc9_arrival = %d\n",
cell->type.unescape(), i.first.name.unescape(), offset, d);
cell->type.unescape(), design->twines.unescaped_str(i.first.name), offset, d);
}
#endif
arrival_times[rhs[offset]] = d;
@ -308,7 +308,7 @@ struct XAigerWriter
}
}
//log_warning("Unsupported cell type: %s (%s)\n", cell->type.unescape(), cell);
//log_warning("Unsupported cell type: %s (%s)\n", cell->type.unescaped(), cell);
}
dict<IdString, std::vector<TwineRef>> box_ports;