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This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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32
backends/aiger/aiger.cc
View file

@ -221,7 +221,7 @@ struct AigerWriter
for (auto cell : module->cells())
{
if (cell->type == ID($_NOT_))
if (cell->type == TW($_NOT_))
{
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit Y = sigmap(cell->getPort(TW::Y).as_bit());
@ -231,7 +231,7 @@ struct AigerWriter
continue;
}
if (cell->type.in(ID($_FF_), ID($_DFF_N_), ID($_DFF_P_)))
if (cell->type.in(TW($_FF_), TW($_DFF_N_), TW($_DFF_P_)))
{
SigBit D = sigmap(cell->getPort(TW::D).as_bit());
SigBit Q = sigmap(cell->getPort(TW::Q).as_bit());
@ -239,14 +239,14 @@ struct AigerWriter
undriven_bits.erase(Q);
ff_map[Q] = D;
if (cell->type != ID($_FF_)) {
if (cell->type != TW($_FF_)) {
auto sig_clk = sigmap(cell->getPort(TW::C).as_bit());
ywmap_clocks[sig_clk] |= cell->type == ID($_DFF_N_) ? 2 : 1;
ywmap_clocks[sig_clk] |= cell->type == TW($_DFF_N_) ? 2 : 1;
}
continue;
}
if (cell->type == ID($anyinit))
if (cell->type == TW($anyinit))
{
auto sig_d = sigmap(cell->getPort(TW::D));
auto sig_q = sigmap(cell->getPort(TW::Q));
@ -257,7 +257,7 @@ struct AigerWriter
continue;
}
if (cell->type == ID($_AND_))
if (cell->type == TW($_AND_))
{
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit B = sigmap(cell->getPort(TW::B).as_bit());
@ -269,7 +269,7 @@ struct AigerWriter
continue;
}
if (cell->type == ID($initstate))
if (cell->type == TW($initstate))
{
SigBit Y = sigmap(cell->getPort(TW::Y).as_bit());
undriven_bits.erase(Y);
@ -277,7 +277,7 @@ struct AigerWriter
continue;
}
if (cell->type == ID($assert))
if (cell->type == TW($assert))
{
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit EN = sigmap(cell->getPort(TW::EN).as_bit());
@ -288,7 +288,7 @@ struct AigerWriter
continue;
}
if (cell->type == ID($assume))
if (cell->type == TW($assume))
{
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit EN = sigmap(cell->getPort(TW::EN).as_bit());
@ -299,7 +299,7 @@ struct AigerWriter
continue;
}
if (cell->type == ID($live))
if (cell->type == TW($live))
{
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit EN = sigmap(cell->getPort(TW::EN).as_bit());
@ -309,7 +309,7 @@ struct AigerWriter
continue;
}
if (cell->type == ID($fair))
if (cell->type == TW($fair))
{
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit EN = sigmap(cell->getPort(TW::EN).as_bit());
@ -319,7 +319,7 @@ struct AigerWriter
continue;
}
if (cell->type == ID($anyconst))
if (cell->type == TW($anyconst))
{
for (auto bit : sigmap(cell->getPort(TW::Y))) {
undriven_bits.erase(bit);
@ -328,7 +328,7 @@ struct AigerWriter
continue;
}
if (cell->type == ID($anyseq))
if (cell->type == TW($anyseq))
{
for (auto bit : sigmap(cell->getPort(TW::Y))) {
undriven_bits.erase(bit);
@ -337,7 +337,7 @@ struct AigerWriter
continue;
}
if (cell->type.in(ID($scopeinfo), ID($input_port), ID($output_port), ID($public)))
if (cell->type.in(TW($scopeinfo), TW($input_port), TW($output_port), TW($public)))
continue;
log_error("Unsupported cell type: %s (%s)\n", cell->type.unescape(), cell);
@ -773,10 +773,10 @@ struct AigerWriter
for (auto cell : module->cells())
{
if (cell->type.in(ID($_FF_), ID($_DFF_N_), ID($_DFF_P_), ID($anyinit), ID($anyconst), ID($anyseq)))
if (cell->type.in(TW($_FF_), TW($_DFF_N_), TW($_DFF_P_), TW($anyinit), TW($anyconst), TW($anyseq)))
{
// Use sig_q to get the FF output name, but sig to lookup aiger bits
auto sig_qy = cell->getPort(cell->type.in(ID($anyconst), ID($anyseq)) ? TW::Y : TW::Q);
auto sig_qy = cell->getPort(cell->type.in(TW($anyconst), TW($anyseq)) ? TW::Y : TW::Q);
SigSpec sig = sigmap(sig_qy);
if (cell->get_bool_attribute(ID(clk2fflogic)))

18
backends/aiger/xaiger.cc
View file

@ -187,11 +187,11 @@ struct XAigerWriter
TimingInfo timing;
for (auto cell : module->cells()) {
if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
if (cell->type.in(TW($input_port), TW($output_port), TW($public)))
continue;
if (!cell->has_keep_attr()) {
if (cell->type == ID($_NOT_))
if (cell->type == TW($_NOT_))
{
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit Y = sigmap(cell->getPort(TW::Y).as_bit());
@ -201,7 +201,7 @@ struct XAigerWriter
continue;
}
if (cell->type == ID($_AND_))
if (cell->type == TW($_AND_))
{
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit B = sigmap(cell->getPort(TW::B).as_bit());
@ -213,7 +213,7 @@ struct XAigerWriter
continue;
}
if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep))
if (dff_mode && cell->type.in(TW($_DFF_N_), TW($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep))
{
SigBit D = sigmap(cell->getPort(TW::D).as_bit());
SigBit Q = sigmap(cell->getPort(TW::Q).as_bit());
@ -224,7 +224,7 @@ struct XAigerWriter
continue;
}
if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
if (cell->type.in(TW($specify2), TW($specify3), TW($specrule)))
continue;
}
@ -248,12 +248,12 @@ struct XAigerWriter
continue;
}
auto inst_name_id = RTLIL::IdString(design->twines.str(inst_module->meta_->name));
auto inst_name_id = inst_module->meta_->name;
if (!timing.count(inst_name_id))
timing.setup_module(inst_module);
for (auto &i : timing.at(inst_name_id).arrival) {
auto port_name_ref = design->twines.add(Twine{i.first.name.str()});
auto port_name_ref = i.first.name;
if (!cell->hasPort(port_name_ref))
continue;
@ -273,7 +273,7 @@ struct XAigerWriter
if (ys_debug(1)) {
static pool<std::pair<IdString,TimingInfo::NameBit>> seen;
if (seen.emplace(inst_name_id, i.first).second) log("%s.%s[%d] abc9_arrival = %d\n",
cell->type.unescape(), i.first.name.unescape(), offset, d);
cell->type.unescape(), design->twines.unescaped_str(i.first.name), offset, d);
}
#endif
arrival_times[rhs[offset]] = d;
@ -308,7 +308,7 @@ struct XAigerWriter
}
}
//log_warning("Unsupported cell type: %s (%s)\n", cell->type.unescape(), cell);
//log_warning("Unsupported cell type: %s (%s)\n", cell->type.unescaped(), cell);
}
dict<IdString, std::vector<TwineRef>> box_ports;

112
backends/aiger2/aiger.cc
View file

@ -32,21 +32,21 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
#define BITWISE_OPS ID($buf), ID($not), ID($mux), ID($and), ID($or), ID($xor), ID($xnor), ID($fa), \
ID($bwmux)
#define BITWISE_OPS TW($buf), TW($not), TW($mux), TW($and), TW($or), TW($xor), TW($xnor), TW($fa), \
TW($bwmux)
#define REDUCE_OPS ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool)
#define REDUCE_OPS TW($reduce_and), TW($reduce_or), TW($reduce_xor), TW($reduce_xnor), TW($reduce_bool)
#define LOGIC_OPS ID($logic_and), ID($logic_or), ID($logic_not)
#define LOGIC_OPS TW($logic_and), TW($logic_or), TW($logic_not)
#define GATE_OPS ID($_BUF_), ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), \
ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($_MUX_), ID($_NMUX_), \
ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_)
#define GATE_OPS TW($_BUF_), TW($_NOT_), TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_), \
TW($_XOR_), TW($_XNOR_), TW($_ANDNOT_), TW($_ORNOT_), TW($_MUX_), TW($_NMUX_), \
TW($_AOI3_), TW($_OAI3_), TW($_AOI4_), TW($_OAI4_)
#define CMP_OPS ID($eq), ID($ne), ID($lt), ID($le), ID($ge), ID($gt)
#define CMP_OPS TW($eq), TW($ne), TW($lt), TW($le), TW($ge), TW($gt)
// TODO
//#define ARITH_OPS ID($add), ID($sub), ID($neg)
//#define ARITH_OPS TW($add), TW($sub), TW($neg)
static constexpr auto known_ops = []() constexpr {
StaticCellTypes::Categories::Category c{};
@ -60,7 +60,7 @@ static constexpr auto known_ops = []() constexpr {
c.set_id(id);
for (auto id : {CMP_OPS})
c.set_id(id);
for (auto id : {ID($pos), ID($pmux), ID($bmux)})
for (auto id : {TW($pos), TW($pmux), TW($bmux)})
c.set_id(id);
return c;
}();
@ -109,7 +109,7 @@ struct Index {
int pos = index_wires(info, m);
for (auto cell : m->cells()) {
if (known_ops(cell->type) || cell->type.in(ID($scopeinfo), ID($specify2), ID($specify3), ID($input_port), ID($output_port), ID($public)))
if (known_ops(cell->type) || cell->type.in(TW($scopeinfo), TW($specify2), TW($specify3), TW($input_port), TW($output_port), TW($public)))
continue;
Module *submodule = m->design->module(cell->type);
@ -128,7 +128,7 @@ struct Index {
// can't bail at this point. If they are hit by a traversal
// (which can only really happen with $tribuf not
// $connect), we can still detect this as an error later.
if (cell->type == ID($connect) || (cell->type == ID($tribuf) && cell->has_attribute(ID(aiger2_zbuf))))
if (cell->type == TW($connect) || (cell->type == TW($tribuf) && cell->has_attribute(ID(aiger2_zbuf))))
continue;
if (!submodule || submodule->get_blackbox_attribute())
log_error("Unsupported cell type: %s (%s in %s)\n",
@ -292,18 +292,18 @@ struct Index {
aport.extend_u0(width, asigned);
bport.extend_u0(width, bsigned);
if (cell->type.in(ID($eq), ID($ne))) {
if (cell->type.in(TW($eq), TW($ne))) {
int carry = CTRUE;
for (int i = 0; i < width; i++) {
Lit a = visit(cursor, aport[i]);
Lit b = visit(cursor, bport[i]);
carry = AND(carry, XNOR(a, b));
}
return (cell->type == ID($eq)) ? carry : /* $ne */ NOT(carry);
} else if (cell->type.in(ID($lt), ID($le), ID($gt), ID($ge))) {
if (cell->type.in(ID($gt), ID($ge)))
return (cell->type == TW($eq)) ? carry : /* $ne */ NOT(carry);
} else if (cell->type.in(TW($lt), TW($le), TW($gt), TW($ge))) {
if (cell->type.in(TW($gt), TW($ge)))
std::swap(aport, bport);
int carry = cell->type.in(ID($le), ID($ge)) ? CFALSE : CTRUE;
int carry = cell->type.in(TW($le), TW($ge)) ? CFALSE : CTRUE;
Lit a = Writer::EMPTY_LIT;
Lit b = Writer::EMPTY_LIT;
// TODO: this might not be the most economic structure; revisit at a later date
@ -317,28 +317,28 @@ struct Index {
} else {
log_abort();
}
} else if (cell->type.in(REDUCE_OPS, ID($logic_not))) {
} else if (cell->type.in(REDUCE_OPS, TW($logic_not))) {
SigSpec inport = cell->getPort(TW::A);
std::vector<Lit> lits;
for (int i = 0; i < inport.size(); i++) {
Lit lit = visit(cursor, inport[i]);
if (cell->type.in(ID($reduce_and), ID($reduce_xor), ID($reduce_xnor))) {
if (cell->type.in(TW($reduce_and), TW($reduce_xor), TW($reduce_xnor))) {
lits.push_back(lit);
} else if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not))) {
} else if (cell->type.in(TW($reduce_or), TW($reduce_bool), TW($logic_not))) {
lits.push_back(NOT(lit));
} else {
log_abort();
}
}
Lit acc = REDUCE(lits, cell->type.in(ID($reduce_xor), ID($reduce_xnor)));
Lit acc = REDUCE(lits, cell->type.in(TW($reduce_xor), TW($reduce_xnor)));
if (!cell->type.in(ID($reduce_xnor), ID($reduce_or), ID($reduce_bool)))
if (!cell->type.in(TW($reduce_xnor), TW($reduce_or), TW($reduce_bool)))
return acc;
else
return NOT(acc);
} else if (cell->type.in(ID($logic_and), ID($logic_or))) {
} else if (cell->type.in(TW($logic_and), TW($logic_or))) {
SigSpec aport = cell->getPort(TW::A);
SigSpec bport = cell->getPort(TW::B);
@ -356,13 +356,13 @@ struct Index {
b = OR(b, l);
}
if (cell->type == ID($logic_and))
if (cell->type == TW($logic_and))
return AND(a, b);
else if (cell->type == ID($logic_or))
else if (cell->type == TW($logic_or))
return OR(a, b);
else
log_abort();
} else if (cell->type.in(BITWISE_OPS, GATE_OPS, ID($pos))) {
} else if (cell->type.in(BITWISE_OPS, GATE_OPS, TW($pos))) {
SigSpec aport = cell->getPort(TW::A);
Lit a;
if (obit < aport.size()) {
@ -374,9 +374,9 @@ struct Index {
a = CFALSE;
}
if (cell->type.in(ID($buf), ID($pos), ID($_BUF_))) {
if (cell->type.in(TW($buf), TW($pos), TW($_BUF_))) {
return a;
} else if (cell->type.in(ID($not), ID($_NOT_))) {
} else if (cell->type.in(TW($not), TW($_NOT_))) {
return NOT(a);
} else {
SigSpec bport = cell->getPort(TW::B);
@ -390,32 +390,32 @@ struct Index {
b = CFALSE;
}
if (cell->type.in(ID($and), ID($_AND_))) {
if (cell->type.in(TW($and), TW($_AND_))) {
return AND(a, b);
} else if (cell->type.in(ID($_NAND_))) {
} else if (cell->type.in(TW($_NAND_))) {
return NOT(AND(a, b));
} else if (cell->type.in(ID($or), ID($_OR_))) {
} else if (cell->type.in(TW($or), TW($_OR_))) {
return OR(a, b);
} else if (cell->type.in(ID($_NOR_))) {
} else if (cell->type.in(TW($_NOR_))) {
return NOT(OR(a, b));
} else if (cell->type.in(ID($xor), ID($_XOR_))) {
} else if (cell->type.in(TW($xor), TW($_XOR_))) {
return XOR(a, b);
} else if (cell->type.in(ID($xnor), ID($_XNOR_))) {
} else if (cell->type.in(TW($xnor), TW($_XNOR_))) {
return XNOR(a, b);
} else if (cell->type.in(ID($_ANDNOT_))) {
} else if (cell->type.in(TW($_ANDNOT_))) {
return AND(a, NOT(b));
} else if (cell->type.in(ID($_ORNOT_))) {
} else if (cell->type.in(TW($_ORNOT_))) {
return OR(a, NOT(b));
} else if (cell->type.in(ID($mux), ID($_MUX_))) {
} else if (cell->type.in(TW($mux), TW($_MUX_))) {
Lit s = visit(cursor, cell->getPort(TW::S));
return MUX(a, b, s);
} else if (cell->type.in(ID($bwmux))) {
} else if (cell->type.in(TW($bwmux))) {
Lit s = visit(cursor, cell->getPort(TW::S)[obit]);
return MUX(a, b, s);
} else if (cell->type.in(ID($_NMUX_))) {
} else if (cell->type.in(TW($_NMUX_))) {
Lit s = visit(cursor, cell->getPort(TW::S)[obit]);
return NOT(MUX(a, b, s));
} else if (cell->type.in(ID($fa))) {
} else if (cell->type.in(TW($fa))) {
Lit c = visit(cursor, cell->getPort(TW::C)[obit]);
Lit ab = XOR(a, b);
if (oport == TW::Y) {
@ -425,16 +425,16 @@ struct Index {
Lit c_and_ab = AND(c, ab);
return OR(a_and_b, c_and_ab);
}
} else if (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) {
} else if (cell->type.in(TW($_AOI3_), TW($_OAI3_), TW($_AOI4_), TW($_OAI4_))) {
Lit c, d;
c = visit(cursor, cell->getPort(TW::C)[obit]);
if (/* 4 input types */ cell->type.in(ID($_AOI4_), ID($_OAI4_)))
if (/* 4 input types */ cell->type.in(TW($_AOI4_), TW($_OAI4_)))
d = visit(cursor, cell->getPort(TW::D)[obit]);
else
d = cell->type == ID($_AOI3_) ? CTRUE : CFALSE;
d = cell->type == TW($_AOI3_) ? CTRUE : CFALSE;
if (/* aoi */ cell->type.in(ID($_AOI3_), ID($_AOI4_))) {
if (/* aoi */ cell->type.in(TW($_AOI3_), TW($_AOI4_))) {
Lit a_and_b = AND(a, b);
Lit c_and_d = AND(c, d);
return NOT(OR(a_and_b, c_and_d));
@ -447,7 +447,7 @@ struct Index {
log_abort();
}
}
} else if (cell->type == ID($pmux)) {
} else if (cell->type == TW($pmux)) {
SigSpec aport = cell->getPort(TW::A);
SigSpec bport = cell->getPort(TW::B);
SigSpec sport = cell->getPort(TW::S);
@ -468,7 +468,7 @@ struct Index {
Lit reduce_bar = NOT(REDUCE(bar));
return OR(reduce_sels_and_a, reduce_bar);
} else if (cell->type == ID($bmux)) {
} else if (cell->type == TW($bmux)) {
SigSpec aport = cell->getPort(TW::A);
SigSpec sport = cell->getPort(TW::S);
int width = cell->getParam(ID::WIDTH).as_int();
@ -537,7 +537,7 @@ struct Index {
Design *design = index.design;
auto &minfo = leaf_minfo(index);
if (!minfo.suboffsets.count(cell))
log_error("Reached unsupported cell %s (%s in %s)\n", cell->type.unescape(), cell, cell->module);
log_error("Reached unsupported cell %s (%s in %s)\n", cell->type.unescaped(), cell, cell->module);
Module *def = design->module(cell->type);
log_assert(def);
levels.push_back(Level(index.modules.at(def), cell));
@ -660,7 +660,7 @@ struct Index {
auto &port = instance->getPort(portname);
if (bit.offset >= port.size())
log_error("Bit %d of input port %s on instance %s of %s unconnected\n",
bit.offset, design->twines.str(portname).c_str(), instance, instance->type.unescape());
bit.offset, design->twines.str(portname).c_str(), instance, design->twines.unescaped_str(instance->type));
ret = visit(cursor, port[bit.offset]);
}
cursor.enter(*this, instance);
@ -845,7 +845,7 @@ struct AigerWriter : Index<AigerWriter, unsigned int, 0, 1> {
char buf[32];
snprintf(buf, sizeof(buf), "o%d ", i);
f->write(buf, strlen(buf));
std::string name = bit.wire->name.unescape();
std::string name = design->twines.unescaped_str(bit.wire->name);
f->write(name.data(), name.size());
f->put('\n');
}
@ -858,7 +858,7 @@ struct AigerWriter : Index<AigerWriter, unsigned int, 0, 1> {
char buf[32];
snprintf(buf, sizeof(buf), "i%d ", i);
f->write(buf, strlen(buf));
std::string name = bit.wire->name.unescape();
std::string name = design->twines.unescaped_str(bit.wire->name);
f->write(name.data(), name.size());
f->put('\n');
}
@ -1090,7 +1090,7 @@ struct XAigerWriter : AigerWriter {
for (auto box : minfo.found_blackboxes) {
log_debug(" - %s.%s (type %s): ", cursor.path(),
box,
box->type.unescape());
design->twines.unescaped_str(box->type));
Module *box_module = design->module(box->type), *box_derived;
@ -1159,7 +1159,7 @@ struct XAigerWriter : AigerWriter {
} else {
// FIXME: hierarchical path
log_warning("connection on port %s[%d] of instance %s (type %s) missing, using 1'bx\n",
design->twines.str(port_id).c_str(), i, box, box->type.unescape());
design->twines.str(port_id).c_str(), i, box, design->twines.unescaped_str(box->type));
bit = RTLIL::Sx;
}
@ -1194,7 +1194,7 @@ struct XAigerWriter : AigerWriter {
} else {
// FIXME: hierarchical path
log_warning("connection on port %s[%d] of instance %s (type %s) missing\n",
design->twines.str(port_id).c_str(), i, box, box->type.unescape());
design->twines.str(port_id).c_str(), i, box, design->twines.unescaped_str(box->type));
pad_pi();
continue;
}
@ -1211,7 +1211,7 @@ struct XAigerWriter : AigerWriter {
holes_wb->setPort(port_id, w);
} else {
log_error("Ambiguous port direction on %s/%s\n",
box->type.unescape(), design->twines.str(port_id).c_str());
design->twines.unescaped_str(box->type), design->twines.str(port_id).c_str());
}
}
}
@ -1406,7 +1406,7 @@ struct Aiger2Backend : Backend {
continue;
if (known_ops(cell.type))
continue;
std::string name = cell.type.unescape();
std::string name = design->twines.unescaped_str(cell.type);
if (col + name.size() + 2 > 72) {
log("\n ");
col = 0;
@ -1428,7 +1428,7 @@ struct Aiger2Backend : Backend {
continue;
if (known_ops(cell.type))
continue;
std::string name = cell.type.unescape();
std::string name = design->twines.unescaped_str(cell.type);
if (col + name.size() + 2 > 72) {
log("\n ");
col = 0;

52
backends/blif/blif.cc
View file

@ -91,7 +91,7 @@ struct BlifDumper
const std::string str(RTLIL::IdString id)
{
std::string str = id.unescape();
std::string str = design->twines.unescaped_str(id);
for (size_t i = 0; i < str.size(); i++)
if (str[i] == '#' || str[i] == '=' || str[i] == '<' || str[i] == '>')
str[i] = '?';
@ -108,7 +108,7 @@ struct BlifDumper
return config->undef_type == "-" || config->undef_type == "+" ? config->undef_out.c_str() : "$undef";
}
std::string str = sig.wire->name.unescape();
std::string str = design->twines.unescaped_str(sig.wire->name);
for (size_t i = 0; i < str.size(); i++)
if (str[i] == '#' || str[i] == '=' || str[i] == '<' || str[i] == '>')
str[i] = '?';
@ -150,7 +150,7 @@ struct BlifDumper
void dump_params(const char *command, dict<IdString, Const> &params)
{
for (auto &param : params) {
f << stringf("%s %s ", command, param.first.unescape());
f << stringf("%s %s ", command, design->twines.unescaped_str(param.first));
if (param.second.flags & RTLIL::CONST_FLAG_STRING) {
std::string str = param.second.decode_string();
f << stringf("\"");
@ -232,7 +232,7 @@ struct BlifDumper
for (auto cell : module->cells())
{
if (cell->type == ID($scopeinfo))
if (cell->type == TW($scopeinfo))
continue;
if (config->unbuf_types.count(cell->type)) {
@ -244,131 +244,131 @@ struct BlifDumper
continue;
}
if (!config->icells_mode && cell->type == ID($_NOT_)) {
if (!config->icells_mode && cell->type == TW($_NOT_)) {
f << stringf(".names %s %s\n0 1\n",
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_AND_)) {
if (!config->icells_mode && cell->type == TW($_AND_)) {
f << stringf(".names %s %s %s\n11 1\n",
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_OR_)) {
if (!config->icells_mode && cell->type == TW($_OR_)) {
f << stringf(".names %s %s %s\n1- 1\n-1 1\n",
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_XOR_)) {
if (!config->icells_mode && cell->type == TW($_XOR_)) {
f << stringf(".names %s %s %s\n10 1\n01 1\n",
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_NAND_)) {
if (!config->icells_mode && cell->type == TW($_NAND_)) {
f << stringf(".names %s %s %s\n0- 1\n-0 1\n",
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_NOR_)) {
if (!config->icells_mode && cell->type == TW($_NOR_)) {
f << stringf(".names %s %s %s\n00 1\n",
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_XNOR_)) {
if (!config->icells_mode && cell->type == TW($_XNOR_)) {
f << stringf(".names %s %s %s\n11 1\n00 1\n",
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_ANDNOT_)) {
if (!config->icells_mode && cell->type == TW($_ANDNOT_)) {
f << stringf(".names %s %s %s\n10 1\n",
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_ORNOT_)) {
if (!config->icells_mode && cell->type == TW($_ORNOT_)) {
f << stringf(".names %s %s %s\n1- 1\n-0 1\n",
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_AOI3_)) {
if (!config->icells_mode && cell->type == TW($_AOI3_)) {
f << stringf(".names %s %s %s %s\n-00 1\n0-0 1\n",
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::C)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_OAI3_)) {
if (!config->icells_mode && cell->type == TW($_OAI3_)) {
f << stringf(".names %s %s %s %s\n00- 1\n--0 1\n",
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::C)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_AOI4_)) {
if (!config->icells_mode && cell->type == TW($_AOI4_)) {
f << stringf(".names %s %s %s %s %s\n-0-0 1\n-00- 1\n0--0 1\n0-0- 1\n",
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(),
str(cell->getPort(TW::C)).c_str(), str(cell->getPort(TW::D)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_OAI4_)) {
if (!config->icells_mode && cell->type == TW($_OAI4_)) {
f << stringf(".names %s %s %s %s %s\n00-- 1\n--00 1\n",
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(),
str(cell->getPort(TW::C)).c_str(), str(cell->getPort(TW::D)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_MUX_)) {
if (!config->icells_mode && cell->type == TW($_MUX_)) {
f << stringf(".names %s %s %s %s\n1-0 1\n-11 1\n",
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(),
str(cell->getPort(TW::S)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_NMUX_)) {
if (!config->icells_mode && cell->type == TW($_NMUX_)) {
f << stringf(".names %s %s %s %s\n0-0 1\n-01 1\n",
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(),
str(cell->getPort(TW::S)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_FF_)) {
if (!config->icells_mode && cell->type == TW($_FF_)) {
f << stringf(".latch %s %s%s\n", str(cell->getPort(TW::D)), str(cell->getPort(TW::Q)),
str_init(cell->getPort(TW::Q)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_DFF_N_)) {
if (!config->icells_mode && cell->type == TW($_DFF_N_)) {
f << stringf(".latch %s %s fe %s%s\n", str(cell->getPort(TW::D)), str(cell->getPort(TW::Q)),
str(cell->getPort(TW::C)).c_str(), str_init(cell->getPort(TW::Q)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_DFF_P_)) {
if (!config->icells_mode && cell->type == TW($_DFF_P_)) {
f << stringf(".latch %s %s re %s%s\n", str(cell->getPort(TW::D)), str(cell->getPort(TW::Q)),
str(cell->getPort(TW::C)).c_str(), str_init(cell->getPort(TW::Q)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_DLATCH_N_)) {
if (!config->icells_mode && cell->type == TW($_DLATCH_N_)) {
f << stringf(".latch %s %s al %s%s\n", str(cell->getPort(TW::D)), str(cell->getPort(TW::Q)),
str(cell->getPort(TW::E)).c_str(), str_init(cell->getPort(TW::Q)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_DLATCH_P_)) {
if (!config->icells_mode && cell->type == TW($_DLATCH_P_)) {
f << stringf(".latch %s %s ah %s%s\n", str(cell->getPort(TW::D)), str(cell->getPort(TW::Q)),
str(cell->getPort(TW::E)).c_str(), str_init(cell->getPort(TW::Q)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($lut)) {
if (!config->icells_mode && cell->type == TW($lut)) {
f << stringf(".names");
auto &inputs = cell->getPort(TW::A);
auto width = cell->parameters.at(ID::WIDTH).as_int();
@ -390,7 +390,7 @@ struct BlifDumper
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($sop)) {
if (!config->icells_mode && cell->type == TW($sop)) {
f << stringf(".names");
auto &inputs = cell->getPort(TW::A);
auto width = cell->parameters.at(ID::WIDTH).as_int();

156
backends/btor/btor.cc
View file

@ -119,7 +119,7 @@ struct BtorWorker
template<typename T>
string getinfo(T *obj, bool srcsym = false)
{
string infostr = obj->name.unescape();
string infostr = design->twines.unescaped_str(obj->name);
if (!srcsym && !print_internal_names && infostr[0] == '$') return "";
if (obj->has_attribute(ID::src)) {
string src = module && module->design ? module->design->get_src_attribute(obj) : std::string();
@ -147,7 +147,7 @@ struct BtorWorker
string getinfo(Mem *mem, bool srcsym = false)
{
string infostr = mem->memid.unescape();
string infostr = design->twines.unescaped_str(mem->memid);
if (!srcsym && !print_internal_names && infostr[0] == '$') return "";
if (mem->has_attribute(ID::src)) {
string src = module && module->design ? module->design->get_src_attribute(mem) : std::string();
@ -280,24 +280,24 @@ struct BtorWorker
cell_recursion_guard.insert(cell);
btorf_push(cell->module->design->twines.str(cell->meta_->name));
if (cell->type.in(ID($add), ID($sub), ID($mul), ID($and), ID($or), ID($xor), ID($xnor), ID($shl), ID($sshl), ID($shr), ID($sshr), ID($shift), ID($shiftx),
ID($concat), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_)))
if (cell->type.in(TW($add), TW($sub), TW($mul), TW($and), TW($or), TW($xor), TW($xnor), TW($shl), TW($sshl), TW($shr), TW($sshr), TW($shift), TW($shiftx),
TW($concat), TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_), TW($_XOR_), TW($_XNOR_)))
{
string btor_op;
if (cell->type == ID($add)) btor_op = "add";
if (cell->type == ID($sub)) btor_op = "sub";
if (cell->type == ID($mul)) btor_op = "mul";
if (cell->type.in(ID($shl), ID($sshl))) btor_op = "sll";
if (cell->type == ID($shr)) btor_op = "srl";
if (cell->type == ID($sshr)) btor_op = "sra";
if (cell->type.in(ID($shift), ID($shiftx))) btor_op = "shift";
if (cell->type.in(ID($and), ID($_AND_))) btor_op = "and";
if (cell->type.in(ID($or), ID($_OR_))) btor_op = "or";
if (cell->type.in(ID($xor), ID($_XOR_))) btor_op = "xor";
if (cell->type == ID($concat)) btor_op = "concat";
if (cell->type == ID($_NAND_)) btor_op = "nand";
if (cell->type == ID($_NOR_)) btor_op = "nor";
if (cell->type.in(ID($xnor), ID($_XNOR_))) btor_op = "xnor";
if (cell->type == TW($add)) btor_op = "add";
if (cell->type == TW($sub)) btor_op = "sub";
if (cell->type == TW($mul)) btor_op = "mul";
if (cell->type.in(TW($shl), TW($sshl))) btor_op = "sll";
if (cell->type == TW($shr)) btor_op = "srl";
if (cell->type == TW($sshr)) btor_op = "sra";
if (cell->type.in(TW($shift), TW($shiftx))) btor_op = "shift";
if (cell->type.in(TW($and), TW($_AND_))) btor_op = "and";
if (cell->type.in(TW($or), TW($_OR_))) btor_op = "or";
if (cell->type.in(TW($xor), TW($_XOR_))) btor_op = "xor";
if (cell->type == TW($concat)) btor_op = "concat";
if (cell->type == TW($_NAND_)) btor_op = "nand";
if (cell->type == TW($_NOR_)) btor_op = "nor";
if (cell->type.in(TW($xnor), TW($_XNOR_))) btor_op = "xnor";
log_assert(!btor_op.empty());
int width_ay = std::max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::Y)));
@ -309,17 +309,17 @@ struct BtorWorker
if (btor_op == "shift" && !b_signed)
btor_op = "srl";
if (cell->type.in(ID($shl), ID($sshl), ID($shr), ID($sshr)))
if (cell->type.in(TW($shl), TW($sshl), TW($shr), TW($sshr)))
b_signed = false;
if (cell->type == ID($sshr) && !a_signed)
if (cell->type == TW($sshr) && !a_signed)
btor_op = "srl";
int sid = get_bv_sid(width);
int nid;
int nid_a;
if (cell->type.in(ID($shl), ID($shr), ID($shift), ID($shiftx)) && a_signed && width_ay < width) {
if (cell->type.in(TW($shl), TW($shr), TW($shift), TW($shiftx)) && a_signed && width_ay < width) {
// sign-extend A up to the width of Y
int nid_a_padded = get_sig_nid(cell->getPort(TW::A), width_ay, a_signed);
@ -371,17 +371,17 @@ struct BtorWorker
goto okay;
}
if (cell->type.in(ID($div), ID($mod), ID($modfloor)))
if (cell->type.in(TW($div), TW($mod), TW($modfloor)))
{
bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
string btor_op;
if (cell->type == ID($div)) btor_op = "div";
if (cell->type == TW($div)) btor_op = "div";
// "rem" = truncating modulo
if (cell->type == ID($mod)) btor_op = "rem";
if (cell->type == TW($mod)) btor_op = "rem";
// "mod" = flooring modulo
if (cell->type == ID($modfloor)) {
if (cell->type == TW($modfloor)) {
// "umod" doesn't exist because it's the same as "urem"
btor_op = a_signed || b_signed ? "mod" : "rem";
}
@ -411,7 +411,7 @@ struct BtorWorker
goto okay;
}
if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
if (cell->type.in(TW($_ANDNOT_), TW($_ORNOT_)))
{
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(TW::A));
@ -420,12 +420,12 @@ struct BtorWorker
int nid1 = next_nid++;
int nid2 = next_nid++;
if (cell->type == ID($_ANDNOT_)) {
if (cell->type == TW($_ANDNOT_)) {
btorf("%d not %d %d\n", nid1, sid, nid_b);
btorf("%d and %d %d %d%s\n", nid2, sid, nid_a, nid1, getinfo(cell));
}
if (cell->type == ID($_ORNOT_)) {
if (cell->type == TW($_ORNOT_)) {
btorf("%d not %d %d\n", nid1, sid, nid_b);
btorf("%d or %d %d %d%s\n", nid2, sid, nid_a, nid1, getinfo(cell));
}
@ -435,7 +435,7 @@ struct BtorWorker
goto okay;
}
if (cell->type.in(ID($_OAI3_), ID($_AOI3_)))
if (cell->type.in(TW($_OAI3_), TW($_AOI3_)))
{
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(TW::A));
@ -446,13 +446,13 @@ struct BtorWorker
int nid2 = next_nid++;
int nid3 = next_nid++;
if (cell->type == ID($_OAI3_)) {
if (cell->type == TW($_OAI3_)) {
btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
btorf("%d and %d %d %d\n", nid2, sid, nid1, nid_c);
btorf("%d not %d %d%s\n", nid3, sid, nid2, getinfo(cell));
}
if (cell->type == ID($_AOI3_)) {
if (cell->type == TW($_AOI3_)) {
btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
btorf("%d or %d %d %d\n", nid2, sid, nid1, nid_c);
btorf("%d not %d %d%s\n", nid3, sid, nid2, getinfo(cell));
@ -463,7 +463,7 @@ struct BtorWorker
goto okay;
}
if (cell->type.in(ID($_OAI4_), ID($_AOI4_)))
if (cell->type.in(TW($_OAI4_), TW($_AOI4_)))
{
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(TW::A));
@ -476,14 +476,14 @@ struct BtorWorker
int nid3 = next_nid++;
int nid4 = next_nid++;
if (cell->type == ID($_OAI4_)) {
if (cell->type == TW($_OAI4_)) {
btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
btorf("%d or %d %d %d\n", nid2, sid, nid_c, nid_d);
btorf("%d and %d %d %d\n", nid3, sid, nid1, nid2);
btorf("%d not %d %d%s\n", nid4, sid, nid3, getinfo(cell));
}
if (cell->type == ID($_AOI4_)) {
if (cell->type == TW($_AOI4_)) {
btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
btorf("%d and %d %d %d\n", nid2, sid, nid_c, nid_d);
btorf("%d or %d %d %d\n", nid3, sid, nid1, nid2);
@ -495,15 +495,15 @@ struct BtorWorker
goto okay;
}
if (cell->type.in(ID($lt), ID($le), ID($eq), ID($eqx), ID($ne), ID($nex), ID($ge), ID($gt)))
if (cell->type.in(TW($lt), TW($le), TW($eq), TW($eqx), TW($ne), TW($nex), TW($ge), TW($gt)))
{
string btor_op;
if (cell->type == ID($lt)) btor_op = "lt";
if (cell->type == ID($le)) btor_op = "lte";
if (cell->type.in(ID($eq), ID($eqx))) btor_op = "eq";
if (cell->type.in(ID($ne), ID($nex))) btor_op = "neq";
if (cell->type == ID($ge)) btor_op = "gte";
if (cell->type == ID($gt)) btor_op = "gt";
if (cell->type == TW($lt)) btor_op = "lt";
if (cell->type == TW($le)) btor_op = "lte";
if (cell->type.in(TW($eq), TW($eqx))) btor_op = "eq";
if (cell->type.in(TW($ne), TW($nex))) btor_op = "neq";
if (cell->type == TW($ge)) btor_op = "gte";
if (cell->type == TW($gt)) btor_op = "gt";
log_assert(!btor_op.empty());
int width = 1;
@ -518,7 +518,7 @@ struct BtorWorker
int nid_b = get_sig_nid(cell->getPort(TW::B), width, b_signed);
int nid = next_nid++;
if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt))) {
if (cell->type.in(TW($lt), TW($le), TW($ge), TW($gt))) {
btorf("%d %c%s %d %d %d%s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op, sid, nid_a, nid_b, getinfo(cell));
} else {
btorf("%d %s %d %d %d%s\n", nid, btor_op, sid, nid_a, nid_b, getinfo(cell));
@ -537,11 +537,11 @@ struct BtorWorker
goto okay;
}
if (cell->type.in(ID($not), ID($neg), ID($_NOT_), ID($pos), ID($buf), ID($_BUF_)))
if (cell->type.in(TW($not), TW($neg), TW($_NOT_), TW($pos), TW($buf), TW($_BUF_)))
{
string btor_op;
if (cell->type.in(ID($not), ID($_NOT_))) btor_op = "not";
if (cell->type == ID($neg)) btor_op = "neg";
if (cell->type.in(TW($not), TW($_NOT_))) btor_op = "not";
if (cell->type == TW($neg)) btor_op = "neg";
int width = std::max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::Y)));
@ -551,7 +551,7 @@ struct BtorWorker
// the $pos/$buf cells just pass through, all other cells need an actual operation applied
int nid = nid_a;
if (!cell->type.in(ID($pos), ID($buf), ID($_BUF_)))
if (!cell->type.in(TW($pos), TW($buf), TW($_BUF_)))
{
log_assert(!btor_op.empty());
int sid = get_bv_sid(width);
@ -570,12 +570,12 @@ struct BtorWorker
goto okay;
}
if (cell->type.in(ID($logic_and), ID($logic_or), ID($logic_not)))
if (cell->type.in(TW($logic_and), TW($logic_or), TW($logic_not)))
{
string btor_op;
if (cell->type == ID($logic_and)) btor_op = "and";
if (cell->type == ID($logic_or)) btor_op = "or";
if (cell->type == ID($logic_not)) btor_op = "not";
if (cell->type == TW($logic_and)) btor_op = "and";
if (cell->type == TW($logic_or)) btor_op = "or";
if (cell->type == TW($logic_not)) btor_op = "not";
log_assert(!btor_op.empty());
int sid = get_bv_sid(1);
@ -614,12 +614,12 @@ struct BtorWorker
goto okay;
}
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($reduce_xor), ID($reduce_xnor)))
if (cell->type.in(TW($reduce_and), TW($reduce_or), TW($reduce_bool), TW($reduce_xor), TW($reduce_xnor)))
{
string btor_op;
if (cell->type == ID($reduce_and)) btor_op = "redand";
if (cell->type.in(ID($reduce_or), ID($reduce_bool))) btor_op = "redor";
if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) btor_op = "redxor";
if (cell->type == TW($reduce_and)) btor_op = "redand";
if (cell->type.in(TW($reduce_or), TW($reduce_bool))) btor_op = "redor";
if (cell->type.in(TW($reduce_xor), TW($reduce_xnor))) btor_op = "redxor";
log_assert(!btor_op.empty());
int sid = get_bv_sid(1);
@ -627,7 +627,7 @@ struct BtorWorker
int nid = next_nid++;
if (cell->type == ID($reduce_xnor)) {
if (cell->type == TW($reduce_xnor)) {
int nid2 = next_nid++;
btorf("%d %s %d %d%s\n", nid, btor_op, sid, nid_a, getinfo(cell));
btorf("%d not %d %d\n", nid2, sid, nid);
@ -650,7 +650,7 @@ struct BtorWorker
goto okay;
}
if (cell->type.in(ID($mux), ID($_MUX_), ID($_NMUX_)))
if (cell->type.in(TW($mux), TW($_MUX_), TW($_NMUX_)))
{
SigSpec sig_a = sigmap(cell->getPort(TW::A));
SigSpec sig_b = sigmap(cell->getPort(TW::B));
@ -664,7 +664,7 @@ struct BtorWorker
int sid = get_bv_sid(GetSize(sig_y));
int nid = next_nid++;
if (cell->type == ID($_NMUX_)) {
if (cell->type == TW($_NMUX_)) {
int tmp = nid;
nid = next_nid++;
btorf("%d ite %d %d %d %d\n", tmp, sid, nid_s, nid_b, nid_a);
@ -677,7 +677,7 @@ struct BtorWorker
goto okay;
}
if (cell->type == ID($pmux))
if (cell->type == TW($pmux))
{
SigSpec sig_a = sigmap(cell->getPort(TW::A));
SigSpec sig_b = sigmap(cell->getPort(TW::B));
@ -703,21 +703,21 @@ struct BtorWorker
goto okay;
}
if (cell->type.in(ID($dff), ID($ff), ID($anyinit), ID($_DFF_P_), ID($_DFF_N), ID($_FF_)))
if (cell->type.in(TW($dff), TW($ff), TW($anyinit), TW($_DFF_P_), TW($_DFF_N), TW($_FF_)))
{
SigSpec sig_d = sigmap(cell->getPort(TW::D));
SigSpec sig_q = sigmap(cell->getPort(TW::Q));
if ((!info_filename.empty() || ywmap_json.active()) && cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_)))
if ((!info_filename.empty() || ywmap_json.active()) && cell->type.in(TW($dff), TW($_DFF_P_), TW($_DFF_N_)))
{
SigSpec sig_c = sigmap(cell->getPort(cell->type == ID($dff) ? TW::CLK : TW::C));
SigSpec sig_c = sigmap(cell->getPort(cell->type == TW($dff) ? TW::CLK : TW::C));
int nid = get_sig_nid(sig_c);
bool negedge = false;
if (cell->type == ID($_DFF_N_))
if (cell->type == TW($_DFF_N_))
negedge = true;
if (cell->type == ID($dff) && !cell->getParam(ID::CLK_POLARITY).as_bool())
if (cell->type == TW($dff) && !cell->getParam(ID::CLK_POLARITY).as_bool())
negedge = true;
if (!info_filename.empty())
@ -756,7 +756,7 @@ struct BtorWorker
if (symbol.empty() || (!print_internal_names && symbol[0] == '$'))
btorf("%d state %d\n", nid, sid);
else
btorf("%d state %d %s\n", nid, sid, symbol.unescape());
btorf("%d state %d %s\n", nid, sid, design->twines.unescaped_str(symbol));
if (cell->get_bool_attribute(ID(clk2fflogic)))
ywmap_state(cell->getPort(TW::D)); // For a clk2fflogic FF the named signal is the D input not the Q output
@ -775,7 +775,7 @@ struct BtorWorker
goto okay;
}
if (cell->type.in(ID($anyconst), ID($anyseq)))
if (cell->type.in(TW($anyconst), TW($anyseq)))
{
SigSpec sig_y = sigmap(cell->getPort(TW::Y));
@ -786,7 +786,7 @@ struct BtorWorker
ywmap_state(sig_y);
if (cell->type == ID($anyconst)) {
if (cell->type == TW($anyconst)) {
int nid2 = next_nid++;
btorf("%d next %d %d %d\n", nid2, sid, nid, nid);
}
@ -795,7 +795,7 @@ struct BtorWorker
goto okay;
}
if (cell->type == ID($initstate))
if (cell->type == TW($initstate))
{
SigSpec sig_y = sigmap(cell->getPort(TW::Y));
@ -834,12 +834,12 @@ struct BtorWorker
if (asyncwr && syncwr)
log_error("Memory %s.%s has mixed async/sync write ports.\n",
module, mem->memid.unescape());
module, design->twines.unescaped_str(mem->memid));
for (auto &port : mem->rd_ports) {
if (port.clk_enable)
log_error("Memory %s.%s has sync read ports. Please use memory_nordff to convert them first.\n",
module, mem->memid.unescape());
module, design->twines.unescaped_str(mem->memid));
}
int data_sid = get_bv_sid(mem->width);
@ -901,7 +901,7 @@ struct BtorWorker
if (mem->memid[0] == '$')
btorf("%d state %d\n", nid, sid);
else
btorf("%d state %d %s\n", nid, sid, mem->memid.unescape());
btorf("%d state %d %s\n", nid, sid, design->twines.unescaped_str(mem->memid));
ywmap_state(cell);
@ -976,15 +976,15 @@ struct BtorWorker
goto okay;
}
if (cell->type.in(ID($dffe), ID($sdff), ID($sdffe), ID($sdffce)) || cell->type.str().substr(0, 6) == "$_SDFF" || (cell->type.str().substr(0, 6) == "$_DFFE" && cell->type.str().size() == 10)) {
if (cell->type.in(TW($dffe), TW($sdff), TW($sdffe), TW($sdffce)) || cell->type.str().substr(0, 6) == "$_SDFF" || (cell->type.str().substr(0, 6) == "$_DFFE" && cell->type.str().size() == 10)) {
log_error("Unsupported cell type %s for cell %s.%s -- please run `dffunmap` before `write_btor`.\n",
cell->type.unescape(), module, cell);
}
if (cell->type.in(ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($dffsr), ID($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF" || cell->type.str().substr(0, 7) == "$_ALDFF") {
if (cell->type.in(TW($adff), TW($adffe), TW($aldff), TW($aldffe), TW($dffsr), TW($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF" || cell->type.str().substr(0, 7) == "$_ALDFF") {
log_error("Unsupported cell type %s for cell %s.%s -- please run `async2sync; dffunmap` or `clk2fflogic` before `write_btor`.\n",
cell->type.unescape(), module, cell);
}
if (cell->type.in(ID($sr), ID($dlatch), ID($adlatch), ID($dlatchsr)) || cell->type.str().substr(0, 8) == "$_DLATCH" || cell->type.str().substr(0, 5) == "$_SR_") {
if (cell->type.in(TW($sr), TW($dlatch), TW($adlatch), TW($dlatchsr)) || cell->type.str().substr(0, 8) == "$_DLATCH" || cell->type.str().substr(0, 5) == "$_SR_") {
log_error("Unsupported cell type %s for cell %s.%s -- please run `clk2fflogic` before `write_btor`.\n",
cell->type.unescape(), module, cell);
}
@ -1296,7 +1296,7 @@ struct BtorWorker
for (auto cell : module->cells())
{
if (cell->type == ID($assume))
if (cell->type == TW($assume))
{
btorf_push(cell->module->design->twines.str(cell->meta_->name));
@ -1316,7 +1316,7 @@ struct BtorWorker
btorf_pop(cell->module->design->twines.str(cell->meta_->name));
}
if (cell->type == ID($assert))
if (cell->type == TW($assert))
{
btorf_push(cell->module->design->twines.str(cell->meta_->name));
@ -1345,7 +1345,7 @@ struct BtorWorker
btorf_pop(cell->module->design->twines.str(cell->meta_->name));
}
if (cell->type == ID($cover) && cover_mode)
if (cell->type == TW($cover) && cover_mode)
{
btorf_push(cell->module->design->twines.str(cell->meta_->name));
@ -1417,7 +1417,7 @@ struct BtorWorker
int nid = it.first;
Mem *mem = it.second;
btorf_push(stringf("next %s", mem->memid.unescape()));
btorf_push(stringf("next %s", design->twines.unescaped_str(mem->memid)));
int abits = ceil_log2(mem->size);
@ -1465,7 +1465,7 @@ struct BtorWorker
int nid2 = next_nid++;
btorf("%d next %d %d %d%s\n", nid2, sid, nid, nid_head, getinfo(mem));
btorf_pop(stringf("next %s", mem->memid.unescape()));
btorf_pop(stringf("next %s", design->twines.unescaped_str(mem->memid)));
}
}

70
backends/cxxrtl/cxxrtl_backend.cc
View file

@ -177,39 +177,39 @@ struct Scheduler {
bool is_unary_cell(TwineRef type)
{
return type.in(
ID($not), ID($logic_not), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
ID($pos), ID($neg));
TW($not), TW($logic_not), TW($reduce_and), TW($reduce_or), TW($reduce_xor), TW($reduce_xnor), TW($reduce_bool),
TW($pos), TW($neg));
}
bool is_binary_cell(TwineRef type)
{
return type.in(
ID($and), ID($or), ID($xor), ID($xnor), ID($logic_and), ID($logic_or),
ID($shl), ID($sshl), ID($shr), ID($sshr), ID($shift), ID($shiftx),
ID($eq), ID($ne), ID($eqx), ID($nex), ID($gt), ID($ge), ID($lt), ID($le),
ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($modfloor), ID($divfloor));
TW($and), TW($or), TW($xor), TW($xnor), TW($logic_and), TW($logic_or),
TW($shl), TW($sshl), TW($shr), TW($sshr), TW($shift), TW($shiftx),
TW($eq), TW($ne), TW($eqx), TW($nex), TW($gt), TW($ge), TW($lt), TW($le),
TW($add), TW($sub), TW($mul), TW($div), TW($mod), TW($modfloor), TW($divfloor));
}
bool is_extending_cell(TwineRef type)
{
return !type.in(
ID($logic_not), ID($logic_and), ID($logic_or),
ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool));
TW($logic_not), TW($logic_and), TW($logic_or),
TW($reduce_and), TW($reduce_or), TW($reduce_xor), TW($reduce_xnor), TW($reduce_bool));
}
bool is_inlinable_cell(TwineRef type)
{
return is_unary_cell(type) || is_binary_cell(type) || type.in(
ID($mux), ID($concat), ID($slice), ID($pmux), ID($bmux), ID($demux), ID($bwmux));
TW($mux), TW($concat), TW($slice), TW($pmux), TW($bmux), TW($demux), TW($bwmux));
}
bool is_ff_cell(TwineRef type)
{
return type.in(
ID($dff), ID($dffe), ID($sdff), ID($sdffe), ID($sdffce),
ID($adff), ID($adffe), ID($dffsr), ID($dffsre),
ID($aldff), ID($aldffe),
ID($dlatch), ID($adlatch), ID($dlatchsr), ID($sr));
TW($dff), TW($dffe), TW($sdff), TW($sdffe), TW($sdffce),
TW($adff), TW($adffe), TW($dffsr), TW($dffsre),
TW($aldff), TW($aldffe),
TW($dlatch), TW($adlatch), TW($dlatchsr), TW($sr));
}
bool is_internal_cell(TwineRef type)
@ -219,7 +219,7 @@ bool is_internal_cell(TwineRef type)
bool is_effectful_cell(TwineRef type)
{
return type.in(ID($print), ID($check));
return type.in(TW($print), TW($check));
}
bool is_cxxrtl_blackbox_cell(const RTLIL::Cell *cell)
@ -1169,7 +1169,7 @@ struct CxxrtlWorker {
dump_sigspec_rhs(cell->getPort(TW::B), for_debug);
f << ")";
// Muxes
} else if (cell->type == ID($mux)) {
} else if (cell->type == TW($mux)) {
f << "(";
dump_sigspec_rhs(cell->getPort(TW::S), for_debug);
f << " ? ";
@ -1178,7 +1178,7 @@ struct CxxrtlWorker {
dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
f << ")";
// Parallel (one-hot) muxes
} else if (cell->type == ID($pmux)) {
} else if (cell->type == TW($pmux)) {
int width = cell->getParam(ID::WIDTH).as_int();
int s_width = cell->getParam(ID::S_WIDTH).as_int();
for (int part = 0; part < s_width; part++) {
@ -1193,7 +1193,7 @@ struct CxxrtlWorker {
f << ")";
}
// Big muxes
} else if (cell->type == ID($bmux)) {
} else if (cell->type == TW($bmux)) {
dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
f << ".bmux<";
f << cell->getParam(ID::WIDTH).as_int();
@ -1201,7 +1201,7 @@ struct CxxrtlWorker {
dump_sigspec_rhs(cell->getPort(TW::S), for_debug);
f << ").val()";
// Bitwise muxes
} else if (cell->type == ID($bwmux)) {
} else if (cell->type == TW($bwmux)) {
dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
f << ".bwmux(";
dump_sigspec_rhs(cell->getPort(TW::B), for_debug);
@ -1209,7 +1209,7 @@ struct CxxrtlWorker {
dump_sigspec_rhs(cell->getPort(TW::S), for_debug);
f << ").val()";
// Demuxes
} else if (cell->type == ID($demux)) {
} else if (cell->type == TW($demux)) {
dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
f << ".demux<";
f << GetSize(cell->getPort(TW::Y));
@ -1217,13 +1217,13 @@ struct CxxrtlWorker {
dump_sigspec_rhs(cell->getPort(TW::S), for_debug);
f << ").val()";
// Concats
} else if (cell->type == ID($concat)) {
} else if (cell->type == TW($concat)) {
dump_sigspec_rhs(cell->getPort(TW::B), for_debug);
f << ".concat(";
dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
f << ").val()";
// Slices
} else if (cell->type == ID($slice)) {
} else if (cell->type == TW($slice)) {
dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
f << ".slice<";
f << cell->getParam(ID::OFFSET).as_int() + cell->getParam(ID::Y_WIDTH).as_int() - 1;
@ -1333,9 +1333,9 @@ struct CxxrtlWorker {
f << indent << "static const metadata_map attributes = ";
dump_metadata_map(cell->attributes);
f << ";\n";
if (cell->type == ID($print)) {
if (cell->type == TW($print)) {
f << indent << "performer->on_print(formatter, attributes);\n";
} else if (cell->type == ID($check)) {
} else if (cell->type == TW($check)) {
std::string flavor = cell->getParam(ID::FLAVOR).decode_string();
f << indent << "performer->on_check(";
if (flavor == "assert")
@ -1354,9 +1354,9 @@ struct CxxrtlWorker {
dec_indent();
f << indent << "} else {\n";
inc_indent();
if (cell->type == ID($print)) {
if (cell->type == TW($print)) {
f << indent << print_output << " << formatter();\n";
} else if (cell->type == ID($check)) {
} else if (cell->type == TW($check)) {
std::string flavor = cell->getParam(ID::FLAVOR).decode_string();
if (flavor == "assert" || flavor == "assume") {
f << indent << "if (!condition) {\n";
@ -1397,9 +1397,9 @@ struct CxxrtlWorker {
f << indent << "auto " << mangle(cell) << "_next = ";
dump_sigspec_rhs(cell->getPort(TW::EN));
f << ".concat(";
if (cell->type == ID($print))
if (cell->type == TW($print))
dump_sigspec_rhs(cell->getPort(TW::ARGS));
else if (cell->type == ID($check))
else if (cell->type == TW($check))
dump_sigspec_rhs(cell->getPort(TW::A));
else log_assert(false);
f << ").val();\n";
@ -1444,7 +1444,7 @@ struct CxxrtlWorker {
f << " = ";
dump_sigspec_rhs(cell->getPort(TW::D));
f << ";\n";
if (cell->hasPort(TW::EN) && cell->type != ID($sdffce)) {
if (cell->hasPort(TW::EN) && cell->type != TW($sdffce)) {
dec_indent();
f << indent << "}\n";
}
@ -1461,7 +1461,7 @@ struct CxxrtlWorker {
dec_indent();
f << indent << "}\n";
}
if (cell->hasPort(TW::EN) && cell->type == ID($sdffce)) {
if (cell->hasPort(TW::EN) && cell->type == TW($sdffce)) {
dec_indent();
f << indent << "}\n";
}
@ -1534,7 +1534,7 @@ struct CxxrtlWorker {
f << (cell->getParam(ID::CLR_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
}
// Internal cells
} else if (cell->type.in(ID($input_port), ID($output_port), ID($public))) {
} else if (cell->type.in(TW($input_port), TW($output_port), TW($public))) {
} else if (is_internal_cell(cell->type)) {
log_cmd_error("Unsupported internal cell `%s'.\n", cell->type);
// User cells
@ -2412,7 +2412,7 @@ struct CxxrtlWorker {
count_scopes++;
// If there were any submodules that were flattened, the module is also responsible for adding them.
for (auto cell : module->cells()) {
if (cell->type != ID($scopeinfo)) continue;
if (cell->type != TW($scopeinfo)) continue;
if (cell->getParam(ID::TYPE).decode_string() == "module") {
auto module_attrs = scopeinfo_attributes(cell, ScopeinfoAttrs::Module);
auto cell_attrs = scopeinfo_attributes(cell, ScopeinfoAttrs::Cell);
@ -2697,9 +2697,9 @@ struct CxxrtlWorker {
if (is_effectful_cell(cell->type)) {
if (cell->getParam(ID::TRG_ENABLE).as_bool() && cell->getParam(ID::TRG_WIDTH).as_int() == 0)
f << indent << "value<1> " << mangle(cell) << ";\n"; // async initial cell
if (!cell->getParam(ID::TRG_ENABLE).as_bool() && cell->type == ID($print))
if (!cell->getParam(ID::TRG_ENABLE).as_bool() && cell->type == TW($print))
f << indent << "value<" << (1 + cell->getParam(ID::ARGS_WIDTH).as_int()) << "> " << mangle(cell) << ";\n"; // {EN, ARGS}
if (!cell->getParam(ID::TRG_ENABLE).as_bool() && cell->type == ID($check))
if (!cell->getParam(ID::TRG_ENABLE).as_bool() && cell->type == TW($check))
f << indent << "value<2> " << mangle(cell) << ";\n"; // {EN, A}
}
if (is_internal_cell(cell->type))
@ -3017,7 +3017,7 @@ struct CxxrtlWorker {
if (cell_module &&
cell_module->get_blackbox_attribute() &&
!cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
log_cmd_error("External blackbox cell `%s' is not marked as a CXXRTL blackbox.\n", cell->type.unescape());
log_cmd_error("External blackbox cell `%s' is not marked as a CXXRTL blackbox.\n", cell->type.unescaped());
if (cell_module &&
cell_module->get_bool_attribute(ID(cxxrtl_blackbox)) &&
@ -3027,7 +3027,7 @@ struct CxxrtlWorker {
flow.add_node(cell);
// Various DFF cells are treated like posedge/negedge processes, see above for details.
if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($dffsr), ID($dffsre), ID($sdff), ID($sdffe), ID($sdffce))) {
if (cell->type.in(TW($dff), TW($dffe), TW($adff), TW($adffe), TW($aldff), TW($aldffe), TW($dffsr), TW($dffsre), TW($sdff), TW($sdffe), TW($sdffce))) {
if (is_valid_clock(cell->getPort(TW::CLK)))
register_edge_signal(sigmap, cell->getPort(TW::CLK),
cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);

10
backends/edif/edif.cc
View file

@ -30,9 +30,9 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
#define EDIF_DEF(_id) edif_names(_id.unescape(), true)
#define EDIF_DEFR(_id, _ren, _bl, _br) edif_names(_id.unescape(), true, _ren, _bl, _br)
#define EDIF_REF(_id) edif_names(_id.unescape(), false)
#define EDIF_DEF(_id) design->twines.unescaped_str(edif_names(_id), true)
#define EDIF_DEFR(_id, _ren, _bl, _br) design->twines.unescaped_str(edif_names(_id), true, _ren, _bl, _br)
#define EDIF_REF(_id) design->twines.unescaped_str(edif_names(_id), false)
#define EDIF_DEF_STR(_id) edif_names(RTLIL::unescape_id(_id), true)
#define EDIF_REF_STR(_id) edif_names(RTLIL::unescape_id(_id), false)
@ -216,7 +216,7 @@ struct EdifBackend : public Backend {
for (auto cell : module->cells())
{
if (cell->type == ID($scopeinfo))
if (cell->type == TW($scopeinfo))
continue;
if (design->module(cell->type) == nullptr || design->module(cell->type)->get_blackbox_attribute()) {
@ -321,7 +321,7 @@ struct EdifBackend : public Backend {
for (auto &dep : it.second)
if (module_deps.count(dep) > 0)
goto not_ready_yet;
// log("Next in topological sort: %s\n", it.first->name.unescape());
// log("Next in topological sort: %s\n", design->twines.unescaped_str(it.first->name));
sorted_modules.push_back(it.first);
not_ready_yet:;
}

100
backends/firrtl/firrtl.cc
View file

@ -82,7 +82,7 @@ const char *make_id(IdString id)
if (namecache.count(id) != 0)
return namecache.at(id).c_str();
string new_id = id.unescape();
string new_id = design->twines.unescaped_str(id);
for (int i = 0; i < GetSize(new_id); i++)
{
@ -599,7 +599,7 @@ struct FirrtlWorker
string y_id = make_id(cell->name);
std::string cellFileinfo = getFileinfo(cell);
if (cell->type.in(ID($not), ID($logic_not), ID($_NOT_), ID($neg), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_bool), ID($reduce_xnor)))
if (cell->type.in(TW($not), TW($logic_not), TW($_NOT_), TW($neg), TW($reduce_and), TW($reduce_or), TW($reduce_xor), TW($reduce_bool), TW($reduce_xnor)))
{
string a_expr = make_expr(cell->getPort(TW::A));
wire_decls.push_back(stringf("%swire %s: UInt<%d> %s\n", indent, y_id, y_width, cellFileinfo));
@ -609,29 +609,29 @@ struct FirrtlWorker
}
// Don't use the results of logical operations (a single bit) to control padding
if (!(cell->type.in(ID($eq), ID($eqx), ID($gt), ID($ge), ID($lt), ID($le), ID($ne), ID($nex), ID($reduce_bool), ID($logic_not)) && y_width == 1) ) {
if (!(cell->type.in(TW($eq), TW($eqx), TW($gt), TW($ge), TW($lt), TW($le), TW($ne), TW($nex), TW($reduce_bool), TW($logic_not)) && y_width == 1) ) {
a_expr = stringf("pad(%s, %d)", a_expr, y_width);
}
// Assume the FIRRTL width is a single bit.
firrtl_width = 1;
if (cell->type.in(ID($not), ID($_NOT_))) primop = "not";
else if (cell->type == ID($neg)) {
if (cell->type.in(TW($not), TW($_NOT_))) primop = "not";
else if (cell->type == TW($neg)) {
primop = "neg";
firrtl_is_signed = true; // Result of "neg" is signed (an SInt).
firrtl_width = a_width;
} else if (cell->type == ID($logic_not)) {
} else if (cell->type == TW($logic_not)) {
primop = "eq";
a_expr = stringf("%s, UInt(0)", a_expr);
}
else if (cell->type == ID($reduce_and)) primop = "andr";
else if (cell->type == ID($reduce_or)) primop = "orr";
else if (cell->type == ID($reduce_xor)) primop = "xorr";
else if (cell->type == ID($reduce_xnor)) {
else if (cell->type == TW($reduce_and)) primop = "andr";
else if (cell->type == TW($reduce_or)) primop = "orr";
else if (cell->type == TW($reduce_xor)) primop = "xorr";
else if (cell->type == TW($reduce_xnor)) {
primop = "not";
a_expr = stringf("xorr(%s)", a_expr);
}
else if (cell->type == ID($reduce_bool)) {
else if (cell->type == TW($reduce_bool)) {
primop = "neq";
// Use the sign of the a_expr and its width as the type (UInt/SInt) and width of the comparand.
a_expr = stringf("%s, %cInt<%d>(0)", a_expr, a_signed ? 'S' : 'U', a_width);
@ -647,9 +647,9 @@ struct FirrtlWorker
continue;
}
if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($xor), ID($_XOR_), ID($xnor), ID($and), ID($_AND_), ID($or), ID($_OR_), ID($eq), ID($eqx),
ID($gt), ID($ge), ID($lt), ID($le), ID($ne), ID($nex), ID($shr), ID($sshr), ID($sshl), ID($shl),
ID($logic_and), ID($logic_or), ID($pow)))
if (cell->type.in(TW($add), TW($sub), TW($mul), TW($div), TW($mod), TW($xor), TW($_XOR_), TW($xnor), TW($and), TW($_AND_), TW($or), TW($_OR_), TW($eq), TW($eqx),
TW($gt), TW($ge), TW($lt), TW($le), TW($ne), TW($nex), TW($shr), TW($sshr), TW($sshl), TW($shl),
TW($logic_and), TW($logic_or), TW($pow)))
{
string a_expr = make_expr(cell->getPort(TW::A));
string b_expr = make_expr(cell->getPort(TW::B));
@ -666,7 +666,7 @@ struct FirrtlWorker
}
// Shift amount is always unsigned, and needn't be padded to result width,
// otherwise, we need to cast the b_expr appropriately
if (b_signed && !cell->type.in(ID($shr), ID($sshr), ID($shl), ID($sshl), ID($pow))) {
if (b_signed && !cell->type.in(TW($shr), TW($sshr), TW($shl), TW($sshl), TW($pow))) {
b_expr = "asSInt(" + b_expr + ")";
// Expand the "B" operand to the result width
if (b_width < y_width) {
@ -677,7 +677,7 @@ struct FirrtlWorker
// For the arithmetic ops, expand operand widths to result widths befor performing the operation.
// This corresponds (according to iverilog) to what verilog compilers implement.
if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($xor), ID($_XOR_), ID($xnor), ID($and), ID($_AND_), ID($or), ID($_OR_)))
if (cell->type.in(TW($add), TW($sub), TW($mul), TW($div), TW($mod), TW($xor), TW($_XOR_), TW($xnor), TW($and), TW($_AND_), TW($or), TW($_OR_)))
{
if (a_width < y_width) {
a_expr = stringf("pad(%s, %d)", a_expr, y_width);
@ -692,79 +692,79 @@ struct FirrtlWorker
firrtl_width = a_width;
auto a_sig = cell->getPort(TW::A);
if (cell->type == ID($add)) {
if (cell->type == TW($add)) {
primop = "add";
firrtl_is_signed = a_signed | b_signed;
firrtl_width = max(a_width, b_width);
} else if (cell->type == ID($sub)) {
} else if (cell->type == TW($sub)) {
primop = "sub";
firrtl_is_signed = true;
int a_widthInc = (!a_signed && b_signed) ? 2 : (a_signed && !b_signed) ? 1 : 0;
int b_widthInc = (a_signed && !b_signed) ? 2 : (!a_signed && b_signed) ? 1 : 0;
firrtl_width = max(a_width + a_widthInc, b_width + b_widthInc);
} else if (cell->type == ID($mul)) {
} else if (cell->type == TW($mul)) {
primop = "mul";
firrtl_is_signed = a_signed | b_signed;
firrtl_width = a_width + b_width;
} else if (cell->type == ID($div)) {
} else if (cell->type == TW($div)) {
primop = "div";
firrtl_is_signed = a_signed | b_signed;
firrtl_width = a_width;
} else if (cell->type == ID($mod)) {
} else if (cell->type == TW($mod)) {
// "rem" = truncating modulo
primop = "rem";
firrtl_width = min(a_width, b_width);
} else if (cell->type.in(ID($and), ID($_AND_))) {
} else if (cell->type.in(TW($and), TW($_AND_))) {
primop = "and";
always_uint = true;
firrtl_width = max(a_width, b_width);
}
else if (cell->type.in(ID($or), ID($_OR_))) {
else if (cell->type.in(TW($or), TW($_OR_))) {
primop = "or";
always_uint = true;
firrtl_width = max(a_width, b_width);
}
else if (cell->type.in(ID($xor), ID($_XOR_))) {
else if (cell->type.in(TW($xor), TW($_XOR_))) {
primop = "xor";
always_uint = true;
firrtl_width = max(a_width, b_width);
}
else if (cell->type == ID($xnor)) {
else if (cell->type == TW($xnor)) {
primop = "xnor";
always_uint = true;
firrtl_width = max(a_width, b_width);
}
else if ((cell->type == ID($eq)) || (cell->type == ID($eqx))) {
else if ((cell->type == TW($eq)) || (cell->type == TW($eqx))) {
primop = "eq";
always_uint = true;
firrtl_width = 1;
}
else if ((cell->type == ID($ne)) || (cell->type == ID($nex))) {
else if ((cell->type == TW($ne)) || (cell->type == TW($nex))) {
primop = "neq";
always_uint = true;
firrtl_width = 1;
}
else if (cell->type == ID($gt)) {
else if (cell->type == TW($gt)) {
primop = "gt";
always_uint = true;
firrtl_width = 1;
}
else if (cell->type == ID($ge)) {
else if (cell->type == TW($ge)) {
primop = "geq";
always_uint = true;
firrtl_width = 1;
}
else if (cell->type == ID($lt)) {
else if (cell->type == TW($lt)) {
primop = "lt";
always_uint = true;
firrtl_width = 1;
}
else if (cell->type == ID($le)) {
else if (cell->type == TW($le)) {
primop = "leq";
always_uint = true;
firrtl_width = 1;
}
else if ((cell->type == ID($shl)) || (cell->type == ID($sshl))) {
else if ((cell->type == TW($shl)) || (cell->type == TW($sshl))) {
// FIRRTL will widen the result (y) by the amount of the shift.
// We'll need to offset this by extracting the un-widened portion as Verilog would do.
extract_y_bits = true;
@ -782,7 +782,7 @@ struct FirrtlWorker
firrtl_width = a_width + (1 << b_width) - 1;
}
}
else if ((cell->type == ID($shr)) || (cell->type == ID($sshr))) {
else if ((cell->type == TW($shr)) || (cell->type == TW($sshr))) {
// We don't need to extract a specific range of bits.
extract_y_bits = false;
// Is the shift amount constant?
@ -799,26 +799,26 @@ struct FirrtlWorker
// We'll need to do some special fixups if the source (and thus result) is signed.
if (firrtl_is_signed) {
// If this is a "logical" shift right, pretend the source is unsigned.
if (cell->type == ID($shr)) {
if (cell->type == TW($shr)) {
a_expr = "asUInt(" + a_expr + ")";
}
}
}
else if ((cell->type == ID($logic_and))) {
else if ((cell->type == TW($logic_and))) {
primop = "and";
a_expr = "neq(" + a_expr + ", UInt(0))";
b_expr = "neq(" + b_expr + ", UInt(0))";
always_uint = true;
firrtl_width = 1;
}
else if ((cell->type == ID($logic_or))) {
else if ((cell->type == TW($logic_or))) {
primop = "or";
a_expr = "neq(" + a_expr + ", UInt(0))";
b_expr = "neq(" + b_expr + ", UInt(0))";
always_uint = true;
firrtl_width = 1;
}
else if ((cell->type == ID($pow))) {
else if ((cell->type == TW($pow))) {
if (a_sig.is_fully_const() && a_sig.as_int() == 2) {
// We'll convert this to a shift. To simplify things, change the a_expr to "1"
// so we can use b_expr directly as a shift amount.
@ -878,7 +878,7 @@ struct FirrtlWorker
continue;
}
if (cell->type.in(ID($mux), ID($_MUX_)))
if (cell->type.in(TW($mux), TW($_MUX_)))
{
auto it = cell->parameters.find(ID::WIDTH);
int width = it == cell->parameters.end()? 1 : it->second.as_int();
@ -901,7 +901,7 @@ struct FirrtlWorker
continue;
}
if (cell->type.in(ID($dff)))
if (cell->type.in(TW($dff)))
{
bool clkpol = cell->parameters.at(ID::CLK_POLARITY).as_bool();
if (clkpol == false)
@ -919,7 +919,7 @@ struct FirrtlWorker
continue;
}
if (cell->type == ID($shiftx)) {
if (cell->type == TW($shiftx)) {
// assign y = a[b +: y_width];
// We'll extract the correct bits as part of the primop.
@ -940,7 +940,7 @@ struct FirrtlWorker
register_reverse_wire_map(y_id, cell->getPort(TW::Y));
continue;
}
if (cell->type == ID($shift)) {
if (cell->type == TW($shift)) {
// assign y = a >> b;
// where b may be negative
@ -966,7 +966,7 @@ struct FirrtlWorker
register_reverse_wire_map(y_id, cell->getPort(TW::Y));
continue;
}
if (cell->type == ID($pos)) {
if (cell->type == TW($pos)) {
// assign y = a;
// printCell(cell);
string a_expr = make_expr(cell->getPort(TW::A));
@ -981,9 +981,9 @@ struct FirrtlWorker
continue;
}
if (cell->type == ID($scopeinfo))
if (cell->type == TW($scopeinfo))
continue;
log_error("Cell type not supported: %s (%s.%s)\n", cell->type.unescape(), module, cell);
log_error("Cell type not supported: %s (%s.%s)\n", cell->type.unescaped(), module, cell);
}
for (auto &mem : memories) {
@ -991,10 +991,10 @@ struct FirrtlWorker
Const init_data = mem.get_init_data();
if (!init_data.is_fully_undef())
log_error("Memory with initialization data: %s.%s\n", module, mem.memid.unescape());
log_error("Memory with initialization data: %s.%s\n", module, design->twines.unescaped_str(mem.memid));
if (mem.start_offset != 0)
log_error("Memory with nonzero offset: %s.%s\n", module, mem.memid.unescape());
log_error("Memory with nonzero offset: %s.%s\n", module, design->twines.unescaped_str(mem.memid));
for (int i = 0; i < GetSize(mem.rd_ports); i++)
{
@ -1002,7 +1002,7 @@ struct FirrtlWorker
string port_name(stringf("%s.r%d", mem_id, i));
if (port.clk_enable)
log_error("Clocked read port %d on memory %s.%s.\n", i, module, mem.memid.unescape());
log_error("Clocked read port %d on memory %s.%s.\n", i, module, design->twines.unescaped_str(mem.memid));
std::ostringstream rpe;
@ -1023,12 +1023,12 @@ struct FirrtlWorker
string port_name(stringf("%s.w%d", mem_id, i));
if (!port.clk_enable)
log_error("Unclocked write port %d on memory %s.%s.\n", i, module, mem.memid.unescape());
log_error("Unclocked write port %d on memory %s.%s.\n", i, module, design->twines.unescaped_str(mem.memid));
if (!port.clk_polarity)
log_error("Negedge write port %d on memory %s.%s.\n", i, module, mem.memid.unescape());
log_error("Negedge write port %d on memory %s.%s.\n", i, module, design->twines.unescaped_str(mem.memid));
for (int i = 1; i < GetSize(port.en); i++)
if (port.en[0] != port.en[i])
log_error("Complex write enable on port %d on memory %s.%s.\n", i, module, mem.memid.unescape());
log_error("Complex write enable on port %d on memory %s.%s.\n", i, module, design->twines.unescaped_str(mem.memid));
std::ostringstream wpe;

6
backends/functional/cxx.cc
View file

@ -89,7 +89,7 @@ struct CxxStruct {
}
f.print("\n\t\ttemplate <typename T> void visit(T &&fn) {{\n");
for (auto p : types) {
f.print("\t\t\tfn(\"{}\", {});\n", p.first.unescape(), scope(p.first, p.first));
f.print("\t\t\tfn(\"{}\", {});\n", design->twines.unescaped_str(p.first), scope(p.first, p.first));
}
f.print("\t\t}}\n");
f.print("\t}};\n\n");
@ -151,8 +151,8 @@ template<class NodePrinter> struct CxxPrintVisitor : public Functional::Abstract
void arithmetic_shift_right(Node, Node a, Node b) override { print("{}.arithmetic_shift_right({})", a, b); }
void mux(Node, Node a, Node b, Node s) override { print("{2}.any() ? {1} : {0}", a, b, s); }
void constant(Node, RTLIL::Const const & value) override { print("{}", cxx_const(value)); }
void input(Node, IdString name, IdString kind) override { log_assert(kind == ID($input)); print("input.{}", input_struct[name]); }
void state(Node, IdString name, IdString kind) override { log_assert(kind == ID($state)); print("current_state.{}", state_struct[name]); }
void input(Node, IdString name, IdString kind) override { log_assert(kind == TW($input)); print("input.{}", input_struct[name]); }
void state(Node, IdString name, IdString kind) override { log_assert(kind == TW($state)); print("current_state.{}", state_struct[name]); }
void memory_read(Node, Node mem, Node addr) override { print("{}.read({})", mem, addr); }
void memory_write(Node, Node mem, Node addr, Node data) override { print("{}.write({}, {})", mem, addr, data); }
};

6
backends/functional/smtlib.cc
View file

@ -80,7 +80,7 @@ public:
SmtStruct(std::string name, SmtScope &scope) : scope(scope), name(name) {}
void insert(IdString field_name, SmtSort sort) {
field_names(field_name);
auto accessor = scope.unique_name("\\" + name + "_" + field_name.unescape());
auto accessor = scope.unique_name("\\" + name + "_" + design->twines.unescaped_str(field_name));
fields.emplace_back(Field{sort, accessor});
}
void write_definition(SExprWriter &w) {
@ -179,8 +179,8 @@ struct SmtPrintVisitor : public Functional::AbstractVisitor<SExpr> {
SExpr memory_read(Node, Node mem, Node addr) override { return list("select", n(mem), n(addr)); }
SExpr memory_write(Node, Node mem, Node addr, Node data) override { return list("store", n(mem), n(addr), n(data)); }
SExpr input(Node, IdString name, IdString kind) override { log_assert(kind == ID($input)); return input_struct.access("inputs", name); }
SExpr state(Node, IdString name, IdString kind) override { log_assert(kind == ID($state)); return state_struct.access("state", name); }
SExpr input(Node, IdString name, IdString kind) override { log_assert(kind == TW($input)); return input_struct.access("inputs", name); }
SExpr state(Node, IdString name, IdString kind) override { log_assert(kind == TW($state)); return state_struct.access("state", name); }
};
struct SmtModule {

8
backends/functional/smtlib_rosette.cc
View file

@ -180,8 +180,8 @@ struct SmtrPrintVisitor : public Functional::AbstractVisitor<SExpr> {
SExpr memory_read(Node, Node mem, Node addr) override { return list("list-ref-bv", n(mem), n(addr)); }
SExpr memory_write(Node, Node mem, Node addr, Node data) override { return list("list-set-bv", n(mem), n(addr), n(data)); }
SExpr input(Node, IdString name, IdString kind) override { log_assert(kind == ID($input)); return input_struct.access("inputs", name); }
SExpr state(Node, IdString name, IdString kind) override { log_assert(kind == ID($state)); return state_struct.access("state", name); }
SExpr input(Node, IdString name, IdString kind) override { log_assert(kind == TW($input)); return input_struct.access("inputs", name); }
SExpr state(Node, IdString name, IdString kind) override { log_assert(kind == TW($state)); return state_struct.access("state", name); }
};
struct SmtrModule {
@ -281,7 +281,7 @@ struct SmtrModule {
w.push();
w.open(list());
w.open(list("assoc-result"));
w << list("assoc", "\"" + input->name.unescape() + "\"", inputs_name);
w << list("assoc", "\"" + design->twines.unescaped_str(input->name) + "\"", inputs_name);
w.pop();
w.open(list("if", "assoc-result"));
w << list("cdr", "assoc-result");
@ -298,7 +298,7 @@ struct SmtrModule {
w << list(*output_helper_name, outputs_name);
w.open(list("list"));
for (auto output : ir.outputs()) {
w << list("cons", "\"" + output->name.unescape() + "\"", output_struct.access("outputs", output->name));
w << list("cons", "\"" + design->twines.unescaped_str(output->name) + "\"", output_struct.access("outputs", output->name));
}
w.pop();
}

6
backends/functional/test_generic.cc
View file

@ -146,11 +146,11 @@ struct FunctionalTestGeneric : public Pass
log("Dumping module `%s'.\n", module->name);
auto fir = Functional::IR::from_module(module);
for(auto node : fir)
std::cout << node.name().unescape() << " = " << node.to_string([](auto n) { return n.name().unescape(); }) << "\n";
std::cout << design->twines.unescaped_str(node.name()) << " = " << node.to_string([](auto n) { return design->twines.unescaped_str(n.name()); }) << "\n";
for(auto output : fir.all_outputs())
std::cout << output->kind.unescape() << " " << output->name.unescape() << " = " << output->value().name().unescape() << "\n";
std::cout << design->twines.unescaped_str(output->kind) << " " << design->twines.unescaped_str(output->name) << " = " << design->twines.unescaped_str(output->value().name()) << "\n";
for(auto state : fir.all_states())
std::cout << state->kind.unescape() << " " << state->name.unescape() << " = " << state->next_value().name().unescape() << "\n";
std::cout << design->twines.unescaped_str(state->kind) << " " << design->twines.unescaped_str(state->name) << " = " << design->twines.unescaped_str(state->next_value().name()) << "\n";
}
}
} FunctionalCxxBackend;

22
backends/intersynth/intersynth.cc
View file

@ -41,7 +41,7 @@ static std::string netname(std::set<std::string> &conntypes_code, std::set<std::
return stringf("CONST_%d_0x%x", sig.size(), sig.as_int());
}
return sig.as_wire()->name.unescape();
return design->twines.unescaped_str(sig.as_wire()->name);
}
struct IntersynthBackend : public Backend {
@ -151,8 +151,8 @@ struct IntersynthBackend : public Backend {
if (wire->port_input || wire->port_output) {
celltypes_code.insert(stringf("celltype !%s b%d %sPORT\n" "%s %s %d %s PORT\n",
wire->name.unescape(), wire->width, wire->port_input ? "*" : "",
wire->port_input ? "input" : "output", wire->name.unescape(), wire->width, wire->name.unescape()));
netlists_code += stringf("node %s %s PORT %s\n", wire->name.unescape(), wire->name.unescape(),
wire->port_input ? "input" : "output", design->twines.unescaped_str(wire->name), wire->width, design->twines.unescaped_str(wire->name)));
netlists_code += stringf("node %s %s PORT %s\n", design->twines.unescaped_str(wire->name), design->twines.unescaped_str(wire->name),
netname(conntypes_code, celltypes_code, constcells_code, sigmap(wire)).c_str());
}
}
@ -162,28 +162,28 @@ struct IntersynthBackend : public Backend {
{
std::string celltype_code, node_code;
if (!ct.cell_known(cell->type))
log_error("Found unknown cell type %s in module!\n", cell->type.unescape());
if (!ct.cell_known(cell->type_impl))
log_error("Found unknown cell type %s in module!\n", cell->type.unescaped());
celltype_code = stringf("celltype %s", cell->type.unescape());
node_code = stringf("node %s %s", cell->module->design->twines.str(cell->meta_->name), cell->type.unescape());
celltype_code = stringf("celltype %s", cell->type.unescaped());
node_code = stringf("node %s %s", cell->module->design->twines.str(cell->meta_->name), cell->type.unescaped());
for (auto &port : cell->connections()) {
RTLIL::SigSpec sig = sigmap(port.second);
if (sig.size() != 0) {
conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.size(), sig.size(), sig.size()));
std::string port_name = design->twines.str(port.first);
celltype_code += stringf(" b%d %s%s", sig.size(), ct.cell_output(cell->type, port.first) ? "*" : "", port_name.c_str());
celltype_code += stringf(" b%d %s%s", sig.size(), ct.cell_output(cell->type_impl, port.first) ? "*" : "", port_name.c_str());
node_code += stringf(" %s %s", port_name.c_str(), netname(conntypes_code, celltypes_code, constcells_code, sig));
}
}
for (auto &param : cell->parameters) {
celltype_code += stringf(" cfg:%d %s", int(param.second.size()), param.first.unescape());
celltype_code += stringf(" cfg:%d %s", int(param.second.size()), design->twines.unescaped_str(param.first));
if (param.second.size() != 32) {
node_code += stringf(" %s '", param.first.unescape());
node_code += stringf(" %s '", design->twines.unescaped_str(param.first));
for (int i = param.second.size()-1; i >= 0; i--)
node_code += param.second[i] == State::S1 ? "1" : "0";
} else
node_code += stringf(" %s 0x%x", param.first.unescape(), param.second.as_int());
node_code += stringf(" %s 0x%x", design->twines.unescaped_str(param.first), param.second.as_int());
}
celltypes_code.insert(celltype_code + "\n");

6
backends/jny/jny.cc
View file

@ -91,7 +91,7 @@ struct JnyWriter
{
_cells.clear();
for (auto cell : mod->cells()) {
const auto cell_type = escape_string(cell->type.unescape());
const auto cell_type = design->twines.unescaped_str(escape_string(cell->type));
if (_cells.find(cell_type) == _cells.end())
_cells.emplace(cell_type, std::vector<Cell*>());
@ -353,10 +353,10 @@ struct JnyWriter
f << stringf(",\n");
const auto param_val = param.second;
if (!param_val.empty()) {
f << stringf(" %s\"%s\": ", _indent, escape_string(param.first.unescape()));
f << stringf(" %s\"%s\": ", _indent, design->twines.unescaped_str(escape_string(param.first)));
write_param_val(param_val);
} else {
f << stringf(" %s\"%s\": true", _indent, escape_string(param.first.unescape()));
f << stringf(" %s\"%s\": true", _indent, design->twines.unescaped_str(escape_string(param.first)));
}
first_param = false;

4
backends/json/json.cc
View file

@ -76,7 +76,7 @@ struct JsonWriter
string get_name(IdString name)
{
return get_string(name.unescape());
return design->twines.unescaped_str(get_string(name));
}
string get_name(TwineRef name)
@ -205,7 +205,7 @@ struct JsonWriter
for (auto c : module->cells()) {
if (use_selection && !module->selected(c))
continue;
if (!scopeinfo_mode && c->type == ID($scopeinfo))
if (!scopeinfo_mode && c->type == TW($scopeinfo))
continue;
f << stringf("%s\n", first ? "" : ",");
f << stringf(" %s: {\n", get_name(c->name));

56
backends/simplec/simplec.cc
View file

@ -378,7 +378,7 @@ struct SimplecWorker
void eval_cell(HierDirtyFlags *work, Cell *cell)
{
if (cell->type.in(ID($_BUF_), ID($_NOT_)))
if (cell->type.in(TW($_BUF_), TW($_NOT_)))
{
SigBit a = sigmaps.at(work->module)(cell->getPort(TW::A));
SigBit y = sigmaps.at(work->module)(cell->getPort(TW::Y));
@ -386,18 +386,18 @@ struct SimplecWorker
string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
string expr;
if (cell->type == ID($_BUF_)) expr = a_expr;
if (cell->type == ID($_NOT_)) expr = "!" + a_expr;
if (cell->type == TW($_BUF_)) expr = a_expr;
if (cell->type == TW($_NOT_)) expr = "!" + a_expr;
log_assert(y.wire);
funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
stringf(" // %s (%s)", cell, cell->type.unescape()));
stringf(" // %s (%s)", cell, cell->type.unescaped()));
work->set_dirty(y);
return;
}
if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
if (cell->type.in(TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_), TW($_XOR_), TW($_XNOR_), TW($_ANDNOT_), TW($_ORNOT_)))
{
SigBit a = sigmaps.at(work->module)(cell->getPort(TW::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(TW::B));
@ -407,24 +407,24 @@ struct SimplecWorker
string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0";
string expr;
if (cell->type == ID($_AND_)) expr = stringf("%s & %s", a_expr, b_expr);
if (cell->type == ID($_NAND_)) expr = stringf("!(%s & %s)", a_expr, b_expr);
if (cell->type == ID($_OR_)) expr = stringf("%s | %s", a_expr, b_expr);
if (cell->type == ID($_NOR_)) expr = stringf("!(%s | %s)", a_expr, b_expr);
if (cell->type == ID($_XOR_)) expr = stringf("%s ^ %s", a_expr, b_expr);
if (cell->type == ID($_XNOR_)) expr = stringf("!(%s ^ %s)", a_expr, b_expr);
if (cell->type == ID($_ANDNOT_)) expr = stringf("%s & (!%s)", a_expr, b_expr);
if (cell->type == ID($_ORNOT_)) expr = stringf("%s | (!%s)", a_expr, b_expr);
if (cell->type == TW($_AND_)) expr = stringf("%s & %s", a_expr, b_expr);
if (cell->type == TW($_NAND_)) expr = stringf("!(%s & %s)", a_expr, b_expr);
if (cell->type == TW($_OR_)) expr = stringf("%s | %s", a_expr, b_expr);
if (cell->type == TW($_NOR_)) expr = stringf("!(%s | %s)", a_expr, b_expr);
if (cell->type == TW($_XOR_)) expr = stringf("%s ^ %s", a_expr, b_expr);
if (cell->type == TW($_XNOR_)) expr = stringf("!(%s ^ %s)", a_expr, b_expr);
if (cell->type == TW($_ANDNOT_)) expr = stringf("%s & (!%s)", a_expr, b_expr);
if (cell->type == TW($_ORNOT_)) expr = stringf("%s | (!%s)", a_expr, b_expr);
log_assert(y.wire);
funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
stringf(" // %s (%s)", cell, cell->type.unescape()));
stringf(" // %s (%s)", cell, cell->type.unescaped()));
work->set_dirty(y);
return;
}
if (cell->type.in(ID($_AOI3_), ID($_OAI3_)))
if (cell->type.in(TW($_AOI3_), TW($_OAI3_)))
{
SigBit a = sigmaps.at(work->module)(cell->getPort(TW::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(TW::B));
@ -436,18 +436,18 @@ struct SimplecWorker
string c_expr = c.wire ? util_get_bit(work->prefix + cid(c.wire->name), c.wire->width, c.offset) : c.data ? "1" : "0";
string expr;
if (cell->type == ID($_AOI3_)) expr = stringf("!((%s & %s) | %s)", a_expr, b_expr, c_expr);
if (cell->type == ID($_OAI3_)) expr = stringf("!((%s | %s) & %s)", a_expr, b_expr, c_expr);
if (cell->type == TW($_AOI3_)) expr = stringf("!((%s & %s) | %s)", a_expr, b_expr, c_expr);
if (cell->type == TW($_OAI3_)) expr = stringf("!((%s | %s) & %s)", a_expr, b_expr, c_expr);
log_assert(y.wire);
funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
stringf(" // %s (%s)", cell, cell->type.unescape()));
stringf(" // %s (%s)", cell, cell->type.unescaped()));
work->set_dirty(y);
return;
}
if (cell->type.in(ID($_AOI4_), ID($_OAI4_)))
if (cell->type.in(TW($_AOI4_), TW($_OAI4_)))
{
SigBit a = sigmaps.at(work->module)(cell->getPort(TW::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(TW::B));
@ -461,18 +461,18 @@ struct SimplecWorker
string d_expr = d.wire ? util_get_bit(work->prefix + cid(d.wire->name), d.wire->width, d.offset) : d.data ? "1" : "0";
string expr;
if (cell->type == ID($_AOI4_)) expr = stringf("!((%s & %s) | (%s & %s))", a_expr, b_expr, c_expr, d_expr);
if (cell->type == ID($_OAI4_)) expr = stringf("!((%s | %s) & (%s | %s))", a_expr, b_expr, c_expr, d_expr);
if (cell->type == TW($_AOI4_)) expr = stringf("!((%s & %s) | (%s & %s))", a_expr, b_expr, c_expr, d_expr);
if (cell->type == TW($_OAI4_)) expr = stringf("!((%s | %s) & (%s | %s))", a_expr, b_expr, c_expr, d_expr);
log_assert(y.wire);
funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
stringf(" // %s (%s)", cell, cell->type.unescape()));
stringf(" // %s (%s)", cell, cell->type.unescaped()));
work->set_dirty(y);
return;
}
if (cell->type.in(ID($_MUX_), ID($_NMUX_)))
if (cell->type.in(TW($_MUX_), TW($_NMUX_)))
{
SigBit a = sigmaps.at(work->module)(cell->getPort(TW::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(TW::B));
@ -485,18 +485,18 @@ struct SimplecWorker
// casts to bool are a workaround for CBMC bug (https://github.com/diffblue/cbmc/issues/933)
string expr = stringf("%s ? %s(bool)%s : %s(bool)%s", s_expr,
cell->type == ID($_NMUX_) ? "!" : "", b_expr,
cell->type == ID($_NMUX_) ? "!" : "", a_expr);
cell->type == TW($_NMUX_) ? "!" : "", b_expr,
cell->type == TW($_NMUX_) ? "!" : "", a_expr);
log_assert(y.wire);
funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
stringf(" // %s (%s)", cell, cell->type.unescape()));
stringf(" // %s (%s)", cell, cell->type.unescaped()));
work->set_dirty(y);
return;
}
log_error("No C model for %s available at the moment (FIXME).\n", cell->type.unescape());
log_error("No C model for %s available at the moment (FIXME).\n", cell->type.unescaped());
}
void eval_dirty(HierDirtyFlags *work)
@ -579,7 +579,7 @@ struct SimplecWorker
string hiername = work->log_prefix + "." + cell->module->design->twines.str(cell->meta_->name);
if (verbose)
log(" Evaluating %s (%s, best of %d).\n", hiername, cell->type.unescape(), GetSize(work->dirty_cells));
log(" Evaluating %s (%s, best of %d).\n", hiername, cell->type.unescaped(), GetSize(work->dirty_cells));
if (activated_cells.count(hiername))
reactivated_cells.insert(hiername);

188
backends/smt2/smt2.cc
View file

@ -60,7 +60,7 @@ struct Smt2Worker
const char *get_id(IdString n)
{
if (ids.count(n) == 0) {
std::string str = n.unescape();
std::string str = design->twines.unescaped_str(n);
for (int i = 0; i < GetSize(str); i++) {
if (str[i] == '\\')
str[i] = '/';
@ -196,8 +196,8 @@ struct Smt2Worker
continue;
}
bool is_input = ct.cell_input(cell->type, conn.first);
bool is_output = ct.cell_output(cell->type, conn.first);
bool is_input = ct.cell_input(cell->type_impl, conn.first);
bool is_output = ct.cell_output(cell->type_impl, conn.first);
if (is_output && !is_input)
for (auto bit : sigmap(conn.second)) {
@ -207,11 +207,11 @@ struct Smt2Worker
}
else if (is_output || !is_input)
log_error("Unsupported or unknown directionality on port %s of cell %s.%s (%s).\n",
module->design->twines.str(conn.first).c_str(), module, cell, cell->type.unescape());
module->design->twines.str(conn.first).c_str(), module, cell, cell->type.unescaped());
if (cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_)) && (conn.first == TW::CLK || conn.first == TW::C))
if (cell->type.in(TW($dff), TW($_DFF_P_), TW($_DFF_N_)) && (conn.first == TW::CLK || conn.first == TW::C))
{
bool posedge = (cell->type == ID($_DFF_N_)) || (cell->type == ID($dff) && cell->getParam(ID::CLK_POLARITY).as_bool());
bool posedge = (cell->type == TW($_DFF_N_)) || (cell->type == TW($dff) && cell->getParam(ID::CLK_POLARITY).as_bool());
for (auto bit : sigmap(conn.second)) {
if (posedge)
clock_posedge.insert(bit);
@ -546,7 +546,7 @@ struct Smt2Worker
{
if (verbose)
log("%*s=> export_cell %s (%s) [%s]\n", 2+2*GetSize(recursive_cells), "",
cell, cell->type.unescape(), exported_cells.count(cell) ? "old" : "new");
cell, cell->type.unescaped(), exported_cells.count(cell) ? "old" : "new");
if (recursive_cells.count(cell))
log_error("Found logic loop in module %s! See cell %s.\n", get_id(module), get_id(cell));
@ -557,7 +557,7 @@ struct Smt2Worker
exported_cells.insert(cell);
recursive_cells.insert(cell);
if (cell->type == ID($initstate))
if (cell->type == TW($initstate))
{
SigBit bit = sigmap(cell->getPort(TW::Y).as_bit());
decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool (|%s_is| state)) ; %s\n",
@ -567,7 +567,7 @@ struct Smt2Worker
return;
}
if (cell->type.in(ID($_FF_), ID($_DFF_P_), ID($_DFF_N_)))
if (cell->type.in(TW($_FF_), TW($_DFF_P_), TW($_DFF_N_)))
{
registers.insert(cell);
SigBit q_bit = cell->getPort(TW::Q);
@ -579,28 +579,28 @@ struct Smt2Worker
return;
}
if (cell->type == ID($_BUF_)) return export_gate(cell, "A");
if (cell->type == ID($_NOT_)) return export_gate(cell, "(not A)");
if (cell->type == ID($_AND_)) return export_gate(cell, "(and A B)");
if (cell->type == ID($_NAND_)) return export_gate(cell, "(not (and A B))");
if (cell->type == ID($_OR_)) return export_gate(cell, "(or A B)");
if (cell->type == ID($_NOR_)) return export_gate(cell, "(not (or A B))");
if (cell->type == ID($_XOR_)) return export_gate(cell, "(xor A B)");
if (cell->type == ID($_XNOR_)) return export_gate(cell, "(not (xor A B))");
if (cell->type == ID($_ANDNOT_)) return export_gate(cell, "(and A (not B))");
if (cell->type == ID($_ORNOT_)) return export_gate(cell, "(or A (not B))");
if (cell->type == ID($_MUX_)) return export_gate(cell, "(ite S B A)");
if (cell->type == ID($_NMUX_)) return export_gate(cell, "(not (ite S B A))");
if (cell->type == ID($_AOI3_)) return export_gate(cell, "(not (or (and A B) C))");
if (cell->type == ID($_OAI3_)) return export_gate(cell, "(not (and (or A B) C))");
if (cell->type == ID($_AOI4_)) return export_gate(cell, "(not (or (and A B) (and C D)))");
if (cell->type == ID($_OAI4_)) return export_gate(cell, "(not (and (or A B) (or C D)))");
if (cell->type == TW($_BUF_)) return export_gate(cell, "A");
if (cell->type == TW($_NOT_)) return export_gate(cell, "(not A)");
if (cell->type == TW($_AND_)) return export_gate(cell, "(and A B)");
if (cell->type == TW($_NAND_)) return export_gate(cell, "(not (and A B))");
if (cell->type == TW($_OR_)) return export_gate(cell, "(or A B)");
if (cell->type == TW($_NOR_)) return export_gate(cell, "(not (or A B))");
if (cell->type == TW($_XOR_)) return export_gate(cell, "(xor A B)");
if (cell->type == TW($_XNOR_)) return export_gate(cell, "(not (xor A B))");
if (cell->type == TW($_ANDNOT_)) return export_gate(cell, "(and A (not B))");
if (cell->type == TW($_ORNOT_)) return export_gate(cell, "(or A (not B))");
if (cell->type == TW($_MUX_)) return export_gate(cell, "(ite S B A)");
if (cell->type == TW($_NMUX_)) return export_gate(cell, "(not (ite S B A))");
if (cell->type == TW($_AOI3_)) return export_gate(cell, "(not (or (and A B) C))");
if (cell->type == TW($_OAI3_)) return export_gate(cell, "(not (and (or A B) C))");
if (cell->type == TW($_AOI4_)) return export_gate(cell, "(not (or (and A B) (and C D)))");
if (cell->type == TW($_OAI4_)) return export_gate(cell, "(not (and (or A B) (or C D)))");
// FIXME: $lut
if (bvmode)
{
if (cell->type.in(ID($ff), ID($dff)))
if (cell->type.in(TW($ff), TW($dff)))
{
registers.insert(cell);
int smtoffset = 0;
@ -615,9 +615,9 @@ struct Smt2Worker
return;
}
if (cell->type.in(ID($anyconst), ID($anyseq), ID($anyinit), ID($allconst), ID($allseq)))
if (cell->type.in(TW($anyconst), TW($anyseq), TW($anyinit), TW($allconst), TW($allseq)))
{
auto QY = cell->type == ID($anyinit) ? TW::Q : TW::Y;
auto QY = cell->type == TW($anyinit) ? TW::Q : TW::Y;
registers.insert(cell);
string infostr;
if (cell->has_attribute(ID::src)) {
@ -637,8 +637,8 @@ struct Smt2Worker
log("Wire %s is minimized\n", cell->getPort(QY).as_wire()->name.str());
}
bool init_only = cell->type.in(ID($anyconst), ID($anyinit), ID($allconst));
bool clk2fflogic = cell->type == ID($anyinit) && cell->get_bool_attribute(ID(clk2fflogic));
bool init_only = cell->type.in(TW($anyconst), TW($anyinit), TW($allconst));
bool clk2fflogic = cell->type == TW($anyinit) && cell->get_bool_attribute(ID(clk2fflogic));
int smtoffset = 0;
for (auto chunk : cell->getPort(clk2fflogic ? TW::D : QY).chunks()) {
if (chunk.is_wire())
@ -647,27 +647,27 @@ struct Smt2Worker
}
makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort(QY)), log_signal(cell->getPort(QY)));
if (cell->type == ID($anyseq))
if (cell->type == TW($anyseq))
ex_input_eq.push_back(stringf(" (= (|%s#%d| state) (|%s#%d| other_state))", get_id(module), idcounter, get_id(module), idcounter));
register_bv(cell->getPort(QY), idcounter++);
recursive_cells.erase(cell);
return;
}
if (cell->type == ID($and)) return export_bvop(cell, "(bvand A B)");
if (cell->type == ID($or)) return export_bvop(cell, "(bvor A B)");
if (cell->type == ID($xor)) return export_bvop(cell, "(bvxor A B)");
if (cell->type == ID($xnor)) return export_bvop(cell, "(bvxnor A B)");
if (cell->type == TW($and)) return export_bvop(cell, "(bvand A B)");
if (cell->type == TW($or)) return export_bvop(cell, "(bvor A B)");
if (cell->type == TW($xor)) return export_bvop(cell, "(bvxor A B)");
if (cell->type == TW($xnor)) return export_bvop(cell, "(bvxnor A B)");
if (cell->type == ID($bweqx)) return export_bvop(cell, "(bvxnor A B)", 'U');
if (cell->type == ID($bwmux)) return export_bvop(cell, "(bvor (bvand A (bvnot S)) (bvand B S))", 'U');
if (cell->type == TW($bweqx)) return export_bvop(cell, "(bvxnor A B)", 'U');
if (cell->type == TW($bwmux)) return export_bvop(cell, "(bvor (bvand A (bvnot S)) (bvand B S))", 'U');
if (cell->type == ID($shl)) return export_bvop(cell, "(bvshl A B)", 's');
if (cell->type == ID($shr)) return export_bvop(cell, "(bvlshr A B)", 's');
if (cell->type == ID($sshl)) return export_bvop(cell, "(bvshl A B)", 's');
if (cell->type == ID($sshr)) return export_bvop(cell, "(bvLshr A B)", 's');
if (cell->type == TW($shl)) return export_bvop(cell, "(bvshl A B)", 's');
if (cell->type == TW($shr)) return export_bvop(cell, "(bvlshr A B)", 's');
if (cell->type == TW($sshl)) return export_bvop(cell, "(bvshl A B)", 's');
if (cell->type == TW($sshr)) return export_bvop(cell, "(bvLshr A B)", 's');
if (cell->type.in(ID($shift), ID($shiftx))) {
if (cell->type.in(TW($shift), TW($shiftx))) {
if (cell->getParam(ID::B_SIGNED).as_bool()) {
return export_bvop(cell, stringf("(ite (bvsge P #b%0*d) "
"(bvlshr A B) (bvshl A (bvneg B)))",
@ -677,28 +677,28 @@ struct Smt2Worker
}
}
if (cell->type == ID($lt)) return export_bvop(cell, "(bvUlt A B)", 'b');
if (cell->type == ID($le)) return export_bvop(cell, "(bvUle A B)", 'b');
if (cell->type == ID($ge)) return export_bvop(cell, "(bvUge A B)", 'b');
if (cell->type == ID($gt)) return export_bvop(cell, "(bvUgt A B)", 'b');
if (cell->type == TW($lt)) return export_bvop(cell, "(bvUlt A B)", 'b');
if (cell->type == TW($le)) return export_bvop(cell, "(bvUle A B)", 'b');
if (cell->type == TW($ge)) return export_bvop(cell, "(bvUge A B)", 'b');
if (cell->type == TW($gt)) return export_bvop(cell, "(bvUgt A B)", 'b');
if (cell->type == ID($ne)) return export_bvop(cell, "(distinct A B)", 'b');
if (cell->type == ID($nex)) return export_bvop(cell, "(distinct A B)", 'b');
if (cell->type == ID($eq)) return export_bvop(cell, "(= A B)", 'b');
if (cell->type == ID($eqx)) return export_bvop(cell, "(= A B)", 'b');
if (cell->type == TW($ne)) return export_bvop(cell, "(distinct A B)", 'b');
if (cell->type == TW($nex)) return export_bvop(cell, "(distinct A B)", 'b');
if (cell->type == TW($eq)) return export_bvop(cell, "(= A B)", 'b');
if (cell->type == TW($eqx)) return export_bvop(cell, "(= A B)", 'b');
if (cell->type == ID($not)) return export_bvop(cell, "(bvnot A)");
if (cell->type == ID($pos)) return export_bvop(cell, "A");
if (cell->type == ID($neg)) return export_bvop(cell, "(bvneg A)");
if (cell->type == TW($not)) return export_bvop(cell, "(bvnot A)");
if (cell->type == TW($pos)) return export_bvop(cell, "A");
if (cell->type == TW($neg)) return export_bvop(cell, "(bvneg A)");
if (cell->type == ID($add)) return export_bvop(cell, "(bvadd A B)");
if (cell->type == ID($sub)) return export_bvop(cell, "(bvsub A B)");
if (cell->type == ID($mul)) return export_bvop(cell, "(bvmul A B)");
if (cell->type == ID($div)) return export_bvop(cell, "(bvUdiv A B)", 'd');
if (cell->type == TW($add)) return export_bvop(cell, "(bvadd A B)");
if (cell->type == TW($sub)) return export_bvop(cell, "(bvsub A B)");
if (cell->type == TW($mul)) return export_bvop(cell, "(bvmul A B)");
if (cell->type == TW($div)) return export_bvop(cell, "(bvUdiv A B)", 'd');
// "rem" = truncating modulo
if (cell->type == ID($mod)) return export_bvop(cell, "(bvUrem A B)", 'd');
if (cell->type == TW($mod)) return export_bvop(cell, "(bvUrem A B)", 'd');
// "mod" = flooring modulo
if (cell->type == ID($modfloor)) {
if (cell->type == TW($modfloor)) {
// bvumod doesn't exist because it's the same as bvurem
if (cell->getParam(ID::A_SIGNED).as_bool()) {
return export_bvop(cell, "(bvsmod A B)", 'd');
@ -707,7 +707,7 @@ struct Smt2Worker
}
}
// "div" = flooring division
if (cell->type == ID($divfloor)) {
if (cell->type == TW($divfloor)) {
if (cell->getParam(ID::A_SIGNED).as_bool()) {
// bvsdiv is truncating division, so we can't use it here.
int width = max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::B)));
@ -728,24 +728,24 @@ struct Smt2Worker
}
}
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool)) &&
if (cell->type.in(TW($reduce_and), TW($reduce_or), TW($reduce_bool)) &&
2*GetSize(cell->getPort(TW::A).chunks()) < GetSize(cell->getPort(TW::A))) {
bool is_and = cell->type == ID($reduce_and);
bool is_and = cell->type == TW($reduce_and);
string bits(GetSize(cell->getPort(TW::A)), is_and ? '1' : '0');
return export_bvop(cell, stringf("(%s A #b%s)", is_and ? "=" : "distinct", bits), 'b');
}
if (cell->type == ID($reduce_and)) return export_reduce(cell, "(and A)", true);
if (cell->type == ID($reduce_or)) return export_reduce(cell, "(or A)", false);
if (cell->type == ID($reduce_xor)) return export_reduce(cell, "(xor A)", false);
if (cell->type == ID($reduce_xnor)) return export_reduce(cell, "(not (xor A))", false);
if (cell->type == ID($reduce_bool)) return export_reduce(cell, "(or A)", false);
if (cell->type == TW($reduce_and)) return export_reduce(cell, "(and A)", true);
if (cell->type == TW($reduce_or)) return export_reduce(cell, "(or A)", false);
if (cell->type == TW($reduce_xor)) return export_reduce(cell, "(xor A)", false);
if (cell->type == TW($reduce_xnor)) return export_reduce(cell, "(not (xor A))", false);
if (cell->type == TW($reduce_bool)) return export_reduce(cell, "(or A)", false);
if (cell->type == ID($logic_not)) return export_reduce(cell, "(not (or A))", false);
if (cell->type == ID($logic_and)) return export_reduce(cell, "(and (or A) (or B))", false);
if (cell->type == ID($logic_or)) return export_reduce(cell, "(or A B)", false);
if (cell->type == TW($logic_not)) return export_reduce(cell, "(not (or A))", false);
if (cell->type == TW($logic_and)) return export_reduce(cell, "(and (or A) (or B))", false);
if (cell->type == TW($logic_or)) return export_reduce(cell, "(or A B)", false);
if (cell->type.in(ID($mux), ID($pmux)))
if (cell->type.in(TW($mux), TW($pmux)))
{
int width = GetSize(cell->getPort(TW::Y));
std::string processed_expr = get_bv(cell->getPort(TW::A));
@ -798,7 +798,7 @@ struct Smt2Worker
if (has_async_wr && has_sync_wr)
log_error("Memory %s.%s has mixed clocked/nonclocked write ports. This is not supported by \"write_smt2\".\n", cell, module);
decls.push_back(stringf("; yosys-smt2-memory %s %d %d %d %d %s\n", mem->memid.unescape(), abits, mem->width, GetSize(mem->rd_ports), GetSize(mem->wr_ports), has_async_wr ? "async" : "sync"));
decls.push_back(stringf("; yosys-smt2-memory %s %d %d %d %d %s\n", design->twines.unescaped_str(mem->memid), abits, mem->width, GetSize(mem->rd_ports), GetSize(mem->wr_ports), has_async_wr ? "async" : "sync"));
decls.push_back(witness_memory(get_id(mem->memid), cell, mem));
string memstate;
@ -823,7 +823,7 @@ struct Smt2Worker
if (port.clk_enable)
log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! "
"Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(port.data), mem->memid.unescape(), module);
"Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(port.data), design->twines.unescaped_str(mem->memid), module);
decls.push_back(stringf("(define-fun |%s_m:R%dA %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
get_id(module), i, get_id(mem->memid), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
@ -867,7 +867,7 @@ struct Smt2Worker
if (port.clk_enable)
log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! "
"Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(port.data), mem->memid.unescape(), module);
"Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(port.data), design->twines.unescaped_str(mem->memid), module);
decls.push_back(stringf("(define-fun |%s_m:R%dA %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
get_id(module), i, get_id(mem->memid), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
@ -936,15 +936,15 @@ struct Smt2Worker
return;
}
if (cell->type.in(ID($dffe), ID($sdff), ID($sdffe), ID($sdffce)) || cell->type.str().substr(0, 6) == "$_SDFF" || (cell->type.str().substr(0, 6) == "$_DFFE" && cell->type.str().size() == 10)) {
if (cell->type.in(TW($dffe), TW($sdff), TW($sdffe), TW($sdffce)) || cell->type.str().substr(0, 6) == "$_SDFF" || (cell->type.str().substr(0, 6) == "$_DFFE" && cell->type.str().size() == 10)) {
log_error("Unsupported cell type %s for cell %s.%s -- please run `dffunmap` before `write_smt2`.\n",
cell->type.unescape(), module, cell);
}
if (cell->type.in(ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($dffsr), ID($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF" || cell->type.str().substr(0, 7) == "$_ALDFF") {
if (cell->type.in(TW($adff), TW($adffe), TW($aldff), TW($aldffe), TW($dffsr), TW($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF" || cell->type.str().substr(0, 7) == "$_ALDFF") {
log_error("Unsupported cell type %s for cell %s.%s -- please run `async2sync; dffunmap` or `clk2fflogic` before `write_smt2`.\n",
cell->type.unescape(), module, cell);
}
if (cell->type.in(ID($sr), ID($dlatch), ID($adlatch), ID($dlatchsr)) || cell->type.str().substr(0, 8) == "$_DLATCH" || cell->type.str().substr(0, 5) == "$_SR_") {
if (cell->type.in(TW($sr), TW($dlatch), TW($adlatch), TW($dlatchsr)) || cell->type.str().substr(0, 8) == "$_DLATCH" || cell->type.str().substr(0, 5) == "$_SR_") {
log_error("Unsupported cell type %s for cell %s.%s -- please run `clk2fflogic` before `write_smt2`.\n",
cell->type, module, cell);
}
@ -973,7 +973,7 @@ struct Smt2Worker
pool<SigBit> reg_bits;
for (auto cell : module->cells())
if (cell->type.in(ID($ff), ID($dff), ID($_FF_), ID($_DFF_P_), ID($_DFF_N_), ID($anyinit))) {
if (cell->type.in(TW($ff), TW($dff), TW($_FF_), TW($_DFF_P_), TW($_DFF_N_), TW($anyinit))) {
// not using sigmap -- we want the net directly at the dff output
for (auto bit : cell->getPort(TW::Q))
reg_bits.insert(bit);
@ -1117,15 +1117,15 @@ struct Smt2Worker
for (auto cell : module->cells())
{
if (cell->type.in(ID($assert), ID($assume), ID($cover)))
if (cell->type.in(TW($assert), TW($assume), TW($cover)))
{
int &id = cell->type == ID($assert) ? assert_id :
cell->type == ID($assume) ? assume_id :
cell->type == ID($cover) ? cover_id : *(int*)nullptr;
int &id = cell->type == TW($assert) ? assert_id :
cell->type == TW($assume) ? assume_id :
cell->type == TW($cover) ? cover_id : *(int*)nullptr;
char postfix = cell->type == ID($assert) ? 'a' :
cell->type == ID($assume) ? 'u' :
cell->type == ID($cover) ? 'c' : 0;
char postfix = cell->type == TW($assert) ? 'a' :
cell->type == TW($assume) ? 'u' :
cell->type == TW($cover) ? 'c' : 0;
string name_a = get_bool(cell->getPort(TW::A));
string name_en = get_bool(cell->getPort(TW::EN));
@ -1147,16 +1147,16 @@ struct Smt2Worker
else
decls.push_back(stringf("; yosys-smt2-%s %d %s\n", cell->type.c_str() + 1, id, get_id(cell)));
if (cell->type == ID($cover))
if (cell->type == TW($cover))
decls.push_back(stringf("(define-fun |%s_%c %d| ((state |%s_s|)) Bool (and %s %s)) ; %s\n",
get_id(module), postfix, id, get_id(module), name_a.c_str(), name_en.c_str(), get_id(cell)));
else
decls.push_back(stringf("(define-fun |%s_%c %d| ((state |%s_s|)) Bool (or %s (not %s))) ; %s\n",
get_id(module), postfix, id, get_id(module), name_a.c_str(), name_en.c_str(), get_id(cell)));
if (cell->type == ID($assert))
if (cell->type == TW($assert))
assert_list.push_back(stringf("(|%s_a %d| state)", get_id(module), id));
else if (cell->type == ID($assume))
else if (cell->type == TW($assume))
assume_list.push_back(stringf("(|%s_u %d| state)", get_id(module), id));
id++;
@ -1212,7 +1212,7 @@ struct Smt2Worker
for (auto cell : this_regs)
{
if (cell->type.in(ID($_FF_), ID($_DFF_P_), ID($_DFF_N_)))
if (cell->type.in(TW($_FF_), TW($_DFF_P_), TW($_DFF_N_)))
{
std::string expr_d = get_bool(cell->getPort(TW::D));
std::string expr_q = get_bool(cell->getPort(TW::Q), "next_state");
@ -1220,7 +1220,7 @@ struct Smt2Worker
ex_state_eq.push_back(stringf("(= %s %s)", get_bool(cell->getPort(TW::Q)), get_bool(cell->getPort(TW::Q), "other_state")));
}
if (cell->type.in(ID($ff), ID($dff), ID($anyinit)))
if (cell->type.in(TW($ff), TW($dff), TW($anyinit)))
{
std::string expr_d = get_bv(cell->getPort(TW::D));
std::string expr_q = get_bv(cell->getPort(TW::Q), "next_state");
@ -1228,12 +1228,12 @@ struct Smt2Worker
ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(TW::Q)), get_bv(cell->getPort(TW::Q), "other_state")));
}
if (cell->type.in(ID($anyconst), ID($allconst)))
if (cell->type.in(TW($anyconst), TW($allconst)))
{
std::string expr_d = get_bv(cell->getPort(TW::Y));
std::string expr_q = get_bv(cell->getPort(TW::Y), "next_state");
trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d, expr_q, get_id(cell), log_signal(cell->getPort(TW::Y))));
if (cell->type == ID($anyconst))
if (cell->type == TW($anyconst))
ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(TW::Y)), get_bv(cell->getPort(TW::Y), "other_state")));
}
}
@ -1882,7 +1882,7 @@ struct Smt2Backend : public Backend {
for (auto &dep : it.second)
if (module_deps.count(dep) > 0)
goto not_ready_yet;
// log("Next in topological sort: %s\n", it.first->name.unescape());
// log("Next in topological sort: %s\n", design->twines.unescaped_str(it.first->name));
sorted_modules.push_back(it.first);
not_ready_yet:;
}
@ -1899,7 +1899,7 @@ struct Smt2Backend : public Backend {
for (auto module : sorted_modules)
for (auto cell : module->cells())
if (cell->type.in(ID($allconst), ID($allseq)))
if (cell->type.in(TW($allconst), TW($allseq)))
goto found_forall;
if (0) {
found_forall:

122
backends/smv/smv.cc
View file

@ -227,7 +227,7 @@ struct SmvWorker
{
// FIXME: $slice, $concat, $mem
if (cell->type.in(ID($assert)))
if (cell->type.in(TW($assert)))
{
SigSpec sig_a = cell->getPort(TW::A);
SigSpec sig_en = cell->getPort(TW::EN);
@ -237,7 +237,7 @@ struct SmvWorker
continue;
}
if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)))
if (cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx)))
{
SigSpec sig_a = cell->getPort(TW::A);
SigSpec sig_b = cell->getPort(TW::B);
@ -256,10 +256,10 @@ struct SmvWorker
bool signed_a = cell->getParam(ID::A_SIGNED).as_bool();
bool signed_b = cell->getParam(ID::B_SIGNED).as_bool();
string op = cell->type.in(ID($shl), ID($sshl)) ? "<<" : ">>";
string op = cell->type.in(TW($shl), TW($sshl)) ? "<<" : ">>";
string expr, expr_a;
if (cell->type == ID($sshr) && signed_a)
if (cell->type == TW($sshr) && signed_a)
{
expr_a = rvalue_s(sig_a, width);
expr = stringf("resize(unsigned(%s %s %s), %d)", expr_a, op, rvalue(sig_b.extract(0, shift_b_width)), width_y);
@ -268,7 +268,7 @@ struct SmvWorker
rvalue(sig_b.extract(shift_b_width, GetSize(sig_b) - shift_b_width)), GetSize(sig_b) - shift_b_width,
rvalue(sig_a[GetSize(sig_a)-1]), width_y, width_y, expr.c_str());
}
else if (cell->type.in(ID($shift), ID($shiftx)) && signed_b)
else if (cell->type.in(TW($shift), TW($shiftx)) && signed_b)
{
expr_a = rvalue_u(sig_a, width);
@ -292,7 +292,7 @@ struct SmvWorker
}
else
{
if (cell->type.in(ID($shift), ID($shiftx)) || !signed_a)
if (cell->type.in(TW($shift), TW($shiftx)) || !signed_a)
expr_a = rvalue_u(sig_a, width);
else
expr_a = stringf("resize(unsigned(%s), %d)", rvalue_s(sig_a, width_ay), width);
@ -308,14 +308,14 @@ struct SmvWorker
continue;
}
if (cell->type.in(ID($not), ID($pos), ID($neg)))
if (cell->type.in(TW($not), TW($pos), TW($neg)))
{
int width = GetSize(cell->getPort(TW::Y));
string expr_a, op;
if (cell->type == ID($not)) op = "!";
if (cell->type == ID($pos)) op = "";
if (cell->type == ID($neg)) op = "-";
if (cell->type == TW($not)) op = "!";
if (cell->type == TW($pos)) op = "";
if (cell->type == TW($neg)) op = "-";
if (cell->getParam(ID::A_SIGNED).as_bool())
{
@ -331,18 +331,18 @@ struct SmvWorker
continue;
}
if (cell->type.in(ID($add), ID($sub), ID($mul), ID($and), ID($or), ID($xor), ID($xnor)))
if (cell->type.in(TW($add), TW($sub), TW($mul), TW($and), TW($or), TW($xor), TW($xnor)))
{
int width = GetSize(cell->getPort(TW::Y));
string expr_a, expr_b, op;
if (cell->type == ID($add)) op = "+";
if (cell->type == ID($sub)) op = "-";
if (cell->type == ID($mul)) op = "*";
if (cell->type == ID($and)) op = "&";
if (cell->type == ID($or)) op = "|";
if (cell->type == ID($xor)) op = "xor";
if (cell->type == ID($xnor)) op = "xnor";
if (cell->type == TW($add)) op = "+";
if (cell->type == TW($sub)) op = "-";
if (cell->type == TW($mul)) op = "*";
if (cell->type == TW($and)) op = "&";
if (cell->type == TW($or)) op = "|";
if (cell->type == TW($xor)) op = "xor";
if (cell->type == TW($xnor)) op = "xnor";
if (cell->getParam(ID::A_SIGNED).as_bool())
{
@ -359,15 +359,15 @@ struct SmvWorker
}
// SMV has a "mod" operator, but its semantics don't seem to be well-defined - to be safe, don't generate it at all
if (cell->type.in(ID($div)/*, ID($mod), ID($modfloor)*/))
if (cell->type.in(TW($div)/*, TW($mod), TW($modfloor)*/))
{
int width_y = GetSize(cell->getPort(TW::Y));
int width = max(width_y, GetSize(cell->getPort(TW::A)));
width = max(width, GetSize(cell->getPort(TW::B)));
string expr_a, expr_b, op;
if (cell->type == ID($div)) op = "/";
//if (cell->type == ID($mod)) op = "mod";
if (cell->type == TW($div)) op = "/";
//if (cell->type == TW($mod)) op = "mod";
if (cell->getParam(ID::A_SIGNED).as_bool())
{
@ -383,19 +383,19 @@ struct SmvWorker
continue;
}
if (cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex), ID($lt), ID($le), ID($ge), ID($gt)))
if (cell->type.in(TW($eq), TW($ne), TW($eqx), TW($nex), TW($lt), TW($le), TW($ge), TW($gt)))
{
int width = max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::B)));
string expr_a, expr_b, op;
if (cell->type == ID($eq)) op = "=";
if (cell->type == ID($ne)) op = "!=";
if (cell->type == ID($eqx)) op = "=";
if (cell->type == ID($nex)) op = "!=";
if (cell->type == ID($lt)) op = "<";
if (cell->type == ID($le)) op = "<=";
if (cell->type == ID($ge)) op = ">=";
if (cell->type == ID($gt)) op = ">";
if (cell->type == TW($eq)) op = "=";
if (cell->type == TW($ne)) op = "!=";
if (cell->type == TW($eqx)) op = "=";
if (cell->type == TW($nex)) op = "!=";
if (cell->type == TW($lt)) op = "<";
if (cell->type == TW($le)) op = "<=";
if (cell->type == TW($ge)) op = ">=";
if (cell->type == TW($gt)) op = ">";
if (cell->getParam(ID::A_SIGNED).as_bool())
{
@ -414,7 +414,7 @@ struct SmvWorker
continue;
}
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool)))
if (cell->type.in(TW($reduce_and), TW($reduce_or), TW($reduce_bool)))
{
int width_a = GetSize(cell->getPort(TW::A));
int width_y = GetSize(cell->getPort(TW::Y));
@ -422,15 +422,15 @@ struct SmvWorker
const char *expr_y = lvalue(cell->getPort(TW::Y));
string expr;
if (cell->type == ID($reduce_and)) expr = stringf("%s = !0ub%d_0", expr_a, width_a);
if (cell->type == ID($reduce_or)) expr = stringf("%s != 0ub%d_0", expr_a, width_a);
if (cell->type == ID($reduce_bool)) expr = stringf("%s != 0ub%d_0", expr_a, width_a);
if (cell->type == TW($reduce_and)) expr = stringf("%s = !0ub%d_0", expr_a, width_a);
if (cell->type == TW($reduce_or)) expr = stringf("%s != 0ub%d_0", expr_a, width_a);
if (cell->type == TW($reduce_bool)) expr = stringf("%s != 0ub%d_0", expr_a, width_a);
definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr, width_y));
continue;
}
if (cell->type.in(ID($reduce_xor), ID($reduce_xnor)))
if (cell->type.in(TW($reduce_xor), TW($reduce_xnor)))
{
int width_y = GetSize(cell->getPort(TW::Y));
const char *expr_y = lvalue(cell->getPort(TW::Y));
@ -442,14 +442,14 @@ struct SmvWorker
expr += rvalue(bit);
}
if (cell->type == ID($reduce_xnor))
if (cell->type == TW($reduce_xnor))
expr = "!(" + expr + ")";
definitions.push_back(stringf("%s := resize(%s, %d);", expr_y, expr, width_y));
continue;
}
if (cell->type.in(ID($logic_and), ID($logic_or)))
if (cell->type.in(TW($logic_and), TW($logic_or)))
{
int width_a = GetSize(cell->getPort(TW::A));
int width_b = GetSize(cell->getPort(TW::B));
@ -460,14 +460,14 @@ struct SmvWorker
const char *expr_y = lvalue(cell->getPort(TW::Y));
string expr;
if (cell->type == ID($logic_and)) expr = expr_a + " & " + expr_b;
if (cell->type == ID($logic_or)) expr = expr_a + " | " + expr_b;
if (cell->type == TW($logic_and)) expr = expr_a + " & " + expr_b;
if (cell->type == TW($logic_or)) expr = expr_a + " | " + expr_b;
definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr, width_y));
continue;
}
if (cell->type.in(ID($logic_not)))
if (cell->type.in(TW($logic_not)))
{
int width_a = GetSize(cell->getPort(TW::A));
int width_y = GetSize(cell->getPort(TW::Y));
@ -479,7 +479,7 @@ struct SmvWorker
continue;
}
if (cell->type.in(ID($mux), ID($pmux)))
if (cell->type.in(TW($mux), TW($pmux)))
{
int width = GetSize(cell->getPort(TW::Y));
SigSpec sig_a = cell->getPort(TW::A);
@ -495,34 +495,34 @@ struct SmvWorker
continue;
}
if (cell->type == ID($dff))
if (cell->type == TW($dff))
{
vars.push_back(stringf("%s : unsigned word[%d]; -- %s", lvalue(cell->getPort(TW::Q)), GetSize(cell->getPort(TW::Q)), log_signal(cell->getPort(TW::Q))));
assignments.push_back(stringf("next(%s) := %s;", lvalue(cell->getPort(TW::Q)), rvalue(cell->getPort(TW::D))));
continue;
}
if (cell->type.in(ID($_BUF_), ID($_NOT_)))
if (cell->type.in(TW($_BUF_), TW($_NOT_)))
{
string op = cell->type == ID($_NOT_) ? "!" : "";
string op = cell->type == TW($_NOT_) ? "!" : "";
definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort(TW::Y)), op, rvalue(cell->getPort(TW::A))));
continue;
}
if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
if (cell->type.in(TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_), TW($_XOR_), TW($_XNOR_), TW($_ANDNOT_), TW($_ORNOT_)))
{
string op;
if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_ANDNOT_))) op = "&";
if (cell->type.in(ID($_OR_), ID($_NOR_), ID($_ORNOT_))) op = "|";
if (cell->type.in(ID($_XOR_))) op = "xor";
if (cell->type.in(ID($_XNOR_))) op = "xnor";
if (cell->type.in(TW($_AND_), TW($_NAND_), TW($_ANDNOT_))) op = "&";
if (cell->type.in(TW($_OR_), TW($_NOR_), TW($_ORNOT_))) op = "|";
if (cell->type.in(TW($_XOR_))) op = "xor";
if (cell->type.in(TW($_XNOR_))) op = "xnor";
if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
if (cell->type.in(TW($_ANDNOT_), TW($_ORNOT_)))
definitions.push_back(stringf("%s := %s %s (!%s);", lvalue(cell->getPort(TW::Y)),
rvalue(cell->getPort(TW::A)), op.c_str(), rvalue(cell->getPort(TW::B))));
else
if (cell->type.in(ID($_NAND_), ID($_NOR_)))
if (cell->type.in(TW($_NAND_), TW($_NOR_)))
definitions.push_back(stringf("%s := !(%s %s %s);", lvalue(cell->getPort(TW::Y)),
rvalue(cell->getPort(TW::A)), op.c_str(), rvalue(cell->getPort(TW::B))));
else
@ -531,61 +531,61 @@ struct SmvWorker
continue;
}
if (cell->type == ID($_MUX_))
if (cell->type == TW($_MUX_))
{
definitions.push_back(stringf("%s := bool(%s) ? %s : %s;", lvalue(cell->getPort(TW::Y)),
rvalue(cell->getPort(TW::S)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::A))));
continue;
}
if (cell->type == ID($_NMUX_))
if (cell->type == TW($_NMUX_))
{
definitions.push_back(stringf("%s := !(bool(%s) ? %s : %s);", lvalue(cell->getPort(TW::Y)),
rvalue(cell->getPort(TW::S)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::A))));
continue;
}
if (cell->type == ID($_AOI3_))
if (cell->type == TW($_AOI3_))
{
definitions.push_back(stringf("%s := !((%s & %s) | %s);", lvalue(cell->getPort(TW::Y)),
rvalue(cell->getPort(TW::A)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::C))));
continue;
}
if (cell->type == ID($_OAI3_))
if (cell->type == TW($_OAI3_))
{
definitions.push_back(stringf("%s := !((%s | %s) & %s);", lvalue(cell->getPort(TW::Y)),
rvalue(cell->getPort(TW::A)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::C))));
continue;
}
if (cell->type == ID($_AOI4_))
if (cell->type == TW($_AOI4_))
{
definitions.push_back(stringf("%s := !((%s & %s) | (%s & %s));", lvalue(cell->getPort(TW::Y)),
rvalue(cell->getPort(TW::A)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::C)), rvalue(cell->getPort(TW::D))));
continue;
}
if (cell->type == ID($_OAI4_))
if (cell->type == TW($_OAI4_))
{
definitions.push_back(stringf("%s := !((%s | %s) & (%s | %s));", lvalue(cell->getPort(TW::Y)),
rvalue(cell->getPort(TW::A)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::C)), rvalue(cell->getPort(TW::D))));
continue;
}
if (cell->type == ID($scopeinfo))
if (cell->type == TW($scopeinfo))
continue;
if (cell->type[0] == '$') {
if (cell->type.in(ID($dffe), ID($sdff), ID($sdffe), ID($sdffce)) || cell->type.str().substr(0, 6) == "$_SDFF" || (cell->type.str().substr(0, 6) == "$_DFFE" && cell->type.str().size() == 10)) {
if (cell->type.in(TW($dffe), TW($sdff), TW($sdffe), TW($sdffce)) || cell->type.str().substr(0, 6) == "$_SDFF" || (cell->type.str().substr(0, 6) == "$_DFFE" && cell->type.str().size() == 10)) {
log_error("Unsupported cell type %s for cell %s.%s -- please run `dffunmap` before `write_smv`.\n",
cell->type.unescape(), module, cell);
}
if (cell->type.in(ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($dffsr), ID($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF" || cell->type.str().substr(0, 7) == "$_ALDFF") {
if (cell->type.in(TW($adff), TW($adffe), TW($aldff), TW($aldffe), TW($dffsr), TW($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF" || cell->type.str().substr(0, 7) == "$_ALDFF") {
log_error("Unsupported cell type %s for cell %s.%s -- please run `async2sync; dffunmap` or `clk2fflogic` before `write_smv`.\n",
cell->type.unescape(), module, cell);
}
if (cell->type.in(ID($sr), ID($dlatch), ID($adlatch), ID($dlatchsr)) || cell->type.str().substr(0, 8) == "$_DLATCH" || cell->type.str().substr(0, 5) == "$_SR_") {
if (cell->type.in(TW($sr), TW($dlatch), TW($adlatch), TW($dlatchsr)) || cell->type.str().substr(0, 8) == "$_DLATCH" || cell->type.str().substr(0, 5) == "$_SR_") {
log_error("Unsupported cell type %s for cell %s.%s -- please run `clk2fflogic` before `write_smv`.\n",
cell->type.unescape(), module, cell);
}

4
backends/spice/spice.cc
View file

@ -30,7 +30,7 @@ PRIVATE_NAMESPACE_BEGIN
static string spice_id2str(IdString id)
{
static const char *escape_chars = "$\\[]()<>=";
string s = id.unescape();
string s = design->twines.unescaped_str(id);
for (auto &ch : s)
if (strchr(escape_chars, ch) != nullptr) ch = '_';
@ -72,7 +72,7 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
for (auto cell : module->cells())
{
if (cell->type == ID($scopeinfo))
if (cell->type == TW($scopeinfo))
continue;
f << stringf("X%d", cell_counter++);

4
backends/table/table.cc
View file

@ -78,7 +78,7 @@ struct TableBackend : public Backend {
continue;
*f << design->twines.str(module->meta_->name) << "\t";
*f << wire->name.unescape() << "\t";
*f << design->twines.unescaped_str(wire->name) << "\t";
*f << "-" << "\t";
*f << "-" << "\t";
@ -99,7 +99,7 @@ struct TableBackend : public Backend {
{
*f << design->twines.str(module->meta_->name) << "\t";
*f << cell->module->design->twines.str(cell->meta_->name) << "\t";
*f << cell->type.unescape() << "\t";
*f << cell->type.unescaped() << "\t";
*f << design->twines.str(conn.first) << "\t";
if (cell->input(conn.first) && cell->output(conn.first))

158
backends/verilog/verilog_backend.cc
View file

@ -992,7 +992,7 @@ void dump_cell_expr_port(std::ostream &f, RTLIL::Cell *cell, std::string port, b
std::string cellname(RTLIL::Cell *cell)
{
if (!norename && cell->name[0] == '$' && cell->is_builtin_ff() && cell->hasPort(TW::Q) && !cell->type.in(ID($ff), ID($_FF_)))
if (!norename && cell->name[0] == '$' && cell->is_builtin_ff() && cell->hasPort(TW::Q) && !cell->type.in(TW($ff), TW($_FF_)))
{
RTLIL::SigSpec sig = cell->getPort(TW::Q);
if (GetSize(sig) != 1 || sig.is_fully_const())
@ -1109,7 +1109,7 @@ void dump_cell_expr_check(std::ostream &f, std::string indent, const RTLIL::Cell
bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
{
if (cell->type == ID($_NOT_)) {
if (cell->type == TW($_NOT_)) {
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ");
@ -1120,8 +1120,8 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}
if (cell->type.in(ID($_BUF_), ID($buf))) {
if (cell->type == ID($buf) && cell->getPort(TW::A).has_const(State::Sz)) {
if (cell->type.in(TW($_BUF_), TW($buf))) {
if (cell->type == TW($buf) && cell->getPort(TW::A).has_const(State::Sz)) {
RTLIL::SigSpec a = cell->getPort(TW::A);
RTLIL::SigSpec y = cell->getPort(TW::Y);
a.extend_u0(GetSize(y));
@ -1156,32 +1156,32 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}
if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_))) {
if (cell->type.in(TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_), TW($_XOR_), TW($_XNOR_), TW($_ANDNOT_), TW($_ORNOT_))) {
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ");
if (cell->type.in(ID($_NAND_), ID($_NOR_), ID($_XNOR_)))
if (cell->type.in(TW($_NAND_), TW($_NOR_), TW($_XNOR_)))
f << stringf("~(");
dump_cell_expr_port(f, cell, "A", false);
f << stringf(" ");
if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_ANDNOT_)))
if (cell->type.in(TW($_AND_), TW($_NAND_), TW($_ANDNOT_)))
f << stringf("&");
if (cell->type.in(ID($_OR_), ID($_NOR_), ID($_ORNOT_)))
if (cell->type.in(TW($_OR_), TW($_NOR_), TW($_ORNOT_)))
f << stringf("|");
if (cell->type.in(ID($_XOR_), ID($_XNOR_)))
if (cell->type.in(TW($_XOR_), TW($_XNOR_)))
f << stringf("^");
dump_attributes(f, "", cell->attributes, " ");
f << stringf(" ");
if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
if (cell->type.in(TW($_ANDNOT_), TW($_ORNOT_)))
f << stringf("~(");
dump_cell_expr_port(f, cell, "B", false);
if (cell->type.in(ID($_NAND_), ID($_NOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
if (cell->type.in(TW($_NAND_), TW($_NOR_), TW($_XNOR_), TW($_ANDNOT_), TW($_ORNOT_)))
f << stringf(")");
f << stringf(";\n");
return true;
}
if (cell->type == ID($_MUX_)) {
if (cell->type == TW($_MUX_)) {
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ");
@ -1195,7 +1195,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}
if (cell->type == ID($_NMUX_)) {
if (cell->type == TW($_NMUX_)) {
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = !(");
@ -1209,14 +1209,14 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}
if (cell->type.in(ID($_AOI3_), ID($_OAI3_))) {
if (cell->type.in(TW($_AOI3_), TW($_OAI3_))) {
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ~((");
dump_cell_expr_port(f, cell, "A", false);
f << (cell->type == ID($_AOI3_) ? " & " : " | ");
f << (cell->type == TW($_AOI3_) ? " & " : " | ");
dump_cell_expr_port(f, cell, "B", false);
f << (cell->type == ID($_AOI3_) ? ") |" : ") &");
f << (cell->type == TW($_AOI3_) ? ") |" : ") &");
dump_attributes(f, "", cell->attributes, " ");
f << stringf(" ");
dump_cell_expr_port(f, cell, "C", false);
@ -1224,18 +1224,18 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}
if (cell->type.in(ID($_AOI4_), ID($_OAI4_))) {
if (cell->type.in(TW($_AOI4_), TW($_OAI4_))) {
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ~((");
dump_cell_expr_port(f, cell, "A", false);
f << (cell->type == ID($_AOI4_) ? " & " : " | ");
f << (cell->type == TW($_AOI4_) ? " & " : " | ");
dump_cell_expr_port(f, cell, "B", false);
f << (cell->type == ID($_AOI4_) ? ") |" : ") &");
f << (cell->type == TW($_AOI4_) ? ") |" : ") &");
dump_attributes(f, "", cell->attributes, " ");
f << stringf(" (");
dump_cell_expr_port(f, cell, "C", false);
f << (cell->type == ID($_AOI4_) ? " & " : " | ");
f << (cell->type == TW($_AOI4_) ? " & " : " | ");
dump_cell_expr_port(f, cell, "D", false);
f << stringf("));\n");
return true;
@ -1246,50 +1246,50 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
#define HANDLE_BINOP(_type, _operator) \
if (cell->type ==_type) { dump_cell_expr_binop(f, indent, cell, _operator); return true; }
HANDLE_UNIOP(ID($not), "~")
HANDLE_UNIOP(ID($pos), "+")
HANDLE_UNIOP(ID($neg), "-")
HANDLE_UNIOP(TW($not), "~")
HANDLE_UNIOP(TW($pos), "+")
HANDLE_UNIOP(TW($neg), "-")
HANDLE_BINOP(ID($and), "&")
HANDLE_BINOP(ID($or), "|")
HANDLE_BINOP(ID($xor), "^")
HANDLE_BINOP(ID($xnor), "~^")
HANDLE_BINOP(TW($and), "&")
HANDLE_BINOP(TW($or), "|")
HANDLE_BINOP(TW($xor), "^")
HANDLE_BINOP(TW($xnor), "~^")
HANDLE_UNIOP(ID($reduce_and), "&")
HANDLE_UNIOP(ID($reduce_or), "|")
HANDLE_UNIOP(ID($reduce_xor), "^")
HANDLE_UNIOP(ID($reduce_xnor), "~^")
HANDLE_UNIOP(ID($reduce_bool), "|")
HANDLE_UNIOP(TW($reduce_and), "&")
HANDLE_UNIOP(TW($reduce_or), "|")
HANDLE_UNIOP(TW($reduce_xor), "^")
HANDLE_UNIOP(TW($reduce_xnor), "~^")
HANDLE_UNIOP(TW($reduce_bool), "|")
HANDLE_BINOP(ID($shl), "<<")
HANDLE_BINOP(ID($shr), ">>")
HANDLE_BINOP(ID($sshl), "<<<")
HANDLE_BINOP(ID($sshr), ">>>")
HANDLE_BINOP(TW($shl), "<<")
HANDLE_BINOP(TW($shr), ">>")
HANDLE_BINOP(TW($sshl), "<<<")
HANDLE_BINOP(TW($sshr), ">>>")
HANDLE_BINOP(ID($lt), "<")
HANDLE_BINOP(ID($le), "<=")
HANDLE_BINOP(ID($eq), "==")
HANDLE_BINOP(ID($ne), "!=")
HANDLE_BINOP(ID($eqx), "===")
HANDLE_BINOP(ID($nex), "!==")
HANDLE_BINOP(ID($ge), ">=")
HANDLE_BINOP(ID($gt), ">")
HANDLE_BINOP(TW($lt), "<")
HANDLE_BINOP(TW($le), "<=")
HANDLE_BINOP(TW($eq), "==")
HANDLE_BINOP(TW($ne), "!=")
HANDLE_BINOP(TW($eqx), "===")
HANDLE_BINOP(TW($nex), "!==")
HANDLE_BINOP(TW($ge), ">=")
HANDLE_BINOP(TW($gt), ">")
HANDLE_BINOP(ID($add), "+")
HANDLE_BINOP(ID($sub), "-")
HANDLE_BINOP(ID($mul), "*")
HANDLE_BINOP(ID($div), "/")
HANDLE_BINOP(ID($mod), "%")
HANDLE_BINOP(ID($pow), "**")
HANDLE_BINOP(TW($add), "+")
HANDLE_BINOP(TW($sub), "-")
HANDLE_BINOP(TW($mul), "*")
HANDLE_BINOP(TW($div), "/")
HANDLE_BINOP(TW($mod), "%")
HANDLE_BINOP(TW($pow), "**")
HANDLE_UNIOP(ID($logic_not), "!")
HANDLE_BINOP(ID($logic_and), "&&")
HANDLE_BINOP(ID($logic_or), "||")
HANDLE_UNIOP(TW($logic_not), "!")
HANDLE_BINOP(TW($logic_and), "&&")
HANDLE_BINOP(TW($logic_or), "||")
#undef HANDLE_UNIOP
#undef HANDLE_BINOP
if (cell->type == ID($divfloor))
if (cell->type == TW($divfloor))
{
// wire [MAXLEN+1:0] _0_, _1_, _2_;
// assign _0_ = $signed(A);
@ -1344,7 +1344,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
}
}
if (cell->type == ID($modfloor))
if (cell->type == TW($modfloor))
{
// wire truncated = $signed(A) % $signed(B);
// assign Y = (A[-1] == B[-1]) || truncated == 0 ? $signed(truncated) : $signed(B) + $signed(truncated);
@ -1378,7 +1378,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
}
}
if (cell->type == ID($shift))
if (cell->type == TW($shift))
{
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(TW::Y));
@ -1405,7 +1405,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}
if (cell->type == ID($shiftx))
if (cell->type == TW($shiftx))
{
std::string temp_id = next_auto_id();
f << stringf("%s" "wire [%d:0] %s = ", indent, GetSize(cell->getPort(TW::A))-1, temp_id);
@ -1425,7 +1425,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}
if (cell->type == ID($mux))
if (cell->type == TW($mux))
{
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(TW::Y));
@ -1440,7 +1440,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}
if (cell->type == ID($pmux))
if (cell->type == TW($pmux))
{
int width = cell->parameters[ID::WIDTH].as_int();
int s_width = cell->getPort(TW::S).size();
@ -1500,7 +1500,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}
if (cell->type == ID($tribuf))
if (cell->type == TW($tribuf))
{
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(TW::Y));
@ -1512,7 +1512,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}
if (cell->type == ID($slice))
if (cell->type == TW($slice))
{
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(TW::Y));
@ -1522,7 +1522,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}
if (cell->type == ID($concat))
if (cell->type == TW($concat))
{
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(TW::Y));
@ -1534,7 +1534,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}
if (cell->type == ID($lut))
if (cell->type == TW($lut))
{
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(TW::Y));
@ -1547,10 +1547,10 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}
if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
if (cell->type.in(TW($input_port), TW($output_port), TW($public)))
return true;
if (cell->type == ID($connect))
if (cell->type == TW($connect))
{
int width = cell->getParam(ID::WIDTH).as_int() ;
if (width == 1) {
@ -1794,7 +1794,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}
if (cell->type.in(ID($assert), ID($assume), ID($cover)))
if (cell->type.in(TW($assert), TW($assume), TW($cover)))
{
f << stringf("%s" "always%s if (", indent, systemverilog ? "_comb" : " @*");
dump_sigspec(f, cell->getPort(TW::EN));
@ -1804,7 +1804,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}
if (cell->type.in(ID($specify2), ID($specify3)))
if (cell->type.in(TW($specify2), TW($specify3)))
{
f << stringf("%s" "specify\n%s ", indent, indent);
@ -1816,7 +1816,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
}
f << "(";
if (cell->type == ID($specify3) && cell->getParam(ID::EDGE_EN).as_bool())
if (cell->type == TW($specify3) && cell->getParam(ID::EDGE_EN).as_bool())
f << (cell->getParam(ID::EDGE_POL).as_bool() ? "posedge ": "negedge ");
dump_sigspec(f, cell->getPort(TW::SRC));
@ -1826,7 +1826,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << (cell->getParam(ID::SRC_DST_POL).as_bool() ? "+": "-");
f << (cell->getParam(ID::FULL).as_bool() ? "*> ": "=> ");
if (cell->type == ID($specify3)) {
if (cell->type == TW($specify3)) {
f << "(";
dump_sigspec(f, cell->getPort(TW::DST));
f << " ";
@ -1862,7 +1862,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}
if (cell->type == ID($specrule))
if (cell->type == TW($specrule))
{
f << stringf("%s" "specify\n%s ", indent, indent);
@ -1898,7 +1898,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << ": ";
dump_const(f, cell->getParam(ID::T_LIMIT_MAX));
if (spec_type.in(ID($setuphold), ID($recrem), ID($fullskew))) {
if (spec_type.in(TW($setuphold), TW($recrem), TW($fullskew))) {
f << ", ";
dump_const(f, cell->getParam(ID::T_LIMIT2_MIN));
f << ": ";
@ -1914,7 +1914,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}
if (cell->type == ID($print))
if (cell->type == TW($print))
{
// Sync $print cells are accumulated and handled in dump_module.
if (cell->getParam(ID::TRG_ENABLE).as_bool())
@ -1930,7 +1930,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}
if (cell->type == ID($check))
if (cell->type == TW($check))
{
// Sync $check cells are accumulated and handled in dump_module.
if (cell->getParam(ID::TRG_ENABLE).as_bool())
@ -1974,7 +1974,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
// cells that exist only to hold metadata. If in the future that metadata
// should be exposed as part of the write_verilog output it should be
// opt-in and/or represented as something else than a $scopeinfo cell.
if (cell->type == ID($scopeinfo))
if (cell->type == TW($scopeinfo))
return;
// Handled by dump_memory
@ -2052,7 +2052,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
}
}
if (siminit && cell->is_builtin_ff() && cell->hasPort(TW::Q) && !cell->type.in(ID($ff), ID($_FF_))) {
if (siminit && cell->is_builtin_ff() && cell->hasPort(TW::Q) && !cell->type.in(TW($ff), TW($_FF_))) {
std::stringstream ss;
dump_reg_init(ss, cell->getPort(TW::Q));
if (!ss.str().empty()) {
@ -2089,9 +2089,9 @@ void dump_sync_effect(std::ostream &f, std::string indent, const RTLIL::SigSpec
dump_sigspec(f, cell->getPort(TW::EN));
f << stringf(") begin\n");
if (cell->type == ID($print)) {
if (cell->type == TW($print)) {
dump_cell_expr_print(f, indent + " ", cell);
} else if (cell->type == ID($check)) {
} else if (cell->type == TW($check)) {
std::string flavor = cell->getParam(ID::FLAVOR).decode_string();
if (flavor == "assert" || flavor == "assume") {
Fmt fmt;
@ -2408,12 +2408,12 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
std::set<std::pair<RTLIL::Wire*,int>> reg_bits;
for (auto cell : module->cells())
{
if (cell->type.in(ID($print), ID($check)) && cell->getParam(ID::TRG_ENABLE).as_bool()) {
if (cell->type.in(TW($print), TW($check)) && cell->getParam(ID::TRG_ENABLE).as_bool()) {
sync_effect_cells[make_pair(cell->getPort(TW::TRG), cell->getParam(ID::TRG_POLARITY))].push_back(cell);
continue;
}
if (!cell->is_builtin_ff() || !cell->hasPort(TW::Q) || cell->type.in(ID($ff), ID($_FF_)))
if (!cell->is_builtin_ff() || !cell->hasPort(TW::Q) || cell->type.in(TW($ff), TW($_FF_)))
continue;
RTLIL::SigSpec sig = cell->getPort(TW::Q);