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Extend liberty tests

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This commit is contained in:
Martin Povišer 2024-08-13 18:36:31 +02:00
parent 78382eaa6f
commit c35f5e379c
17 changed files with 556 additions and 4 deletions
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2
tests/liberty/.gitignore vendored
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*.log *.log
test.ys test.ys
*.filtered
*.verilogsim

15
tests/liberty/XNOR2X1.lib.filtered.ok Normal file
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library(ls05_stdcells) {
cell(XNOR2X1) {
area : 206080.0 ;
pin(B) {
direction : input ;
}
pin(A) {
direction : input ;
}
pin(Y) {
direction : output ;
function : !(B&!A|!B&A) ;
}
}
}

6
tests/liberty/XNOR2X1.lib.verilogsim.ok Normal file
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module XNOR2X1 (B, A, Y);
input B;
input A;
output Y;
assign Y = !(B&!A|!B&A); // !(B&!A|!B&A)
endmodule

8
tests/liberty/busdef.lib.filtered.ok Normal file
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library(supergate) {
cell(SRAM) {
area : 1 ;
pin(CE1) {
direction : input ;
}
}
}

3
tests/liberty/busdef.lib.verilogsim.ok Normal file
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module SRAM (CE1);
input CE1;
endmodule

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tests/liberty/issue3498_bad.lib.filtered.ok Normal file
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library(fake) {
cell(bugbad) {
}
}

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tests/liberty/issue3498_bad.lib.verilogsim.ok Normal file
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module bugbad ();
endmodule

211
tests/liberty/normal.lib.filtered.ok Normal file
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library(supergate) {
cell(inv) {
area : 1 ;
pin(A) {
direction : input ;
}
pin(Y) {
direction : output ;
function : A' ;
}
}
cell(tri_inv) {
area : 4 ;
pin(A) {
direction : input ;
}
pin(S) {
direction : input ;
}
pin(Z) {
direction : output ;
function : A' ;
}
}
cell(buffer) {
area : 5 ;
pin(A) {
direction : input ;
}
pin(Y) {
direction : output ;
function : A ;
}
}
cell(nand2) {
area : 3 ;
pin(A) {
direction : input ;
}
pin(B) {
direction : input ;
}
pin(Y) {
direction : output ;
function : (A * B)' ;
}
}
cell(nor2) {
area : 3 ;
pin(A) {
direction : input ;
}
pin(B) {
direction : input ;
}
pin(Y) {
direction : output ;
function : (A + B)' ;
}
}
cell(xor2) {
area : 6 ;
pin(A) {
direction : input ;
}
pin(B) {
direction : input ;
}
pin(Y) {
direction : output ;
function : (A *B') + (A' * B) ;
}
}
cell(imux2) {
area : 5 ;
pin(A) {
direction : input ;
}
pin(B) {
direction : input ;
}
pin(S) {
direction : input ;
}
pin(Y) {
direction : output ;
function : ( (A * S) + (B * S') )' ;
}
}
cell(dff) {
area : 6 ;
ff(IQ, IQN) {
next_state : D ;
clocked_on : CLK ;
clear : RESET ;
preset : PRESET ;
clear_preset_var1 : L ;
clear_preset_var2 : L ;
}
pin(D) {
direction : input ;
}
pin(CLK) {
direction : input ;
}
pin(RESET) {
direction : input ;
}
pin(PRESET) {
direction : input ;
}
pin(Q) {
direction : output ;
function : IQ ;
}
pin(QN) {
direction : output ;
function : IQN ;
}
}
cell(latch) {
area : 5 ;
latch(IQ, IQN) {
enable : G ;
data_in : D ;
}
pin(D) {
direction : input ;
}
pin(G) {
direction : input ;
}
pin(Q) {
direction : output ;
function : IQ ;
}
pin(QN) {
direction : output ;
function : IQN ;
}
}
cell(aoi211) {
area : 3 ;
pin(A) {
direction : input ;
}
pin(B) {
direction : input ;
}
pin(C) {
direction : input ;
}
pin(Y) {
direction : output ;
function : ((A * B) + C)' ;
}
}
cell(oai211) {
area : 3 ;
pin(A) {
direction : input ;
}
pin(B) {
direction : input ;
}
pin(C) {
direction : input ;
}
pin(Y) {
direction : output ;
function : ((A + B) * C)' ;
}
}
cell(halfadder) {
area : 5 ;
pin(A) {
direction : input ;
}
pin(B) {
direction : input ;
}
pin(C) {
direction : output ;
function : (A * B) ;
}
pin(Y) {
direction : output ;
function : (A *B') + (A' * B) ;
}
}
cell(fulladder) {
area : 8 ;
pin(A) {
direction : input ;
}
pin(B) {
direction : input ;
}
pin(CI) {
direction : input ;
}
pin(CO) {
direction : output ;
function : (((A * B)+(B * CI))+(CI * A)) ;
}
pin(Y) {
direction : output ;
function : ((A^B)^CI) ;
}
}
}

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tests/liberty/normal.lib.verilogsim.ok Normal file
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module inv (A, Y);
input A;
output Y;
assign Y = ~A; // A'
endmodule
module tri_inv (A, S, Z);
input A;
input S;
output Z;
assign Z = ~A; // A'
endmodule
module buffer (A, Y);
input A;
output Y;
assign Y = A; // A
endmodule
module nand2 (A, B, Y);
input A;
input B;
output Y;
assign Y = ~(A&B); // (A * B)'
endmodule
module nor2 (A, B, Y);
input A;
input B;
output Y;
assign Y = ~(A|B); // (A + B)'
endmodule
module xor2 (A, B, Y);
input A;
input B;
output Y;
assign Y = (A&~B)|(~A&B); // (A *B') + (A' * B)
endmodule
module imux2 (A, B, S, Y);
input A;
input B;
input S;
output Y;
assign Y = ~(&(A&S)|(B&~S)&); // ( (A * S) + (B * S') )'
endmodule
module dff (D, CLK, RESET, PRESET, Q, QN);
reg IQ, IQN;
input D;
input CLK;
input RESET;
input PRESET;
output Q;
assign Q = IQ; // IQ
output QN;
assign QN = IQN; // IQN
always @(posedge CLK, posedge RESET, posedge PRESET) begin
if ((RESET) && (PRESET)) begin
IQ <= 0;
IQN <= 0;
end
else if (RESET) begin
IQ <= 0;
IQN <= 1;
end
else if (PRESET) begin
IQ <= 1;
IQN <= 0;
end
else begin
// D
IQ <= D;
IQN <= ~(D);
end
end
endmodule
module latch (D, G, Q, QN);
reg IQ, IQN;
input D;
input G;
output Q;
assign Q = IQ; // IQ
output QN;
assign QN = IQN; // IQN
always @* begin
if (G) begin
IQ <= D;
IQN <= ~(D);
end
end
endmodule
module aoi211 (A, B, C, Y);
input A;
input B;
input C;
output Y;
assign Y = ~((A&B)|C); // ((A * B) + C)'
endmodule
module oai211 (A, B, C, Y);
input A;
input B;
input C;
output Y;
assign Y = ~((A|B)&C); // ((A + B) * C)'
endmodule
module halfadder (A, B, C, Y);
input A;
input B;
output C;
assign C = (A&B); // (A * B)
output Y;
assign Y = (A&~B)|(~A&B); // (A *B') + (A' * B)
endmodule
module fulladder (A, B, CI, CO, Y);
input A;
input B;
input CI;
output CO;
assign CO = (((A&B)|(B&CI))|(CI&A)); // (((A * B)+(B * CI))+(CI * A))
output Y;
assign Y = ((A^B)^CI); // ((A^B)^CI)
endmodule

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module inv (A, Y);
input A;
output Y;
assign Y = ~A; // A'
endmodule
module tri_inv (A, S, Z);
input A;
input S;
output Z;
assign Z = ~A; // A'
endmodule
module buffer (A, Y);
input A;
output Y;
assign Y = A; // A
endmodule
module nand2 (A, B, Y);
input A;
input B;
output Y;
assign Y = ~(A&B); // (A * B)'
endmodule
module nor2 (A, B, Y);
input A;
input B;
output Y;
assign Y = ~(A|B); // (A + B)'
endmodule
module xor2 (A, B, Y);
input A;
input B;
output Y;
assign Y = (A&~B)|(~A&B); // (A *B') + (A' * B)
endmodule
module imux2 (A, B, S, Y);
input A;
input B;
input S;
output Y;
assign Y = ~(&(A&S)|(B&~S)&); // ( (A * S) + (B * S') )'
endmodule
module dff (D, CLK, RESET, PRESET, Q, QN);
reg IQ, IQN;
input D;
input CLK;
input RESET;
input PRESET;
output Q;
assign Q = IQ; // IQ
output QN;
assign QN = IQN; // IQN
always @(posedge CLK, posedge RESET, posedge PRESET) begin
if ((RESET) && (PRESET)) begin
IQ <= 0;
IQN <= 0;
end
else if (RESET) begin
IQ <= 0;
IQN <= 1;
end
else if (PRESET) begin
IQ <= 1;
IQN <= 0;
end
else begin
// D
IQ <= D;
IQN <= ~(D);
end
end
endmodule
module latch (D, G, Q, QN);
reg IQ, IQN;
input D;
input G;
output Q;
assign Q = IQ; // IQ
output QN;
assign QN = IQN; // IQN
always @* begin
if (G) begin
IQ <= D;
IQN <= ~(D);
end
end
endmodule
module aoi211 (A, B, C, Y);
input A;
input B;
input C;
output Y;
assign Y = ~((A&B)|C); // ((A * B) + C)'
endmodule
module oai211 (A, B, C, Y);
input A;
input B;
input C;
output Y;
assign Y = ~((A|B)&C); // ((A + B) * C)'
endmodule
module halfadder (A, B, C, Y);
input A;
input B;
output C;
assign C = (A&B); // (A * B)
output Y;
assign Y = (A&~B)|(~A&B); // (A *B') + (A' * B)
endmodule
module fulladder (A, B, CI, CO, Y);
input A;
input B;
input CI;
output CO;
assign CO = (((A&B)|(B&CI))|(CI&A)); // (((A * B)+(B * CI))+(CI * A))
output Y;
assign Y = ((A^B)^CI); // ((A^B)^CI)
endmodule

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tests/liberty/processdefs.lib.filtered.ok Normal file
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library(processdefs) {
}

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tests/liberty/processdefs.lib.verilogsim.ok Normal file
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tests/liberty/run-test.sh
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set -e set -e
for x in *.lib; do for x in *.lib; do
echo "Running $x.." echo "Testing on $x.."
echo "read_verilog small.v" > test.ys echo "read_verilog small.v" > test.ys
echo "synth -top small" >> test.ys echo "synth -top small" >> test.ys
echo "dfflibmap -info -liberty ${x}" >> test.ys echo "dfflibmap -info -liberty ${x}" >> test.ys
../../yosys -ql ${x%.lib}.log -s test.ys ../../yosys -ql ${x%.lib}.log -s test.ys
../../yosys-filterlib - $x 2>/dev/null > $x.filtered
../../yosys-filterlib -verilogsim $x > $x.verilogsim
diff $x.filtered $x.filtered.ok && diff $x.verilogsim $x.verilogsim.ok
done done

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tests/liberty/semicolextra.lib.filtered.ok Normal file
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library(supergate) {
cell(DFF) {
cell_footprint : dff ;
area : 50 ;
pin(D) {
direction : input ;
}
pin(CK) {
direction : input ;
clock : true ;
}
ff(IQ, IQN) {
clocked_on : CK ;
next_state : D ;
}
pin(Q) {
direction : output ;
}
}
}

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tests/liberty/semicolextra.lib.verilogsim.ok Normal file
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module DFF (D, CK, Q);
reg IQ, IQN;
input D;
input CK;
output Q;
always @(posedge CK) begin
// D
IQ <= D;
IQN <= ~(D);
end
endmodule

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library(supergate) {
cell(fulladder) {
area : 8 ;
pin(A) {
direction : input ;
}
pin(B) {
direction : input ;
}
pin(CI) {
direction : input ;
}
pin(CO) {
direction : output ;
function : (((A * B)+(B * CI))+(CI * A)) ;
}
pin(Y) {
direction : output ;
function : ((A^B)^CI) ;
}
}
}

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module fulladder (A, B, CI, CO, Y);
input A;
input B;
input CI;
output CO;
assign CO = (((A&B)|(B&CI))|(CI&A)); // (((A * B)+(B * CI))+(CI * A))
output Y;
assign Y = ((A^B)^CI); // ((A^B)^CI)
endmodule