From c35f5e379c2542a8df99aca1711cacbe4121dbee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 13 Aug 2024 18:36:31 +0200 Subject: [PATCH] Extend liberty tests --- tests/liberty/.gitignore | 2 + tests/liberty/XNOR2X1.lib.filtered.ok | 15 ++ tests/liberty/XNOR2X1.lib.verilogsim.ok | 6 + tests/liberty/busdef.lib.filtered.ok | 8 + tests/liberty/busdef.lib.verilogsim.ok | 3 + tests/liberty/issue3498_bad.lib.filtered.ok | 4 + tests/liberty/issue3498_bad.lib.verilogsim.ok | 2 + tests/liberty/normal.lib.filtered.ok | 211 ++++++++++++++++++ tests/liberty/normal.lib.verilogsim.ok | 117 ++++++++++ tests/liberty/normal.verilogsim.ok | 117 ++++++++++ tests/liberty/processdefs.lib.filtered.ok | 2 + tests/liberty/processdefs.lib.verilogsim.ok | 0 tests/liberty/run-test.sh | 11 +- tests/liberty/semicolextra.lib.filtered.ok | 20 ++ tests/liberty/semicolextra.lib.verilogsim.ok | 11 + tests/liberty/semicolmissing.lib.filtered.ok | 22 ++ .../liberty/semicolmissing.lib.verilogsim.ok | 9 + 17 files changed, 556 insertions(+), 4 deletions(-) create mode 100644 tests/liberty/XNOR2X1.lib.filtered.ok create mode 100644 tests/liberty/XNOR2X1.lib.verilogsim.ok create mode 100644 tests/liberty/busdef.lib.filtered.ok create mode 100644 tests/liberty/busdef.lib.verilogsim.ok create mode 100644 tests/liberty/issue3498_bad.lib.filtered.ok create mode 100644 tests/liberty/issue3498_bad.lib.verilogsim.ok create mode 100644 tests/liberty/normal.lib.filtered.ok create mode 100644 tests/liberty/normal.lib.verilogsim.ok create mode 100644 tests/liberty/normal.verilogsim.ok create mode 100644 tests/liberty/processdefs.lib.filtered.ok create mode 100644 tests/liberty/processdefs.lib.verilogsim.ok create mode 100644 tests/liberty/semicolextra.lib.filtered.ok create mode 100644 tests/liberty/semicolextra.lib.verilogsim.ok create mode 100644 tests/liberty/semicolmissing.lib.filtered.ok create mode 100644 tests/liberty/semicolmissing.lib.verilogsim.ok diff --git a/tests/liberty/.gitignore b/tests/liberty/.gitignore index e6ec49c4a..bf5ba57dc 100644 --- a/tests/liberty/.gitignore +++ b/tests/liberty/.gitignore @@ -1,2 +1,4 @@ *.log test.ys +*.filtered +*.verilogsim diff --git a/tests/liberty/XNOR2X1.lib.filtered.ok b/tests/liberty/XNOR2X1.lib.filtered.ok new file mode 100644 index 000000000..14e9b625d --- /dev/null +++ b/tests/liberty/XNOR2X1.lib.filtered.ok @@ -0,0 +1,15 @@ +library(ls05_stdcells) { + cell(XNOR2X1) { + area : 206080.0 ; + pin(B) { + direction : input ; + } + pin(A) { + direction : input ; + } + pin(Y) { + direction : output ; + function : !(B&!A|!B&A) ; + } + } +} diff --git a/tests/liberty/XNOR2X1.lib.verilogsim.ok b/tests/liberty/XNOR2X1.lib.verilogsim.ok new file mode 100644 index 000000000..62c9f7ffa --- /dev/null +++ b/tests/liberty/XNOR2X1.lib.verilogsim.ok @@ -0,0 +1,6 @@ +module XNOR2X1 (B, A, Y); + input B; + input A; + output Y; + assign Y = !(B&!A|!B&A); // !(B&!A|!B&A) +endmodule diff --git a/tests/liberty/busdef.lib.filtered.ok b/tests/liberty/busdef.lib.filtered.ok new file mode 100644 index 000000000..55f5b08a3 --- /dev/null +++ b/tests/liberty/busdef.lib.filtered.ok @@ -0,0 +1,8 @@ +library(supergate) { + cell(SRAM) { + area : 1 ; + pin(CE1) { + direction : input ; + } + } +} diff --git a/tests/liberty/busdef.lib.verilogsim.ok b/tests/liberty/busdef.lib.verilogsim.ok new file mode 100644 index 000000000..5d7f47f37 --- /dev/null +++ b/tests/liberty/busdef.lib.verilogsim.ok @@ -0,0 +1,3 @@ +module SRAM (CE1); + input CE1; +endmodule diff --git a/tests/liberty/issue3498_bad.lib.filtered.ok b/tests/liberty/issue3498_bad.lib.filtered.ok new file mode 100644 index 000000000..e121193df --- /dev/null +++ b/tests/liberty/issue3498_bad.lib.filtered.ok @@ -0,0 +1,4 @@ +library(fake) { + cell(bugbad) { + } +} diff --git a/tests/liberty/issue3498_bad.lib.verilogsim.ok b/tests/liberty/issue3498_bad.lib.verilogsim.ok new file mode 100644 index 000000000..2ce41ea6c --- /dev/null +++ b/tests/liberty/issue3498_bad.lib.verilogsim.ok @@ -0,0 +1,2 @@ +module bugbad (); +endmodule diff --git a/tests/liberty/normal.lib.filtered.ok b/tests/liberty/normal.lib.filtered.ok new file mode 100644 index 000000000..757f09cab --- /dev/null +++ b/tests/liberty/normal.lib.filtered.ok @@ -0,0 +1,211 @@ +library(supergate) { + cell(inv) { + area : 1 ; + pin(A) { + direction : input ; + } + pin(Y) { + direction : output ; + function : A' ; + } + } + cell(tri_inv) { + area : 4 ; + pin(A) { + direction : input ; + } + pin(S) { + direction : input ; + } + pin(Z) { + direction : output ; + function : A' ; + } + } + cell(buffer) { + area : 5 ; + pin(A) { + direction : input ; + } + pin(Y) { + direction : output ; + function : A ; + } + } + cell(nand2) { + area : 3 ; + pin(A) { + direction : input ; + } + pin(B) { + direction : input ; + } + pin(Y) { + direction : output ; + function : (A * B)' ; + } + } + cell(nor2) { + area : 3 ; + pin(A) { + direction : input ; + } + pin(B) { + direction : input ; + } + pin(Y) { + direction : output ; + function : (A + B)' ; + } + } + cell(xor2) { + area : 6 ; + pin(A) { + direction : input ; + } + pin(B) { + direction : input ; + } + pin(Y) { + direction : output ; + function : (A *B') + (A' * B) ; + } + } + cell(imux2) { + area : 5 ; + pin(A) { + direction : input ; + } + pin(B) { + direction : input ; + } + pin(S) { + direction : input ; + } + pin(Y) { + direction : output ; + function : ( (A * S) + (B * S') )' ; + } + } + cell(dff) { + area : 6 ; + ff(IQ, IQN) { + next_state : D ; + clocked_on : CLK ; + clear : RESET ; + preset : PRESET ; + clear_preset_var1 : L ; + clear_preset_var2 : L ; + } + pin(D) { + direction : input ; + } + pin(CLK) { + direction : input ; + } + pin(RESET) { + direction : input ; + } + pin(PRESET) { + direction : input ; + } + pin(Q) { + direction : output ; + function : IQ ; + } + pin(QN) { + direction : output ; + function : IQN ; + } + } + cell(latch) { + area : 5 ; + latch(IQ, IQN) { + enable : G ; + data_in : D ; + } + pin(D) { + direction : input ; + } + pin(G) { + direction : input ; + } + pin(Q) { + direction : output ; + function : IQ ; + } + pin(QN) { + direction : output ; + function : IQN ; + } + } + cell(aoi211) { + area : 3 ; + pin(A) { + direction : input ; + } + pin(B) { + direction : input ; + } + pin(C) { + direction : input ; + } + pin(Y) { + direction : output ; + function : ((A * B) + C)' ; + } + } + cell(oai211) { + area : 3 ; + pin(A) { + direction : input ; + } + pin(B) { + direction : input ; + } + pin(C) { + direction : input ; + } + pin(Y) { + direction : output ; + function : ((A + B) * C)' ; + } + } + cell(halfadder) { + area : 5 ; + pin(A) { + direction : input ; + } + pin(B) { + direction : input ; + } + pin(C) { + direction : output ; + function : (A * B) ; + } + pin(Y) { + direction : output ; + function : (A *B') + (A' * B) ; + } + } + cell(fulladder) { + area : 8 ; + pin(A) { + direction : input ; + } + pin(B) { + direction : input ; + } + pin(CI) { + direction : input ; + } + pin(CO) { + direction : output ; + function : (((A * B)+(B * CI))+(CI * A)) ; + } + pin(Y) { + direction : output ; + function : ((A^B)^CI) ; + } + } +} diff --git a/tests/liberty/normal.lib.verilogsim.ok b/tests/liberty/normal.lib.verilogsim.ok new file mode 100644 index 000000000..30f164a31 --- /dev/null +++ b/tests/liberty/normal.lib.verilogsim.ok @@ -0,0 +1,117 @@ +module inv (A, Y); + input A; + output Y; + assign Y = ~A; // A' +endmodule +module tri_inv (A, S, Z); + input A; + input S; + output Z; + assign Z = ~A; // A' +endmodule +module buffer (A, Y); + input A; + output Y; + assign Y = A; // A +endmodule +module nand2 (A, B, Y); + input A; + input B; + output Y; + assign Y = ~(A&B); // (A * B)' +endmodule +module nor2 (A, B, Y); + input A; + input B; + output Y; + assign Y = ~(A|B); // (A + B)' +endmodule +module xor2 (A, B, Y); + input A; + input B; + output Y; + assign Y = (A&~B)|(~A&B); // (A *B') + (A' * B) +endmodule +module imux2 (A, B, S, Y); + input A; + input B; + input S; + output Y; + assign Y = ~(&(A&S)|(B&~S)&); // ( (A * S) + (B * S') )' +endmodule +module dff (D, CLK, RESET, PRESET, Q, QN); + reg IQ, IQN; + input D; + input CLK; + input RESET; + input PRESET; + output Q; + assign Q = IQ; // IQ + output QN; + assign QN = IQN; // IQN + always @(posedge CLK, posedge RESET, posedge PRESET) begin + if ((RESET) && (PRESET)) begin + IQ <= 0; + IQN <= 0; + end + else if (RESET) begin + IQ <= 0; + IQN <= 1; + end + else if (PRESET) begin + IQ <= 1; + IQN <= 0; + end + else begin + // D + IQ <= D; + IQN <= ~(D); + end + end +endmodule +module latch (D, G, Q, QN); + reg IQ, IQN; + input D; + input G; + output Q; + assign Q = IQ; // IQ + output QN; + assign QN = IQN; // IQN + always @* begin + if (G) begin + IQ <= D; + IQN <= ~(D); + end + end +endmodule +module aoi211 (A, B, C, Y); + input A; + input B; + input C; + output Y; + assign Y = ~((A&B)|C); // ((A * B) + C)' +endmodule +module oai211 (A, B, C, Y); + input A; + input B; + input C; + output Y; + assign Y = ~((A|B)&C); // ((A + B) * C)' +endmodule +module halfadder (A, B, C, Y); + input A; + input B; + output C; + assign C = (A&B); // (A * B) + output Y; + assign Y = (A&~B)|(~A&B); // (A *B') + (A' * B) +endmodule +module fulladder (A, B, CI, CO, Y); + input A; + input B; + input CI; + output CO; + assign CO = (((A&B)|(B&CI))|(CI&A)); // (((A * B)+(B * CI))+(CI * A)) + output Y; + assign Y = ((A^B)^CI); // ((A^B)^CI) +endmodule diff --git a/tests/liberty/normal.verilogsim.ok b/tests/liberty/normal.verilogsim.ok new file mode 100644 index 000000000..30f164a31 --- /dev/null +++ b/tests/liberty/normal.verilogsim.ok @@ -0,0 +1,117 @@ +module inv (A, Y); + input A; + output Y; + assign Y = ~A; // A' +endmodule +module tri_inv (A, S, Z); + input A; + input S; + output Z; + assign Z = ~A; // A' +endmodule +module buffer (A, Y); + input A; + output Y; + assign Y = A; // A +endmodule +module nand2 (A, B, Y); + input A; + input B; + output Y; + assign Y = ~(A&B); // (A * B)' +endmodule +module nor2 (A, B, Y); + input A; + input B; + output Y; + assign Y = ~(A|B); // (A + B)' +endmodule +module xor2 (A, B, Y); + input A; + input B; + output Y; + assign Y = (A&~B)|(~A&B); // (A *B') + (A' * B) +endmodule +module imux2 (A, B, S, Y); + input A; + input B; + input S; + output Y; + assign Y = ~(&(A&S)|(B&~S)&); // ( (A * S) + (B * S') )' +endmodule +module dff (D, CLK, RESET, PRESET, Q, QN); + reg IQ, IQN; + input D; + input CLK; + input RESET; + input PRESET; + output Q; + assign Q = IQ; // IQ + output QN; + assign QN = IQN; // IQN + always @(posedge CLK, posedge RESET, posedge PRESET) begin + if ((RESET) && (PRESET)) begin + IQ <= 0; + IQN <= 0; + end + else if (RESET) begin + IQ <= 0; + IQN <= 1; + end + else if (PRESET) begin + IQ <= 1; + IQN <= 0; + end + else begin + // D + IQ <= D; + IQN <= ~(D); + end + end +endmodule +module latch (D, G, Q, QN); + reg IQ, IQN; + input D; + input G; + output Q; + assign Q = IQ; // IQ + output QN; + assign QN = IQN; // IQN + always @* begin + if (G) begin + IQ <= D; + IQN <= ~(D); + end + end +endmodule +module aoi211 (A, B, C, Y); + input A; + input B; + input C; + output Y; + assign Y = ~((A&B)|C); // ((A * B) + C)' +endmodule +module oai211 (A, B, C, Y); + input A; + input B; + input C; + output Y; + assign Y = ~((A|B)&C); // ((A + B) * C)' +endmodule +module halfadder (A, B, C, Y); + input A; + input B; + output C; + assign C = (A&B); // (A * B) + output Y; + assign Y = (A&~B)|(~A&B); // (A *B') + (A' * B) +endmodule +module fulladder (A, B, CI, CO, Y); + input A; + input B; + input CI; + output CO; + assign CO = (((A&B)|(B&CI))|(CI&A)); // (((A * B)+(B * CI))+(CI * A)) + output Y; + assign Y = ((A^B)^CI); // ((A^B)^CI) +endmodule diff --git a/tests/liberty/processdefs.lib.filtered.ok b/tests/liberty/processdefs.lib.filtered.ok new file mode 100644 index 000000000..d50f0e17b --- /dev/null +++ b/tests/liberty/processdefs.lib.filtered.ok @@ -0,0 +1,2 @@ +library(processdefs) { +} diff --git a/tests/liberty/processdefs.lib.verilogsim.ok b/tests/liberty/processdefs.lib.verilogsim.ok new file mode 100644 index 000000000..e69de29bb diff --git a/tests/liberty/run-test.sh b/tests/liberty/run-test.sh index 19ce0667d..07d2cce1c 100755 --- a/tests/liberty/run-test.sh +++ b/tests/liberty/run-test.sh @@ -2,9 +2,12 @@ set -e for x in *.lib; do - echo "Running $x.." - echo "read_verilog small.v" > test.ys - echo "synth -top small" >> test.ys - echo "dfflibmap -info -liberty ${x}" >> test.ys + echo "Testing on $x.." + echo "read_verilog small.v" > test.ys + echo "synth -top small" >> test.ys + echo "dfflibmap -info -liberty ${x}" >> test.ys ../../yosys -ql ${x%.lib}.log -s test.ys + ../../yosys-filterlib - $x 2>/dev/null > $x.filtered + ../../yosys-filterlib -verilogsim $x > $x.verilogsim + diff $x.filtered $x.filtered.ok && diff $x.verilogsim $x.verilogsim.ok done diff --git a/tests/liberty/semicolextra.lib.filtered.ok b/tests/liberty/semicolextra.lib.filtered.ok new file mode 100644 index 000000000..791b45084 --- /dev/null +++ b/tests/liberty/semicolextra.lib.filtered.ok @@ -0,0 +1,20 @@ +library(supergate) { + cell(DFF) { + cell_footprint : dff ; + area : 50 ; + pin(D) { + direction : input ; + } + pin(CK) { + direction : input ; + clock : true ; + } + ff(IQ, IQN) { + clocked_on : CK ; + next_state : D ; + } + pin(Q) { + direction : output ; + } + } +} diff --git a/tests/liberty/semicolextra.lib.verilogsim.ok b/tests/liberty/semicolextra.lib.verilogsim.ok new file mode 100644 index 000000000..c9eebd6ed --- /dev/null +++ b/tests/liberty/semicolextra.lib.verilogsim.ok @@ -0,0 +1,11 @@ +module DFF (D, CK, Q); + reg IQ, IQN; + input D; + input CK; + output Q; + always @(posedge CK) begin + // D + IQ <= D; + IQN <= ~(D); + end +endmodule diff --git a/tests/liberty/semicolmissing.lib.filtered.ok b/tests/liberty/semicolmissing.lib.filtered.ok new file mode 100644 index 000000000..29022cf80 --- /dev/null +++ b/tests/liberty/semicolmissing.lib.filtered.ok @@ -0,0 +1,22 @@ +library(supergate) { + cell(fulladder) { + area : 8 ; + pin(A) { + direction : input ; + } + pin(B) { + direction : input ; + } + pin(CI) { + direction : input ; + } + pin(CO) { + direction : output ; + function : (((A * B)+(B * CI))+(CI * A)) ; + } + pin(Y) { + direction : output ; + function : ((A^B)^CI) ; + } + } +} diff --git a/tests/liberty/semicolmissing.lib.verilogsim.ok b/tests/liberty/semicolmissing.lib.verilogsim.ok new file mode 100644 index 000000000..131ce2fdf --- /dev/null +++ b/tests/liberty/semicolmissing.lib.verilogsim.ok @@ -0,0 +1,9 @@ +module fulladder (A, B, CI, CO, Y); + input A; + input B; + input CI; + output CO; + assign CO = (((A&B)|(B&CI))|(CI&A)); // (((A * B)+(B * CI))+(CI * A)) + output Y; + assign Y = ((A^B)^CI); // ((A^B)^CI) +endmodule