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Extend liberty tests

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This commit is contained in:
Martin Povišer 2024-08-13 18:36:31 +02:00
parent 78382eaa6f
commit c35f5e379c
17 changed files with 556 additions and 4 deletions
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tests/liberty/semicolmissing.lib.verilogsim.ok Normal file
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module fulladder (A, B, CI, CO, Y);
input A;
input B;
input CI;
output CO;
assign CO = (((A&B)|(B&CI))|(CI&A)); // (((A * B)+(B * CI))+(CI * A))
output Y;
assign Y = ((A^B)^CI); // ((A^B)^CI)
endmodule