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Extend liberty tests

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Martin Povišer 2024-08-13 18:36:31 +02:00
parent 78382eaa6f
commit c35f5e379c
17 changed files with 556 additions and 4 deletions
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tests/liberty/normal.verilogsim.ok Normal file
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module inv (A, Y);
input A;
output Y;
assign Y = ~A; // A'
endmodule
module tri_inv (A, S, Z);
input A;
input S;
output Z;
assign Z = ~A; // A'
endmodule
module buffer (A, Y);
input A;
output Y;
assign Y = A; // A
endmodule
module nand2 (A, B, Y);
input A;
input B;
output Y;
assign Y = ~(A&B); // (A * B)'
endmodule
module nor2 (A, B, Y);
input A;
input B;
output Y;
assign Y = ~(A|B); // (A + B)'
endmodule
module xor2 (A, B, Y);
input A;
input B;
output Y;
assign Y = (A&~B)|(~A&B); // (A *B') + (A' * B)
endmodule
module imux2 (A, B, S, Y);
input A;
input B;
input S;
output Y;
assign Y = ~(&(A&S)|(B&~S)&); // ( (A * S) + (B * S') )'
endmodule
module dff (D, CLK, RESET, PRESET, Q, QN);
reg IQ, IQN;
input D;
input CLK;
input RESET;
input PRESET;
output Q;
assign Q = IQ; // IQ
output QN;
assign QN = IQN; // IQN
always @(posedge CLK, posedge RESET, posedge PRESET) begin
if ((RESET) && (PRESET)) begin
IQ <= 0;
IQN <= 0;
end
else if (RESET) begin
IQ <= 0;
IQN <= 1;
end
else if (PRESET) begin
IQ <= 1;
IQN <= 0;
end
else begin
// D
IQ <= D;
IQN <= ~(D);
end
end
endmodule
module latch (D, G, Q, QN);
reg IQ, IQN;
input D;
input G;
output Q;
assign Q = IQ; // IQ
output QN;
assign QN = IQN; // IQN
always @* begin
if (G) begin
IQ <= D;
IQN <= ~(D);
end
end
endmodule
module aoi211 (A, B, C, Y);
input A;
input B;
input C;
output Y;
assign Y = ~((A&B)|C); // ((A * B) + C)'
endmodule
module oai211 (A, B, C, Y);
input A;
input B;
input C;
output Y;
assign Y = ~((A|B)&C); // ((A + B) * C)'
endmodule
module halfadder (A, B, C, Y);
input A;
input B;
output C;
assign C = (A&B); // (A * B)
output Y;
assign Y = (A&~B)|(~A&B); // (A *B') + (A' * B)
endmodule
module fulladder (A, B, CI, CO, Y);
input A;
input B;
input CI;
output CO;
assign CO = (((A&B)|(B&CI))|(CI&A)); // (((A * B)+(B * CI))+(CI * A))
output Y;
assign Y = ((A^B)^CI); // ((A^B)^CI)
endmodule