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Extend liberty tests

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This commit is contained in:
Martin Povišer 2024-08-13 18:36:31 +02:00
parent 78382eaa6f
commit c35f5e379c
17 changed files with 556 additions and 4 deletions
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tests/liberty/XNOR2X1.lib.verilogsim.ok Normal file
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module XNOR2X1 (B, A, Y);
input B;
input A;
output Y;
assign Y = !(B&!A|!B&A); // !(B&!A|!B&A)
endmodule