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This commit is contained in:
Emil J. Tywoniak 2026-05-29 11:59:27 +02:00
parent dab9a386cc
commit c3457e2e5c
35 changed files with 204 additions and 63 deletions
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18
techlibs/common/simlib.v
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@ -3250,3 +3250,21 @@ parameter WIDTH = 0;
inout [WIDTH-1:0] Y;
endmodule
// --------------------------------------------------------
//* group wire
module \$output_port (A);
parameter WIDTH = 0;
input [WIDTH-1:0] A;
endmodule
// --------------------------------------------------------
//* group wire
module \$public (A);
parameter WIDTH = 0;
input [WIDTH-1:0] A;
endmodule

18
techlibs/common/techmap.v
View file

@ -637,3 +637,21 @@ parameter WIDTH = 0;
inout [WIDTH-1:0] Y; // This cell is just a maker, so we leave Y undriven
endmodule
(* techmap_celltype = "$output_port" *)
module \$output_port (A);
parameter WIDTH = 0;
input [WIDTH-1:0] A; // This cell is just a marker for module output ports
endmodule
(* techmap_celltype = "$public" *)
module \$public (A);
parameter WIDTH = 0;
input [WIDTH-1:0] A; // This cell is just a marker for public-named wires
endmodule