From c3457e2e5cb1680fe5e11e44add7abb7d4894e6f Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Fri, 29 May 2026 11:59:27 +0200 Subject: [PATCH] WIP --- backends/aiger/aiger.cc | 2 +- backends/aiger2/aiger.cc | 2 +- backends/cxxrtl/cxxrtl_backend.cc | 2 +- backends/verilog/verilog_backend.cc | 2 +- kernel/celltypes.h | 2 + kernel/constids.inc | 2 + kernel/newcelltypes.h | 2 + kernel/rtlil.cc | 6 +++ kernel/rtlil_bufnorm.cc | 69 ++++++++++++++++++++++++++- kernel/satgen.cc | 2 +- kernel/unstable/patch.cc | 7 +++ passes/cmds/abstract.cc | 2 +- passes/cmds/check.cc | 2 +- passes/cmds/portarcs.cc | 2 +- passes/equiv/equiv_make.cc | 4 +- passes/equiv/equiv_miter.cc | 2 +- passes/fsm/fsm_detect.cc | 2 + passes/hierarchy/flatten.cc | 2 +- passes/opt/opt_clean/cells_temp.cc | 14 ++++-- passes/opt/opt_merge_inc.cc | 2 + passes/opt/opt_share.cc | 5 +- passes/sat/sim.cc | 3 ++ passes/techmap/arith_tree.cc | 5 +- techlibs/common/simlib.v | 18 +++++++ techlibs/common/techmap.v | 18 +++++++ tests/opt/bug1758.ys | 4 +- tests/opt/opt_dff_dffmux.ys | 14 +++--- tests/opt/opt_expr_alu.ys | 16 +++---- tests/opt/opt_expr_and.ys | 16 +++---- tests/opt/opt_expr_more.ys | 8 ++-- tests/opt/opt_expr_or.ys | 16 +++---- tests/opt/opt_expr_xnor.ys | 2 +- tests/opt/opt_expr_xor.ys | 8 ++-- tests/techmap/clockgate.tcl | 2 +- tests/various/rename_scramble_name.ys | 2 +- 35 files changed, 204 insertions(+), 63 deletions(-) diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc index 8283e1131..a2dc3a4af 100644 --- a/backends/aiger/aiger.cc +++ b/backends/aiger/aiger.cc @@ -337,7 +337,7 @@ struct AigerWriter continue; } - if (cell->type == ID($scopeinfo) || cell->type == ID($input_port)) + if (cell->type.in(ID($scopeinfo), ID($input_port), ID($output_port), ID($public))) continue; log_error("Unsupported cell type: %s (%s)\n", cell->type.unescape(), cell); diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 0dceaedd6..eb5ac4a64 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -109,7 +109,7 @@ struct Index { int pos = index_wires(info, m); for (auto cell : m->cells()) { - if (known_ops(cell->type) || cell->type.in(ID($scopeinfo), ID($specify2), ID($specify3), ID($input_port))) + if (known_ops(cell->type) || cell->type.in(ID($scopeinfo), ID($specify2), ID($specify3), ID($input_port), ID($output_port), ID($public))) continue; Module *submodule = m->design->module(cell->type); diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index adb3919b0..5fd35e759 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -1518,7 +1518,7 @@ struct CxxrtlWorker { f << (cell->getParam(ID::CLR_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n"; } // Internal cells - } else if (cell->type == ID($input_port)) { + } else if (cell->type.in(ID($input_port), ID($output_port), ID($public))) { } else if (is_internal_cell(cell->type)) { log_cmd_error("Unsupported internal cell `%s'.\n", cell->type); // User cells diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 473918264..7362f4190 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1542,7 +1542,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } - if (cell->type == ID($input_port)) + if (cell->type.in(ID($input_port), ID($output_port), ID($public))) return true; if (cell->type == ID($connect)) diff --git a/kernel/celltypes.h b/kernel/celltypes.h index ceff0bd1a..d67bb29e1 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -113,6 +113,8 @@ struct CellTypes setup_type(ID($future_ff), {ID::A}, {ID::Y}); setup_type(ID($scopeinfo), {}, {}); setup_type(ID($input_port), {}, {ID::Y}); + setup_type(ID($output_port), {ID::A}, {}); + setup_type(ID($public), {ID::A}, {}); setup_type(ID($connect), {ID::A, ID::B}, {}); } diff --git a/kernel/constids.inc b/kernel/constids.inc index cfd12e3fb..1c3055c92 100644 --- a/kernel/constids.inc +++ b/kernel/constids.inc @@ -253,12 +253,14 @@ X($not) X($or) X($original_tag) X($output) +X($output_port) X($overwrite_tag) X($pending) X($pmux) X($pos) X($pow) X($print) +X($public) X($recrem) X($reduce_and) X($reduce_bool) diff --git a/kernel/newcelltypes.h b/kernel/newcelltypes.h index eb42019af..a300948ee 100644 --- a/kernel/newcelltypes.h +++ b/kernel/newcelltypes.h @@ -90,6 +90,8 @@ struct CellTableBuilder { setup_type(ID($future_ff), {ID::A}, {ID::Y}, features); setup_type(ID($scopeinfo), {}, {}, features); setup_type(ID($input_port), {}, {ID::Y}, features); + setup_type(ID($output_port), {ID::A}, {}, features); + setup_type(ID($public), {ID::A}, {}, features); setup_type(ID($connect), {ID::A, ID::B}, {}, features); } constexpr void setup_internals_eval() diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index e3a1e84b1..b9a2b5fa8 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2539,6 +2539,12 @@ namespace { check_expected(); return; } + if (cell->type.in(ID($output_port), ID($public))) { + param(ID::WIDTH); + port(ID::A, param(ID::WIDTH)); + check_expected(); + return; + } if (cell->type.in(ID($connect))) { param(ID::WIDTH); port(ID::A, param(ID::WIDTH)); diff --git a/kernel/rtlil_bufnorm.cc b/kernel/rtlil_bufnorm.cc index e2eaafdfb..6e48def17 100644 --- a/kernel/rtlil_bufnorm.cc +++ b/kernel/rtlil_bufnorm.cc @@ -54,6 +54,7 @@ struct RTLIL::SigNormIndex module->fixup_ports(); setup_module_inputs(); setup_driven_wires(); + setup_module_outputs_and_publics(); setup_fanout(); } @@ -110,6 +111,72 @@ struct RTLIL::SigNormIndex } } + // Creates $output_port cells consuming each pure-output module port wire + // and $public cells consuming each public-named wire that isn't already + // covered by an $input_port or $output_port. These act as fanout sentinels + // so local GC (e.g. in Patch) won't remove driver cells whose only purpose + // is to feed a port or a user-visible wire. + void setup_module_outputs_and_publics() { + std::vector cells_to_remove; + dict output_port_cells; + dict public_cells; + + for (auto cell : module->cells()) { + if (cell->type != ID($output_port) && cell->type != ID($public)) + continue; + + auto const &sig_a = cell->getPort(ID::A); + Wire *wire = nullptr; + if (!sig_a.is_wire()) { + cells_to_remove.push_back(cell); + continue; + } + wire = sig_a.as_wire(); + + if (cell->type == ID($output_port)) { + if (wire->port_output && !wire->port_input && !output_port_cells.count(wire)) + output_port_cells.emplace(wire, cell); + else + cells_to_remove.push_back(cell); + } else { // $public + bool is_pure_input = wire->port_input && !wire->port_output; + bool is_pure_output = wire->port_output && !wire->port_input; + if (wire->name.isPublic() && !is_pure_input && !is_pure_output && !public_cells.count(wire)) + public_cells.emplace(wire, cell); + else + cells_to_remove.push_back(cell); + } + } + for (auto cell : cells_to_remove) + module->remove(cell); + + for (auto portname : module->ports) { + Wire *wire = module->wire(portname); + if (wire->port_output && !wire->port_input && !output_port_cells.count(wire)) { + Cell *cell = module->addCell(NEW_ID, ID($output_port)); + cell->setParam(ID::WIDTH, GetSize(wire)); + cell->setPort(ID::A, wire); + output_port_cells.emplace(wire, cell); + } + } + + for (auto &it : module->wires_) { + Wire *wire = it.second; + if (!wire->name.isPublic()) + continue; + bool is_pure_input = wire->port_input && !wire->port_output; + bool is_pure_output = wire->port_output && !wire->port_input; + if (is_pure_input || is_pure_output) + continue; + if (public_cells.count(wire)) + continue; + Cell *cell = module->addCell(NEW_ID, ID($public)); + cell->setParam(ID::WIDTH, GetSize(wire)); + cell->setPort(ID::A, wire); + public_cells.emplace(wire, cell); + } + } + void setup_driven_wires() { for (auto cell : module->cells()) { xlog("setup_driven_wires cell %s %s\n", cell->type, cell->name); @@ -352,7 +419,7 @@ void RTLIL::Design::sigNormalize(bool enable) // TODO inefficient? std::vector cells_snapshot = module->cells(); for (auto cell : cells_snapshot) { - if (cell->type == ID($input_port)) + if (cell->type.in(ID($input_port), ID($output_port), ID($public))) module->remove(cell); } } diff --git a/kernel/satgen.cc b/kernel/satgen.cc index 93350c1f8..e9c27cae1 100644 --- a/kernel/satgen.cc +++ b/kernel/satgen.cc @@ -1399,7 +1399,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) return true; } - if (cell->type == ID($scopeinfo) || cell->type == ID($input_port)) + if (cell->type.in(ID($scopeinfo), ID($input_port), ID($output_port), ID($public))) { return true; } diff --git a/kernel/unstable/patch.cc b/kernel/unstable/patch.cc index a8dfc68ba..43fe439b0 100644 --- a/kernel/unstable/patch.cc +++ b/kernel/unstable/patch.cc @@ -178,6 +178,13 @@ void Patch::patch(Cell* old_cell, IdString old_port, SigSpec new_sig) { for (auto& wire: wires_) commit_wire(std::move(wire)); + // Flush pending sigmap updates (from the mod->connect above) into the + // fanout index so gc() sees the updated fanout for cells whose outputs + // were the patched wires. Without this, downstream consumers like the + // $output_port / $public sentinels still appear in the OLD wire's fanout + // instead of the new representative. + mod->sigNormalize(); + gc(old_cell); cells_.clear(); wires_.clear(); diff --git a/passes/cmds/abstract.cc b/passes/cmds/abstract.cc index 18641a325..c4840fefc 100644 --- a/passes/cmds/abstract.cc +++ b/passes/cmds/abstract.cc @@ -265,7 +265,7 @@ unsigned int abstract_value(Module* mod, EnableLogic enable, const std::vector cells_snapshot = mod->cells(); for (auto cell : cells_snapshot) { - if (cell->type == ID($input_port)) + if (cell->type.in(ID($input_port), ID($output_port), ID($public))) continue; for (auto conn : cell->connections()) if (cell->output(conn.first)) { diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index 94a37ee79..9fb648748 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -358,7 +358,7 @@ struct CheckPass : public Pass { pool coarsened_cells; for (auto cell : module->cells()) { - if (cell->type == ID($input_port)) + if (cell->type.in(ID($input_port), ID($output_port), ID($public))) continue; if (mapped && cell->type.begins_with("$") && design->module(cell->type) == nullptr) { diff --git a/passes/cmds/portarcs.cc b/passes/cmds/portarcs.cc index 89a4581ce..0644719d7 100644 --- a/passes/cmds/portarcs.cc +++ b/passes/cmds/portarcs.cc @@ -125,7 +125,7 @@ struct PortarcsPass : Pass { for (auto cell : m->cells()) // Ignore all bufnorm helper cells - if (!cell->type.in(ID($buf), ID($input_port), ID($connect), ID($tribuf))) { + if (!cell->type.in(ID($buf), ID($input_port), ID($output_port), ID($public), ID($connect), ID($tribuf))) { auto tdata = tinfo.find(cell->type); if (tdata == tinfo.end()) log_cmd_error("Missing timing data for module '%s'.\n", cell->type.unescape()); diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index 5d5a96dcd..7d5ede9b6 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -115,7 +115,7 @@ struct EquivMakeWorker if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0) cell_names.insert(it->name); gold_clone->rename(it, it->name.str() + "_gold"); - if (it->type == ID($input_port)) + if (it->type.in(ID($input_port), ID($output_port), ID($public))) gold_clone->remove(it); } @@ -129,7 +129,7 @@ struct EquivMakeWorker if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0) cell_names.insert(it->name); gate_clone->rename(it, it->name.str() + "_gate"); - if (it->type == ID($input_port)) + if (it->type.in(ID($input_port), ID($output_port), ID($public))) gate_clone->remove(it); } diff --git a/passes/equiv/equiv_miter.cc b/passes/equiv/equiv_miter.cc index bcdd2bc6f..c0b96e199 100644 --- a/passes/equiv/equiv_miter.cc +++ b/passes/equiv/equiv_miter.cc @@ -143,7 +143,7 @@ struct EquivMiterWorker for (auto w : miter_wires) miter_module->addWire(w->name, w->width); for (auto c : miter_cells) { - if (c->type == ID($input_port)) + if (c->type.in(ID($input_port), ID($output_port), ID($public))) continue; auto mc = miter_module->addCell(c->name, c); for (auto &conn : mc->connections()) diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 7f5107ce9..ad53ba187 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -99,6 +99,8 @@ static bool check_state_users(RTLIL::SigSpec sig) RTLIL::Cell *cell = cellport.first; if (muxtree_cells.count(cell) > 0) continue; + if (cell->type.in(ID($input_port), ID($output_port), ID($public))) + continue; if (cell->type == ID($logic_not) && assign_map(cell->getPort(ID::A)) == sig) continue; if (cellport.second != ID::A && cellport.second != ID::B) diff --git a/passes/hierarchy/flatten.cc b/passes/hierarchy/flatten.cc index 3131650f4..94a31c930 100644 --- a/passes/hierarchy/flatten.cc +++ b/passes/hierarchy/flatten.cc @@ -178,7 +178,7 @@ struct FlattenWorker } for (auto tpl_cell : tpl->cells()) { - if (tpl_cell->type == ID($input_port)) + if (tpl_cell->type.in(ID($input_port), ID($output_port), ID($public))) continue; RTLIL::Cell *new_cell = module->addCell(map_name(cell, tpl_cell, separator), tpl_cell); map_attributes(cell, new_cell, tpl_cell->name); diff --git a/passes/opt/opt_clean/cells_temp.cc b/passes/opt/opt_clean/cells_temp.cc index b265dd5e2..693cfa096 100644 --- a/passes/opt/opt_clean/cells_temp.cc +++ b/passes/opt/opt_clean/cells_temp.cc @@ -50,9 +50,9 @@ bool trim_buf(RTLIL::Cell* cell, ShardedVector& new_connections, } bool remove(ShardedVector& cells, RTLIL::Module* mod, bool verbose) { - // Removing $connect and $input_port doesn't count as "doing something" - // since they get rebuilt in signorm - // and don't enable further opt + // Removing $connect, $input_port, $output_port and $public doesn't count + // as "doing something" since they get rebuilt in signorm and don't enable + // further opt bool did_something = false; for (RTLIL::Cell *cell : cells) { if (verbose) { @@ -62,6 +62,12 @@ bool remove(ShardedVector& cells, RTLIL::Module* mod, bool verbose } else if (cell->type == ID($input_port)) { log_debug(" removing input port marker cell `%s': %s\n", cell->name, log_signal(cell->getPort(ID::Y))); + } else if (cell->type == ID($output_port)) { + log_debug(" removing output port marker cell `%s': %s\n", cell->name, + log_signal(cell->getPort(ID::A))); + } else if (cell->type == ID($public)) { + log_debug(" removing public wire marker cell `%s': %s\n", cell->name, + log_signal(cell->getPort(ID::A))); } else { did_something = true; log_debug(" removing buffer cell `%s': %s = %s\n", cell->name, @@ -93,7 +99,7 @@ void remove_temporary_cells(RTLIL::Module *module, ParallelDispatchThreadPool::S std::swap(a, b); new_connections.insert(ctx, {a, b}); delcells.insert(ctx, cell); - } else if (cell->type.in(ID($input_port)) && !cell->has_keep_attr()) { + } else if (cell->type.in(ID($input_port), ID($output_port), ID($public)) && !cell->has_keep_attr()) { delcells.insert(ctx, cell); } } diff --git a/passes/opt/opt_merge_inc.cc b/passes/opt/opt_merge_inc.cc index 37a2f6abb..1150041ae 100644 --- a/passes/opt/opt_merge_inc.cc +++ b/passes/opt/opt_merge_inc.cc @@ -52,6 +52,8 @@ static constexpr MergeableTypes build_mergeable_types(bool nomux) { c.set_id(ID($allconst), false); c.set_id(ID($connect), false); c.set_id(ID($input_port), false); + c.set_id(ID($output_port), false); + c.set_id(ID($public), false); if (nomux) { c.set_id(ID($mux), false); c.set_id(ID($pmux), false); diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index b213048aa..11740e134 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -363,10 +363,13 @@ struct OptSharePass : public Pass { dict bit_users; - for (auto cell : module->cells()) + for (auto cell : module->cells()) { + if (cell->type.in(ID($input_port), ID($output_port), ID($public))) + continue; for (auto conn : cell->connections()) for (auto bit : conn.second) bit_users[sigmap(bit)]++; + } for (auto wire : module->wires()) if (wire->port_id != 0) diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 3de13cc1a..693906436 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -602,6 +602,9 @@ struct SimInstance if (cell->type == ID($print)) return; + if (cell->type.in(ID($input_port), ID($output_port), ID($public), ID($connect))) + return; + log_error("Unsupported cell type: %s (%s.%s)\n", cell->type.unescape(), module, cell); } diff --git a/passes/techmap/arith_tree.cc b/passes/techmap/arith_tree.cc index 259e0c5bb..2a8419b44 100644 --- a/passes/techmap/arith_tree.cc +++ b/passes/techmap/arith_tree.cc @@ -29,11 +29,14 @@ struct Traversal { dict fanout; Traversal(Module *module) : sigmap(module) { - for (auto cell : module->cells()) + for (auto cell : module->cells()) { + if (cell->type.in(ID($input_port), ID($output_port), ID($public))) + continue; for (auto &conn : cell->connections()) if (cell->input(conn.first)) for (auto bit : sigmap(conn.second)) bit_consumers[bit].insert(cell); + } for (auto &pair : bit_consumers) fanout[pair.first] = pair.second.size(); diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 3f34bfd22..b32470fd3 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -3250,3 +3250,21 @@ parameter WIDTH = 0; inout [WIDTH-1:0] Y; endmodule +// -------------------------------------------------------- +//* group wire +module \$output_port (A); + +parameter WIDTH = 0; + +input [WIDTH-1:0] A; + +endmodule +// -------------------------------------------------------- +//* group wire +module \$public (A); + +parameter WIDTH = 0; + +input [WIDTH-1:0] A; + +endmodule diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index 8061b2e81..9387adf7d 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -637,3 +637,21 @@ parameter WIDTH = 0; inout [WIDTH-1:0] Y; // This cell is just a maker, so we leave Y undriven endmodule + +(* techmap_celltype = "$output_port" *) +module \$output_port (A); + +parameter WIDTH = 0; + +input [WIDTH-1:0] A; // This cell is just a marker for module output ports + +endmodule + +(* techmap_celltype = "$public" *) +module \$public (A); + +parameter WIDTH = 0; + +input [WIDTH-1:0] A; // This cell is just a marker for public-named wires + +endmodule diff --git a/tests/opt/bug1758.ys b/tests/opt/bug1758.ys index f0a98d413..b12f39aff 100644 --- a/tests/opt/bug1758.ys +++ b/tests/opt/bug1758.ys @@ -8,11 +8,11 @@ copy gold fine cd coarse opt_expr -select -assert-none c:* t:$input_port %d +select -assert-none c:* t:$*_port %d t:$public %d cd fine opt_expr -select -assert-none c:* t:$input_port %d +select -assert-none c:* t:$*_port %d t:$public %d cd miter -equiv -flatten -make_assert -make_outputs coarse fine miter sat -verify -prove-asserts -show-ports miter diff --git a/tests/opt/opt_dff_dffmux.ys b/tests/opt/opt_dff_dffmux.ys index e47173409..491621f07 100644 --- a/tests/opt/opt_dff_dffmux.ys +++ b/tests/opt/opt_dff_dffmux.ys @@ -9,7 +9,7 @@ proc equiv_opt -assert opt design -load postopt select -assert-count 1 t:$dffe r:WIDTH=2 %i -select -assert-count 0 t:$dffe %% t:* %D t:$input_port %d +select -assert-count 0 t:$dffe %% t:* %D t:$*_port %d t:$public %d #################### @@ -25,7 +25,7 @@ equiv_opt -assert opt design -load postopt wreduce select -assert-count 1 t:$dffe r:WIDTH=2 %i -select -assert-count 0 t:$dffe %% t:* %D t:$input_port %d +select -assert-count 0 t:$dffe %% t:* %D t:$*_port %d t:$public %d ################### @@ -40,7 +40,7 @@ proc equiv_opt -assert opt design -load postopt select -assert-count 1 t:$dffe r:WIDTH=2 %i -select -assert-count 0 t:$dffe %% t:* %D t:$input_port %d +select -assert-count 0 t:$dffe %% t:* %D t:$*_port %d t:$public %d ################### @@ -56,7 +56,7 @@ equiv_opt -assert opt design -load postopt dump select -assert-count 1 t:$dffe r:WIDTH=4 %i -select -assert-count 0 t:$dffe %% t:* %D t:$input_port %d +select -assert-count 0 t:$dffe %% t:* %D t:$*_port %d t:$public %d #################### @@ -72,7 +72,7 @@ equiv_opt -assert opt design -load postopt wreduce select -assert-count 1 t:$sdffe r:WIDTH=2 %i -select -assert-count 0 t:$sdffe %% t:* %D t:$input_port %d +select -assert-count 0 t:$sdffe %% t:* %D t:$*_port %d t:$public %d #################### @@ -91,7 +91,7 @@ equiv_opt -assert opt design -load postopt wreduce select -assert-count 1 t:$sdffe r:WIDTH=2 %i -select -assert-count 0 t:$sdffe %% t:* %D t:$input_port %d +select -assert-count 0 t:$sdffe %% t:* %D t:$*_port %d t:$public %d #################### @@ -127,4 +127,4 @@ sat -tempinduct -verify -prove-asserts -show-ports miter design -load gate select -assert-count 1 t:$sdffe r:WIDTH=3 %i -select -assert-count 0 t:$sdffe %% t:* %D t:$input_port %d +select -assert-count 0 t:$sdffe %% t:* %D t:$*_port %d t:$public %d diff --git a/tests/opt/opt_expr_alu.ys b/tests/opt/opt_expr_alu.ys index b508b2257..aecee0d76 100644 --- a/tests/opt/opt_expr_alu.ys +++ b/tests/opt/opt_expr_alu.ys @@ -8,7 +8,7 @@ alumacc equiv_opt -assert opt_expr -fine design -load postopt select -assert-count 1 t:$pos -select -assert-none t:$pos t:* %D t:$input_port %d +select -assert-none t:$pos t:* %D t:$*_port %d t:$public %d design -reset @@ -20,7 +20,7 @@ EOT alumacc select -assert-count 1 t:$alu -select -assert-none t:$alu t:* %D t:$input_port %d +select -assert-none t:$alu t:* %D t:$*_port %d t:$public %d design -reset @@ -33,7 +33,7 @@ EOT equiv_opt -assert opt_expr -fine design -load postopt select -assert-count 1 t:$pos -select -assert-none t:$pos t:* %D t:$input_port %d +select -assert-none t:$pos t:* %D t:$*_port %d t:$public %d design -reset @@ -46,7 +46,7 @@ EOT equiv_opt -assert opt_expr -fine design -load postopt select -assert-count 1 t:$pos -select -assert-none t:$pos t:* %D t:$input_port %d +select -assert-none t:$pos t:* %D t:$*_port %d t:$public %d design -reset @@ -60,7 +60,7 @@ alumacc equiv_opt -assert opt_expr -fine design -load postopt select -assert-count 1 t:$not -select -assert-none t:$not %% t:* %D t:$input_port %d +select -assert-none t:$not %% t:* %D t:$*_port %d t:$public %d design -reset @@ -76,7 +76,7 @@ design -load postopt select -assert-count 1 t:$alu select -assert-count 1 t:$alu r:Y_WIDTH=3 %i select -assert-count 1 t:$not -select -assert-none t:$alu t:$not t:* %D %D t:$input_port %d +select -assert-none t:$alu t:$not t:* %D %D t:$*_port %d t:$public %d design -reset @@ -93,7 +93,7 @@ dump select -assert-count 2 t:$alu select -assert-count 1 t:$alu r:Y_WIDTH=2 %i select -assert-count 1 t:$alu r:Y_WIDTH=3 %i -select -assert-none t:$alu t:* %D t:$input_port %d +select -assert-none t:$alu t:* %D t:$*_port %d t:$public %d design -reset @@ -108,7 +108,7 @@ equiv_opt -assert opt -fine design -load postopt select -assert-count 2 t:$alu select -assert-count 2 t:$alu r:Y_WIDTH=3 %i -select -assert-none t:$alu t:* %D t:$input_port %d +select -assert-none t:$alu t:* %D t:$*_port %d t:$public %d design -reset diff --git a/tests/opt/opt_expr_and.ys b/tests/opt/opt_expr_and.ys index c3df09e91..780b8c6a0 100644 --- a/tests/opt/opt_expr_and.ys +++ b/tests/opt/opt_expr_and.ys @@ -12,12 +12,12 @@ copy gold fine_keepdc cd coarse opt_expr -select -assert-none c:* t:$input_port %d +select -assert-none c:* t:$*_port %d t:$public %d cd fine simplemap opt_expr -select -assert-none c:* t:$input_port %d +select -assert-none c:* t:$*_port %d t:$public %d cd miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold coarse miter @@ -27,12 +27,12 @@ sat -verify -prove-asserts -show-ports -enable_undef miter2 cd coarse_keepdc opt_expr -keepdc -select -assert-count 1 c:* t:$input_port %d +select -assert-count 1 c:* t:$*_port %d t:$public %d cd fine_keepdc simplemap opt_expr -keepdc -select -assert-count 1 c:* t:$input_port %d +select -assert-count 1 c:* t:$*_port %d t:$public %d cd miter -equiv -flatten -make_assert -make_outputs gold coarse_keepdc miter3 @@ -56,12 +56,12 @@ copy gold fine_keepdc cd coarse opt_expr -fine -select -assert-none c:* t:$input_port %d +select -assert-none c:* t:$*_port %d t:$public %d cd fine simplemap opt_expr -select -assert-none c:* t:$input_port %d +select -assert-none c:* t:$*_port %d t:$public %d cd miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold coarse miter @@ -71,12 +71,12 @@ sat -verify -prove-asserts -show-ports -enable_undef miter2 cd coarse_keepdc opt_expr -fine -keepdc -select -assert-count 1 c:* t:$input_port %d +select -assert-count 1 c:* t:$*_port %d t:$public %d cd fine_keepdc simplemap opt_expr -keepdc -select -assert-count 2 c:* t:$input_port %d +select -assert-count 2 c:* t:$*_port %d t:$public %d cd miter -equiv -flatten -make_assert -make_outputs gold coarse_keepdc miter3 diff --git a/tests/opt/opt_expr_more.ys b/tests/opt/opt_expr_more.ys index 20b4e0130..e211d88f2 100644 --- a/tests/opt/opt_expr_more.ys +++ b/tests/opt/opt_expr_more.ys @@ -50,7 +50,7 @@ opt_expr -fine # The division by zero should be removed select -assert-count 0 t:$div # No cells should be left as it's replaced with constant undef -select -assert-none t:* t:$input_port %d +select -assert-none t:* t:$*_port %d t:$public %d design -reset read_verilog <