mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-19 13:45:48 +00:00
Code Activity

WIP

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-05-29 11:59:27 +02:00
parent dab9a386cc
commit c3457e2e5c
35 changed files with 204 additions and 63 deletions
Download patch file Download diff file Expand all files Collapse all files

5
passes/techmap/arith_tree.cc
View file

@ -29,11 +29,14 @@ struct Traversal {
dict<SigBit, int> fanout;
Traversal(Module *module) : sigmap(module)
{
for (auto cell : module->cells())
for (auto cell : module->cells()) {
if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
continue;
for (auto &conn : cell->connections())
if (cell->input(conn.first))
for (auto bit : sigmap(conn.second))
bit_consumers[bit].insert(cell);
}
for (auto &pair : bit_consumers)
fanout[pair.first] = pair.second.size();