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This commit is contained in:
Emil J. Tywoniak 2026-05-29 11:59:27 +02:00
parent dab9a386cc
commit c3457e2e5c
35 changed files with 204 additions and 63 deletions
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14
passes/opt/opt_clean/cells_temp.cc
View file

@ -50,9 +50,9 @@ bool trim_buf(RTLIL::Cell* cell, ShardedVector<RTLIL::SigSig>& new_connections,
}
bool remove(ShardedVector<RTLIL::Cell*>& cells, RTLIL::Module* mod, bool verbose) {
// Removing $connect and $input_port doesn't count as "doing something"
// since they get rebuilt in signorm
// and don't enable further opt
// Removing $connect, $input_port, $output_port and $public doesn't count
// as "doing something" since they get rebuilt in signorm and don't enable
// further opt
bool did_something = false;
for (RTLIL::Cell *cell : cells) {
if (verbose) {
@ -62,6 +62,12 @@ bool remove(ShardedVector<RTLIL::Cell*>& cells, RTLIL::Module* mod, bool verbose
} else if (cell->type == ID($input_port)) {
log_debug(" removing input port marker cell `%s': %s\n", cell->name,
log_signal(cell->getPort(ID::Y)));
} else if (cell->type == ID($output_port)) {
log_debug(" removing output port marker cell `%s': %s\n", cell->name,
log_signal(cell->getPort(ID::A)));
} else if (cell->type == ID($public)) {
log_debug(" removing public wire marker cell `%s': %s\n", cell->name,
log_signal(cell->getPort(ID::A)));
} else {
did_something = true;
log_debug(" removing buffer cell `%s': %s = %s\n", cell->name,
@ -93,7 +99,7 @@ void remove_temporary_cells(RTLIL::Module *module, ParallelDispatchThreadPool::S
std::swap(a, b);
new_connections.insert(ctx, {a, b});
delcells.insert(ctx, cell);
} else if (cell->type.in(ID($input_port)) && !cell->has_keep_attr()) {
} else if (cell->type.in(ID($input_port), ID($output_port), ID($public)) && !cell->has_keep_attr()) {
delcells.insert(ctx, cell);
}
}

2
passes/opt/opt_merge_inc.cc
View file

@ -52,6 +52,8 @@ static constexpr MergeableTypes build_mergeable_types(bool nomux) {
c.set_id(ID($allconst), false);
c.set_id(ID($connect), false);
c.set_id(ID($input_port), false);
c.set_id(ID($output_port), false);
c.set_id(ID($public), false);
if (nomux) {
c.set_id(ID($mux), false);
c.set_id(ID($pmux), false);

5
passes/opt/opt_share.cc
View file

@ -363,10 +363,13 @@ struct OptSharePass : public Pass {
dict<RTLIL::SigBit, int> bit_users;
for (auto cell : module->cells())
for (auto cell : module->cells()) {
if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
continue;
for (auto conn : cell->connections())
for (auto bit : conn.second)
bit_users[sigmap(bit)]++;
}
for (auto wire : module->wires())
if (wire->port_id != 0)