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This commit is contained in:
Emil J. Tywoniak 2026-05-29 11:59:27 +02:00
parent dab9a386cc
commit c3457e2e5c
35 changed files with 204 additions and 63 deletions
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2
backends/aiger/aiger.cc
View file

@ -337,7 +337,7 @@ struct AigerWriter
continue;
}
if (cell->type == ID($scopeinfo) || cell->type == ID($input_port))
if (cell->type.in(ID($scopeinfo), ID($input_port), ID($output_port), ID($public)))
continue;
log_error("Unsupported cell type: %s (%s)\n", cell->type.unescape(), cell);

2
backends/aiger2/aiger.cc
View file

@ -109,7 +109,7 @@ struct Index {
int pos = index_wires(info, m);
for (auto cell : m->cells()) {
if (known_ops(cell->type) || cell->type.in(ID($scopeinfo), ID($specify2), ID($specify3), ID($input_port)))
if (known_ops(cell->type) || cell->type.in(ID($scopeinfo), ID($specify2), ID($specify3), ID($input_port), ID($output_port), ID($public)))
continue;
Module *submodule = m->design->module(cell->type);

2
backends/cxxrtl/cxxrtl_backend.cc
View file

@ -1518,7 +1518,7 @@ struct CxxrtlWorker {
f << (cell->getParam(ID::CLR_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
}
// Internal cells
} else if (cell->type == ID($input_port)) {
} else if (cell->type.in(ID($input_port), ID($output_port), ID($public))) {
} else if (is_internal_cell(cell->type)) {
log_cmd_error("Unsupported internal cell `%s'.\n", cell->type);
// User cells

2
backends/verilog/verilog_backend.cc
View file

@ -1542,7 +1542,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}
if (cell->type == ID($input_port))
if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
return true;
if (cell->type == ID($connect))