mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-09-02 00:00:44 +00:00
Code Activity

fix test setup for synth_quicklogic memory tests

Browse source
This commit is contained in:
N. Engelhardt 2023-12-01 14:03:07 +01:00
parent 190cbd54b1
commit c2fc33f0eb
3 changed files with 7 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

2
tests/arch/quicklogic/qlf_k6n10f/mem_tb.v
View file

@ -8,7 +8,7 @@ parameter DATA_WIDTH_A = DATA_WIDTH;
parameter DATA_WIDTH_B = DATA_WIDTH;
parameter VECTORLEN = 16;
parameter SHIFT_VAL = 0;
localparam MAX_WIDTH = 36;
localparam MAX_WIDTH = DATA_WIDTH;
reg rce_a_testvector [VECTORLEN-1:0];
reg [ADDRESS_WIDTH_A-1:0] ra_a_testvector [VECTORLEN-1:0];