From c2fc33f0eb975ff40e4e77d00d23a2700045dd7f Mon Sep 17 00:00:00 2001
From: "N. Engelhardt" <nak@yosyshq.com>
Date: Fri, 1 Dec 2023 14:03:07 +0100
Subject: [PATCH] fix test setup for synth_quicklogic memory tests

---
 tests/arch/quicklogic/qlf_k6n10f/gen_memories.py | 8 +++++---
 tests/arch/quicklogic/qlf_k6n10f/mem_tb.v        | 2 +-
 tests/arch/quicklogic/qlf_k6n10f/run-test.sh     | 2 +-
 3 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py
index 3d74c8b97..1d596b3c7 100644
--- a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py
+++ b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py
@@ -4,12 +4,11 @@ from dataclasses import dataclass
 
 
 blockram_template = """# ======================================
-log ** TESTING {top} WITH PARAMS{param_str}
+log ** GENERATING TEST {top} WITH PARAMS{param_str}
 design -reset; read_verilog -defer ../../common/blockram.v
 chparam{param_str} {top}
 hierarchy -top {top}
 synth_quicklogic -family qlf_k6n10f -top {top}
-design -stash synthesized
 """
 blockram_tests: "list[tuple[list[tuple[str, int]], str, list[str]]]" = [
     # TDP36K = 1024x36bit RAM, 2048x18bit or 4096x9bit also work
@@ -104,6 +103,7 @@ blockram_tests: "list[tuple[list[tuple[str, int]], str, list[str]]]" = [
 ]
 
 sim_template = """\
+design -stash synthesized
 design -copy-from synthesized -as {top}_synth {top}
 design -delete synthesized
 read_verilog +/quicklogic/common/cells_sim.v +/quicklogic/qlf_k6n10f/cells_sim.v +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
@@ -117,6 +117,7 @@ read_verilog -defer -formal mem_tb.v
 chparam{param_str} -set VECTORLEN {vectorlen} TB
 hierarchy -top TB -check
 prep
+log ** CHECKING SIMULATION FOR TEST {top} WITH PARAMS{param_str}
 sim -clock clk -n {vectorlen} -assert
 """
 
@@ -179,7 +180,7 @@ double_sync_ram_sdp_synth uut (\\
 	.address_in_w_a(wa_a),\\
 	.address_in_r_a(ra_a),\\
 	.data_in_a(wd_a),\\
-	.data_out_b(rq_b),\\
+	.data_out_a(rq_a),\\
 	.clk_b(clk),\\
 	.write_enable_b(wce_b),\\
 	.address_in_w_b(wa_b),\\
@@ -401,6 +402,7 @@ for sim_test in sim_tests:
             file=f
         )
         for assertion in sim_test.assertions:
+            print("log ** CHECKING CELL COUNTS FOR TEST {top} WITH PARAMS{param_str}".format(param_str=param_str, top=top), file=f)
             print("select {}".format(assertion), file=f)
         print("", file=f)
 
diff --git a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v
index cb64269a1..89e41f8bc 100644
--- a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v
+++ b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v
@@ -8,7 +8,7 @@ parameter DATA_WIDTH_A = DATA_WIDTH;
 parameter DATA_WIDTH_B = DATA_WIDTH;
 parameter VECTORLEN = 16;
 parameter SHIFT_VAL = 0;
-localparam MAX_WIDTH = 36;
+localparam MAX_WIDTH = DATA_WIDTH;
 
 reg rce_a_testvector [VECTORLEN-1:0];
 reg [ADDRESS_WIDTH_A-1:0] ra_a_testvector [VECTORLEN-1:0];
diff --git a/tests/arch/quicklogic/qlf_k6n10f/run-test.sh b/tests/arch/quicklogic/qlf_k6n10f/run-test.sh
index 73e49b961..be16b7829 100755
--- a/tests/arch/quicklogic/qlf_k6n10f/run-test.sh
+++ b/tests/arch/quicklogic/qlf_k6n10f/run-test.sh
@@ -1,5 +1,5 @@
 #!/usr/bin/env bash
 set -eu
-python3 generate.py
+python3 gen_memories.py
 source ../../../gen-tests-makefile.sh
 run_tests --yosys-scripts --bash