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Merge pull request #1599 from YosysHQ/eddie/retry_1588

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Retry #1588 -- "write_xaiger: only instantiate each whitebox cell type once"
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Eddie Hung 2019-12-30 10:01:02 -08:00 • committed by GitHub
commit c2c74f9bb0
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4 changed files with 87 additions and 20 deletions
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16
tests/arch/ecp5/bug1598.ys Normal file
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read_verilog <<EOT
module led_blink (
input clk,
output ledc
);
reg [6:0] led_counter = 0;
always @( posedge clk ) begin
led_counter <= led_counter + 1;
end
assign ledc = !led_counter[ 6:3 ];
endmodule
EOT
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -abc9

16
tests/arch/ice40/bug1598.ys Normal file
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@ -0,0 +1,16 @@
read_verilog <<EOT
module led_blink (
input clk,
output ledc
);
reg [6:0] led_counter = 0;
always @( posedge clk ) begin
led_counter <= led_counter + 1;
end
assign ledc = !led_counter[ 6:3 ];
endmodule
EOT
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -abc9

16
tests/arch/xilinx/bug1598.ys Normal file
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@ -0,0 +1,16 @@
read_verilog <<EOT
module led_blink (
input clk,
output ledc
);
reg [6:0] led_counter = 0;
always @( posedge clk ) begin
led_counter <= led_counter + 1;
end
assign ledc = !led_counter[ 6:3 ];
endmodule
EOT
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -abc9