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anlogic: support BRAM mapping

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Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being
true dual port (or 18bit*512 when simple dual port), the other is
16bit*2K.

Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and
32Kbit BRAM with 8bit width are not support yet.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
This commit is contained in:
Icenowy Zheng 2021-12-17 20:25:32 +08:00
parent 60c3ea367c
commit c2b7ad3b28
8 changed files with 283 additions and 2 deletions
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21
techlibs/anlogic/brams_init.py Normal file
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#!/usr/bin/env python3
with open("techlibs/anlogic/brams_init_9.vh", "w") as f:
for i in range(4):
init_snippets = [" INIT[%3d*9+8]" % (k+256*i,) for k in range(255, -1, -1)]
for k in range(4, 256, 4):
init_snippets[k] = "\n " + init_snippets[k]
print(".INITP_%02X({%s})," % (i, ",".join(init_snippets)), file=f)
for i in range(32):
init_snippets = [" INIT[%3d*9 +: 8]" % (k+32*i,) for k in range(31, -1, -1)]
for k in range(4, 32, 4):
init_snippets[k] = "\n " + init_snippets[k]
print(".INIT_%02X({%s})," % (i, ",".join(init_snippets)), file=f)
with open("techlibs/anlogic/brams_init_8.vh", "w") as f:
for i in range(32):
print(".INIT_%02X(INIT[%3d*256 +: 256])," % (i, i), file=f)
with open("techlibs/anlogic/brams_init_16.vh", "w") as f:
for i in range(128):
print(".INIT_%02X(INIT[%3d*256 +: 256])," % (i, i), file=f)