mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity

Minor refactor

Browse source
This commit is contained in:
Eddie Hung 2019-08-20 14:47:58 -07:00
parent 0079e9b4a6
commit c00d72cdb3
1 changed files with 6 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

13
backends/aiger/xaiger.cc
View file

@ -331,14 +331,15 @@ struct XAigerWriter
}
for (const auto &conn : cell->connections()) {
if (cell->input(conn.first)) {
auto port_wire = inst_module->wire(conn.first);
if (port_wire->port_input) {
// Ignore inout for the sake of topographical ordering
if (cell->output(conn.first)) continue;
if (port_wire->port_output) continue;
for (auto bit : sigmap(conn.second))
bit_users[bit].insert(cell->name);
}
if (cell->output(conn.first))
if (port_wire->port_output)
for (auto bit : sigmap(conn.second))
bit_drivers[bit].insert(cell->name);
}
@ -354,7 +355,7 @@ struct XAigerWriter
log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
if (is_input) {
for (auto b : c.second.bits()) {
for (auto b : sigmap(c.second)) {
Wire *w = b.wire;
if (!w) continue;
if (!w->port_output || !cell_known) {
@ -380,7 +381,7 @@ struct XAigerWriter
}
}
for (auto b : c.second.bits()) {
for (auto b : sigmap(c.second)) {
Wire *w = b.wire;
if (!w) continue;
input_bits.insert(b);
@ -393,8 +394,6 @@ struct XAigerWriter
arrival_times[b] = arrival;
}
}
}
}