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WIP migration to twine

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This commit is contained in:
Emil J. Tywoniak 2026-06-18 21:54:57 +02:00
parent 0c450ce8c8
commit bffe7a6e57
7 changed files with 62 additions and 32 deletions
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11
frontends/ast/ast.cc
View file

@ -1484,7 +1484,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
if (defer_local)
child->str = "$abstract" + child->str;
TwineRef mod_name = TwineSearch(&design->twines).find(child->str);
TwineRef mod_name = design->twines.find(child->str);
if (design->has(mod_name)) {
RTLIL::Module *existing_mod = design->module(mod_name);
if (!nooverwrite && !overwrite && !existing_mod->get_blackbox_attribute()) {
@ -1720,11 +1720,10 @@ TwineRef AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RT
if (has_interfaces)
new_modname += "$interfaces$" + interf_info;
TwineSearch search(&design->twines);
TwineRef new_modname_ref = search.find(new_modname);
TwineRef new_modname_ref = design->twines.find(new_modname);
if (!design->has(new_modname_ref)) {
if (!new_ast) {
TwineRef modname_ref = search.find(modname);
TwineRef modname_ref = design->twines.find(modname);
auto mod = dynamic_cast<AstModule*>(design->module(modname_ref));
new_ast = mod->ast->clone();
}
@ -1748,7 +1747,7 @@ TwineRef AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RT
}
process_module(design, new_ast.get(), false);
TwineRef new_ref = TwineSearch(&design->twines).find(modname);
TwineRef new_ref = design->twines.find(modname);
design->module(new_ref)->check();
RTLIL::Module* mod = design->module(new_ref);
@ -1872,7 +1871,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
if (parameters.size()) // not named_parameters to cover hierarchical defparams
modname = derived_module_name(stripped_name, named_parameters);
if (design->has(TwineSearch(&design->twines).find(modname)))
if (design->has(design->twines.find(modname)))
return modname;
if (!quiet)

21
frontends/ast/genrtlil.cc
View file

@ -178,7 +178,7 @@ static void check_unique_id(RTLIL::Module *module, RTLIL::IdString id,
to_add_kind, id.c_str(), existing_kind, location_str.c_str());
};
TwineRef id_tw = TwineSearch(&module->design->twines).find(id.str());
TwineRef id_tw = module->design->twines.find(id.str());
if (const RTLIL::Wire *wire = module->wire(id_tw))
already_exists(wire, "signal");
if (const RTLIL::Cell *cell = module->cell(id_tw))
@ -500,13 +500,12 @@ struct AST_INTERNAL::ProcessGenerator
continue;
std::string wire_name;
TwineSearch search(&current_module->design->twines);
do {
wire_name = stringf("$%d%s[%d:%d]", new_temp_count[chunk.wire]++,
chunk.wire->name, chunk.width+chunk.offset-1, chunk.offset);;
if (chunk.wire->name.str().find('$') != std::string::npos)
wire_name += stringf("$%d", autoidx++);
} while (current_module->wire(search.find(wire_name)) != nullptr);
} while (current_module->wire(current_module->design->twines.find(wire_name)) != nullptr);
RTLIL::Wire *wire = current_module->addWire(current_module->design->twines.add(std::string{wire_name}), chunk.width);
set_src_attr(wire, always.get());
@ -985,7 +984,8 @@ struct AST_INTERNAL::ProcessGenerator
set_src_attr(&action, child.get());
action.memid = memid;
action.address = child->children[0]->genWidthRTLIL(-1, true, &subst_rvalue_map.stdmap());
action.data = child->children[1]->genWidthRTLIL(current_module->memories[TwineSearch(&current_module->design->twines).find(memid)]->width, true, &subst_rvalue_map.stdmap());
TwineRef memid_tw = current_module->design->twines.find(memid);
action.data = child->children[1]->genWidthRTLIL(current_module->memories[memid_tw]->width, true, &subst_rvalue_map.stdmap());
action.enable = child->children[2]->genWidthRTLIL(-1, true, &subst_rvalue_map.stdmap());
RTLIL::Const orig_priority_mask = child->children[4]->bitsAsConst();
RTLIL::Const priority_mask = RTLIL::Const(0, cur_idx);
@ -1629,8 +1629,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
log_assert(id2ast != nullptr);
TwineSearch search(&current_module->design->twines);
TwineRef str_ref = search.find(str);
TwineRef str_ref = current_module->design->twines.find(str);
if (id2ast->type == AST_AUTOWIRE && current_module->wire(str_ref) == nullptr) {
RTLIL::Wire *wire = current_module->addWire(current_module->design->twines.add(std::string{str}));
@ -1677,7 +1676,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// with the individual signals:
if (is_interface) {
IdString dummy_wire_name = stringf("$dummywireforinterface%s", str);
RTLIL::Wire *dummy_wire = current_module->wire(search.find(dummy_wire_name.str()));
RTLIL::Wire *dummy_wire = current_module->wire(current_module->design->twines.find(dummy_wire_name.str()));
if (!dummy_wire) {
dummy_wire = current_module->addWire(current_module->design->twines.add(std::string{dummy_wire_name.str()}));
dummy_wire->set_bool_attribute(ID::is_interface);
@ -2052,7 +2051,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
RTLIL::Cell *cell = current_module->addCell(current_module->design->twines.add(std::string{sstr.str()}), TW::$memrd);
set_src_attr(cell, this);
RTLIL::Wire *wire = current_module->addWire(current_module->design->twines.add(std::string{cell->name.str() + "_DATA"}), current_module->memories[TwineSearch(&current_module->design->twines).find(str)]->width);
TwineRef mem_tw = current_module->design->twines.find(str);
RTLIL::Wire *wire = current_module->addWire(current_module->design->twines.add(std::string{cell->name.str() + "_DATA"}), current_module->memories[mem_tw]->width);
set_src_attr(wire, this);
int mem_width, mem_size, addr_bits;
@ -2102,13 +2102,14 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
SigSpec addr_sig = children[0]->genRTLIL();
TwineRef mem_tw = current_module->design->twines.find(str);
cell->setPort(TW::ADDR, addr_sig);
cell->setPort(TW::DATA, children[1]->genWidthRTLIL(current_module->memories[TwineSearch(&current_module->design->twines).find(str)]->width * num_words, true));
cell->setPort(TW::DATA, children[1]->genWidthRTLIL(current_module->memories[mem_tw]->width * num_words, true));
cell->setPort(TW::EN, en_sig);
cell->parameters[ID::MEMID] = RTLIL::Const(str);
cell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr_sig));
cell->parameters[ID::WIDTH] = RTLIL::Const(current_module->memories[TwineSearch(&current_module->design->twines).find(str)]->width);
cell->parameters[ID::WIDTH] = RTLIL::Const(current_module->memories[mem_tw]->width);
cell->parameters[ID::PRIORITY] = RTLIL::Const(autoidx-1);
}