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Convert svinterfaces

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This commit is contained in:
Miodrag Milanovic 2026-03-24 12:31:45 +01:00
parent 2811131d8a
commit bfa1a8ab41
5 changed files with 47 additions and 69 deletions
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2
tests/Makefile
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@ -62,7 +62,7 @@ MK_TEST_DIRS += ./opt_share
MK_TEST_DIRS += ./fsm
MK_TEST_DIRS += ./memlib
MK_TEST_DIRS += ./bram
#SH_TEST_DIRS += ./svinterfaces
MK_TEST_DIRS += ./svinterfaces
MK_TEST_DIRS += ./xprop
MK_TEST_DIRS += ./select
MK_TEST_DIRS += ./peepopt

46
tests/svinterfaces/generate_mk.py Normal file
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@ -0,0 +1,46 @@
#!/usr/bin/env python3
from pathlib import Path
import glob
import sys
sys.path.append("..")
import gen_tests_makefile
runone_tests = [
"svinterface1",
"svinterface_at_top"
]
def run_one():
for testname in runone_tests:
cmd_lines = [
f'../../yosys -p "read_verilog -sv {testname}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog {testname}_syn.v" >> {testname}.log_stdout 2>> {testname}.log_stderr;',
f'../../yosys -p "read_verilog -sv {testname}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog {testname}_ref_syn.v" >> {testname}.log_stdout 2>> {testname}.log_stderr;',
f'rm -f a.out reference_result.txt dut_result.txt;',
f'iverilog -g2012 {testname}_syn.v >/dev/null 2>&1;',
f'iverilog -g2012 {testname}_ref_syn.v >/dev/null 2>&1;',
f'iverilog -g2012 {testname}_tb.v {testname}_ref_syn.v >/dev/null 2>&1;',
f'./a.out >/dev/null 2>&1;',
f'mv output.txt reference_result.txt;',
f'iverilog -g2012 {testname}_tb_wrapper.v {testname}_syn.v >/dev/null 2>&1;' if testname=="svinterface_at_top" else
f'iverilog -g2012 {testname}_tb.v {testname}_syn.v >/dev/null 2>&1;',
f'./a.out >/dev/null 2>&1;',
f'mv output.txt dut_result.txt;',
f'diff reference_result.txt dut_result.txt > {testname}.diff',
]
gen_tests_makefile.generate_cmd_test(testname, cmd_lines)
def run_simple():
for f in sorted(glob.glob("*.ys")):
gen_tests_makefile.generate_ys_test(f)
def main():
def callback():
run_one()
run_simple()
gen_tests_makefile.generate_custom(callback)
if __name__ == "__main__":
main()

9
tests/svinterfaces/run-test.sh
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@ -1,9 +0,0 @@
#/bin/bash -e
source ../common-env.sh
./runone.sh svinterface1
./runone.sh svinterface_at_top
./run_simple.sh load_and_derive
./run_simple.sh resolve_types
./run_simple.sh positional_args

15
tests/svinterfaces/run_simple.sh
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@ -1,15 +0,0 @@
#!/usr/bin/env bash
# Run a simple test with a .ys file
if [ $# != 1 ]; then
echo >&2 "Expected 1 argument"
exit 1
fi
echo -n "Test: $1 ->"
../../yosys $1.ys >$1.log_stdout 2>$1.log_stderr || {
echo "ERROR!"
exit 1
}
echo "ok"

44
tests/svinterfaces/runone.sh
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@ -1,44 +0,0 @@
#!/usr/bin/env bash
TESTNAME=$1
STDOUTFILE=${TESTNAME}.log_stdout
STDERRFILE=${TESTNAME}.log_stderr
echo "" > $STDOUTFILE
echo "" > $STDERRFILE
echo -n "Test: ${TESTNAME} -> "
set -e
$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_syn.v" >> $STDOUTFILE 2>> $STDERRFILE
$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_ref_syn.v" >> $STDOUTFILE 2>> $STDERRFILE
rm -f a.out reference_result.txt dut_result.txt
iverilog -g2012 ${TESTNAME}_syn.v >/dev/null 2>&1
iverilog -g2012 ${TESTNAME}_ref_syn.v >/dev/null 2>&1
set +e
iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_ref_syn.v >/dev/null 2>&1
./a.out >/dev/null 2>&1
mv output.txt reference_result.txt
if [ -f ${TESTNAME}_wrapper.v ] ; then
iverilog -g2012 ${TESTNAME}_tb_wrapper.v ${TESTNAME}_syn.v >/dev/null 2>&1
else
iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_syn.v >/dev/null 2>&1
fi
./a.out >/dev/null 2>&1
mv output.txt dut_result.txt
diff reference_result.txt dut_result.txt > ${TESTNAME}.diff
RET=$?
if [ "$RET" != "0" ] ; then
echo "ERROR!"
exit -1
fi
echo "ok"
exit 0