mirror of
https://github.com/YosysHQ/yosys
synced 2026-03-26 14:25:47 +00:00
Convert arch
This commit is contained in:
parent
1826a66638
commit
2811131d8a
3 changed files with 53 additions and 31 deletions
|
|
@ -68,7 +68,7 @@ MK_TEST_DIRS += ./select
|
|||
MK_TEST_DIRS += ./peepopt
|
||||
MK_TEST_DIRS += ./proc
|
||||
MK_TEST_DIRS += ./blif
|
||||
#SH_TEST_DIRS += ./arch
|
||||
MK_TEST_DIRS += ./arch
|
||||
MK_TEST_DIRS += ./rpc
|
||||
MK_TEST_DIRS += ./memfile
|
||||
#SH_TEST_DIRS += ./fmt
|
||||
|
|
|
|||
52
tests/arch/generate_mk.py
Normal file
52
tests/arch/generate_mk.py
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
from pathlib import Path
|
||||
import sys
|
||||
sys.path.append("..")
|
||||
|
||||
import gen_tests_makefile
|
||||
|
||||
techlibs_dir = Path("../../techlibs")
|
||||
|
||||
# Architecture-specific defines
|
||||
defines = {
|
||||
"ice40": ["ICE40_HX", "ICE40_LP", "ICE40_U"]
|
||||
}
|
||||
|
||||
def archs():
|
||||
# Loop over architectures
|
||||
for arch in techlibs_dir.iterdir():
|
||||
if not arch.is_dir():
|
||||
continue
|
||||
arch_name = arch.name
|
||||
|
||||
for path in arch.rglob("cells_sim.v"):
|
||||
rel_parts = path.relative_to(techlibs_dir).parts
|
||||
target_base = "_".join(rel_parts[-len(rel_parts):]).replace(".v", "")
|
||||
path_str = str(path)
|
||||
if arch_name in defines:
|
||||
for defn in defines[arch_name]:
|
||||
target_name = f"{target_base}_{defn}"
|
||||
cmd = f"iverilog -t null -I{arch} -D{defn} -DNO_ICE40_DEFAULT_ASSIGNMENTS {path_str} >/dev/null 2>&1"
|
||||
gen_tests_makefile.generate_target(target_name, cmd)
|
||||
else:
|
||||
target_name = f"{target_base}"
|
||||
cmd = f"iverilog -t null -I{arch} -g2005-sv {path_str} >/dev/null 2>&1"
|
||||
gen_tests_makefile.generate_target(target_name, cmd)
|
||||
|
||||
def common():
|
||||
for path in ["../../techlibs/common/simcells.v", "../../techlibs/common/simlib.v"]:
|
||||
path_obj = Path(path)
|
||||
target_name = path_obj.stem
|
||||
cmd = f"iverilog -t null {path} >/dev/null 2>&1"
|
||||
gen_tests_makefile.generate_target(target_name, cmd)
|
||||
|
||||
def main():
|
||||
def callback():
|
||||
archs()
|
||||
common()
|
||||
|
||||
gen_tests_makefile.generate_custom(callback)
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
@ -1,30 +0,0 @@
|
|||
#!/usr/bin/env bash
|
||||
source ../common-env.sh
|
||||
|
||||
set -e
|
||||
|
||||
declare -A defines=( ["ice40"]="ICE40_HX ICE40_LP ICE40_U" )
|
||||
|
||||
echo "Running syntax check on arch sim models"
|
||||
for arch in ../../techlibs/*; do
|
||||
find $arch -name cells_sim.v | while read path; do
|
||||
arch_name=$(basename -- $arch)
|
||||
if [ "${defines[$arch_name]}" ]; then
|
||||
for def in ${defines[$arch_name]}; do
|
||||
echo -n "Test $path -D$def ->"
|
||||
iverilog -t null -I$arch -D$def -DNO_ICE40_DEFAULT_ASSIGNMENTS $path >/dev/null 2>&1
|
||||
echo " ok"
|
||||
done
|
||||
else
|
||||
echo -n "Test $path ->"
|
||||
iverilog -t null -I$arch -g2005-sv $path >/dev/null 2>&1
|
||||
echo " ok"
|
||||
fi
|
||||
done
|
||||
done
|
||||
|
||||
for path in "../../techlibs/common/simcells.v" "../../techlibs/common/simlib.v"; do
|
||||
echo -n "Test $path ->"
|
||||
iverilog -t null $path >/dev/null 2>&1
|
||||
echo " ok"
|
||||
done
|
||||
Loading…
Add table
Add a link
Reference in a new issue