mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-23 17:15:33 +00:00
proc_clean: only consider fully-defined case operands.
This commit is contained in:
parent
40978971f4
commit
bf84861fc2
2 changed files with 23 additions and 1 deletions
|
@ -41,7 +41,7 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did
|
|||
break;
|
||||
for (int j = 0; j < int(cs->compare.size()); j++) {
|
||||
RTLIL::SigSpec &val = cs->compare[j];
|
||||
if (!val.is_fully_const())
|
||||
if (!val.is_fully_def())
|
||||
continue;
|
||||
if (val == sw->signal) {
|
||||
cs->compare.clear();
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue