mirror of
https://github.com/YosysHQ/yosys
synced 2025-09-13 05:01:29 +00:00
Update passes/tests to avoid bits()
This commit is contained in:
parent
a8cc9202b9
commit
bebd10377b
1 changed files with 4 additions and 3 deletions
|
@ -641,15 +641,16 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
|
|||
if (!gold_wire->port_input)
|
||||
continue;
|
||||
|
||||
RTLIL::Const in_value;
|
||||
RTLIL::Const::Builder in_value_builder(GetSize(gold_wire));
|
||||
for (int i = 0; i < GetSize(gold_wire); i++)
|
||||
in_value.bits().push_back(xorshift32(2) ? State::S1 : State::S0);
|
||||
in_value_builder.push_back(xorshift32(2) ? State::S1 : State::S0);
|
||||
RTLIL::Const in_value = in_value_builder.build();
|
||||
|
||||
if (xorshift32(4) == 0) {
|
||||
int inv_chance = 1 + xorshift32(8);
|
||||
for (int i = 0; i < GetSize(gold_wire); i++)
|
||||
if (xorshift32(inv_chance) == 0)
|
||||
in_value.bits()[i] = RTLIL::Sx;
|
||||
in_value.set(i, RTLIL::Sx);
|
||||
}
|
||||
|
||||
if (verbose)
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue