From bebd10377bcd935b1fc073f27e6fb807a2703137 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 28 Aug 2025 03:54:00 +0000 Subject: [PATCH] Update passes/tests to avoid bits() --- passes/tests/test_cell.cc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 4285611f7..0f6851a9a 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -641,15 +641,16 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std:: if (!gold_wire->port_input) continue; - RTLIL::Const in_value; + RTLIL::Const::Builder in_value_builder(GetSize(gold_wire)); for (int i = 0; i < GetSize(gold_wire); i++) - in_value.bits().push_back(xorshift32(2) ? State::S1 : State::S0); + in_value_builder.push_back(xorshift32(2) ? State::S1 : State::S0); + RTLIL::Const in_value = in_value_builder.build(); if (xorshift32(4) == 0) { int inv_chance = 1 + xorshift32(8); for (int i = 0; i < GetSize(gold_wire); i++) if (xorshift32(inv_chance) == 0) - in_value.bits()[i] = RTLIL::Sx; + in_value.set(i, RTLIL::Sx); } if (verbose)