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https://github.com/YosysHQ/yosys
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parent
2ae7490adf
commit
bd439fc524
15 changed files with 110 additions and 49 deletions
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@ -377,6 +377,13 @@ static void extract_fsm(RTLIL::Wire *wire)
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fsm_cell->setPort(ID::CTRL_OUT, ctrl_out);
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fsm_cell->parameters[ID::NAME] = RTLIL::Const(wire->name.str());
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fsm_cell->attributes = wire->attributes;
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if(fsm_cell->attributes.count(ID::hdlname)) {
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auto hdlname = fsm_cell->get_hdlname_attribute();
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hdlname.pop_back();
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fsm_cell->set_hdlname_attribute(hdlname);
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fsm_cell->set_string_attribute(ID(scopename), fsm_cell->get_string_attribute(ID::hdlname));
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fsm_cell->attributes.erase(ID::hdlname);
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}
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fsm_data.copy_to_cell(fsm_cell);
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// rename original state wire
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@ -385,6 +392,13 @@ static void extract_fsm(RTLIL::Wire *wire)
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wire->attributes.erase(ID::fsm_encoding);
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wire->name = stringf("$fsm$oldstate%s", wire->name.c_str());
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module->wires_[wire->name] = wire;
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if(wire->attributes.count(ID::hdlname)) {
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auto hdlname = wire->get_hdlname_attribute();
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hdlname.pop_back();
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wire->set_hdlname_attribute(hdlname);
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wire->set_string_attribute(ID(scopename), wire->get_string_attribute(ID::hdlname));
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wire->attributes.erase(ID::hdlname);
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}
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// unconnect control outputs from old drivers
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@ -360,6 +360,9 @@ struct FlattenPass : public Pass {
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FlattenWorker worker;
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if (design->scratchpad.count("flatten.separator"))
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worker.separator = design->scratchpad_get_string("flatten.separator");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-wb") {
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