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fix hierarchy -generate mode handling of cells

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This commit is contained in:
N. Engelhardt 2024-04-12 13:38:33 +02:00
parent 1c09862ad9
commit b87327d1b9
2 changed files with 20 additions and 1 deletions
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2
passes/hierarchy/hierarchy.cc
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@ -47,7 +47,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
{ {
if (design->module(cell->type) != nullptr) if (design->module(cell->type) != nullptr)
continue; continue;
if (cell->type.begins_with("$__")) if (cell->type.begins_with("$") && !cell->type.begins_with("$__"))
continue; continue;
for (auto &pattern : celltypes) for (auto &pattern : celltypes)
if (patmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str())) if (patmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str()))

19
tests/various/hierarchy_generate.ys Normal file
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@ -0,0 +1,19 @@
read_verilog -icells <<EOF
module top(input [2:0] a, input [2:0] b, output [2:0] y);
sub sub_i (.a(a[0]), .b(b[0]), .y(y[0]));
unknown_sub sub_ii (.a(a[1]), .b(b[1]), .y(y[1]));
$__dunder_sub sub_iii (.a(a[2]), .b(b[2]), .y(y[2]));
endmodule
module sub(input a, input b, output y);
assign y = a ^ b;
endmodule
EOF
hierarchy -generate unknown_sub i:a i:b o:y
hierarchy -generate $__dunder_sub i:a i:b o:y
hierarchy -top top -check
check -assert